2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/processor.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define PCI_HOSE_OP(rw, size, type) \
26 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
28 int offset, type value) \
30 return hose->rw##_##size(hose, dev, offset, value); \
33 PCI_HOSE_OP(read, byte, u8 *)
34 PCI_HOSE_OP(read, word, u16 *)
35 PCI_HOSE_OP(read, dword, u32 *)
36 PCI_HOSE_OP(write, byte, u8)
37 PCI_HOSE_OP(write, word, u16)
38 PCI_HOSE_OP(write, dword, u32)
40 #define PCI_OP(rw, size, type, error_code) \
41 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
43 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
51 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
54 PCI_OP(read, byte, u8 *, *value = 0xff)
55 PCI_OP(read, word, u16 *, *value = 0xffff)
56 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
57 PCI_OP(write, byte, u8, )
58 PCI_OP(write, word, u16, )
59 PCI_OP(write, dword, u32, )
61 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
62 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
64 int offset, type val) \
68 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
73 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
78 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
79 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
81 int offset, type val) \
83 u32 val32, mask, ldata, shift; \
85 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
88 shift = ((offset & (int)off_mask) * 8); \
89 ldata = (((unsigned long)val) & val_mask) << shift; \
90 mask = val_mask << shift; \
91 val32 = (val32 & ~mask) | ldata; \
93 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
99 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
100 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
101 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
102 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
104 /* Get a virtual address associated with a BAR region */
105 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
107 pci_addr_t pci_bus_addr;
110 /* read BAR address */
111 pci_read_config_dword(pdev, bar, &bar_response);
112 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
115 * Pass "0" as the length argument to pci_bus_to_virt. The arg
116 * isn't actualy used on any platform because u-boot assumes a static
117 * linear mapping. In the future, this could read the BAR size
118 * and pass that as the size if needed.
120 return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
127 static struct pci_controller* hose_head;
129 struct pci_controller *pci_get_hose_head(void)
137 void pci_register_hose(struct pci_controller* hose)
139 struct pci_controller **phose = &hose_head;
142 phose = &(*phose)->next;
149 struct pci_controller *pci_bus_to_hose(int bus)
151 struct pci_controller *hose;
153 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
154 if (bus >= hose->first_busno && bus <= hose->last_busno)
158 printf("pci_bus_to_hose() failed\n");
162 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
164 struct pci_controller *hose;
166 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
167 if (hose->cfg_addr == cfg_addr)
174 int pci_last_busno(void)
176 struct pci_controller *hose = pci_get_hose_head();
184 return hose->last_busno;
187 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
189 struct pci_controller * hose;
193 int i, bus, found_multi = 0;
195 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
196 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
197 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
199 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
201 for (bdf = PCI_BDF(bus, 0, 0);
202 bdf < PCI_BDF(bus + 1, 0, 0);
203 bdf += PCI_BDF(0, 0, 1)) {
204 if (pci_skip_dev(hose, bdf))
207 if (!PCI_FUNC(bdf)) {
208 pci_read_config_byte(bdf,
212 found_multi = header_type & 0x80;
218 pci_read_config_word(bdf,
221 pci_read_config_word(bdf,
225 for (i = 0; ids[i].vendor != 0; i++) {
226 if (vendor == ids[i].vendor &&
227 device == ids[i].device) {
240 pci_dev_t pci_find_class(uint find_class, int index)
247 for (bus = 0; bus <= pci_last_busno(); bus++) {
248 for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
249 pci_read_config_dword(PCI_BDF(bus, devnum, 0),
250 PCI_CLASS_REVISION, &class);
251 if (class >> 16 == 0xffff)
254 for (bdf = PCI_BDF(bus, devnum, 0);
255 bdf <= PCI_BDF(bus, devnum,
256 PCI_MAX_PCI_FUNCTIONS - 1);
257 bdf += PCI_BDF(0, 0, 1)) {
258 pci_read_config_dword(bdf, PCI_CLASS_REVISION,
262 if (class != find_class)
265 * Decrement the index. We want to return the
266 * correct device, so index is 0 for the first
267 * matching device, 1 for the second, etc.
273 /* Return index'th controller. */
282 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
284 struct pci_device_id ids[2] = { {}, {0, 0} };
286 ids[0].vendor = vendor;
287 ids[0].device = device;
289 return pci_find_devices(ids, index);
296 int __pci_hose_phys_to_bus(struct pci_controller *hose,
297 phys_addr_t phys_addr,
299 unsigned long skip_mask,
302 struct pci_region *res;
306 for (i = 0; i < hose->region_count; i++) {
307 res = &hose->regions[i];
309 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
312 if (res->flags & skip_mask)
315 bus_addr = phys_addr - res->phys_start + res->bus_start;
317 if (bus_addr >= res->bus_start &&
318 bus_addr < res->bus_start + res->size) {
327 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
328 phys_addr_t phys_addr,
331 pci_addr_t bus_addr = 0;
335 puts("pci_hose_phys_to_bus: invalid hose\n");
340 * if PCI_REGION_MEM is set we do a two pass search with preference
341 * on matches that don't have PCI_REGION_SYS_MEMORY set
343 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
344 ret = __pci_hose_phys_to_bus(hose, phys_addr,
345 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
350 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
353 puts("pci_hose_phys_to_bus: invalid physical address\n");
358 int __pci_hose_bus_to_phys(struct pci_controller *hose,
361 unsigned long skip_mask,
364 struct pci_region *res;
367 for (i = 0; i < hose->region_count; i++) {
368 res = &hose->regions[i];
370 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
373 if (res->flags & skip_mask)
376 if (bus_addr >= res->bus_start &&
377 (bus_addr - res->bus_start) < res->size) {
378 *pa = (bus_addr - res->bus_start + res->phys_start);
386 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
390 phys_addr_t phys_addr = 0;
394 puts("pci_hose_bus_to_phys: invalid hose\n");
399 * if PCI_REGION_MEM is set we do a two pass search with preference
400 * on matches that don't have PCI_REGION_SYS_MEMORY set
402 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
403 ret = __pci_hose_bus_to_phys(hose, bus_addr,
404 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
409 ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
412 puts("pci_hose_bus_to_phys: invalid physical address\n");
417 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
422 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
423 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
426 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
431 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
432 pci_hose_read_config_dword(hose, dev, bar, &addr);
433 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
434 return addr & PCI_BASE_ADDRESS_IO_MASK;
436 return addr & PCI_BASE_ADDRESS_MEM_MASK;
439 int pci_hose_config_device(struct pci_controller *hose,
443 unsigned long command)
446 unsigned int old_command;
447 pci_addr_t bar_value;
450 int bar, found_mem64;
452 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
455 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
457 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
458 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
459 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
466 /* Check the BAR type and set our address mask */
467 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
468 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
469 /* round up region base address to a multiple of size */
470 io = ((io - 1) | (bar_size - 1)) + 1;
472 /* compute new region base address */
475 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
476 PCI_BASE_ADDRESS_MEM_TYPE_64) {
477 u32 bar_response_upper;
479 pci_hose_write_config_dword(hose, dev, bar + 4,
481 pci_hose_read_config_dword(hose, dev, bar + 4,
482 &bar_response_upper);
484 bar64 = ((u64)bar_response_upper << 32) | bar_response;
486 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
489 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
492 /* round up region base address to multiple of size */
493 mem = ((mem - 1) | (bar_size - 1)) + 1;
495 /* compute new region base address */
496 mem = mem + bar_size;
499 /* Write it out and update our limit */
500 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
504 #ifdef CONFIG_SYS_PCI_64BIT
505 pci_hose_write_config_dword(hose, dev, bar,
506 (u32)(bar_value >> 32));
508 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
513 /* Configure Cache Line Size Register */
514 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
516 /* Configure Latency Timer */
517 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
519 /* Disable interrupt line, if device says it wants to use interrupts */
520 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
522 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
525 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
526 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
527 (old_command & 0xffff0000) | command);
536 struct pci_config_table *pci_find_config(struct pci_controller *hose,
537 unsigned short class,
544 struct pci_config_table *table;
546 for (table = hose->config_table; table && table->vendor; table++) {
547 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
548 (table->device == PCI_ANY_ID || table->device == device) &&
549 (table->class == PCI_ANY_ID || table->class == class) &&
550 (table->bus == PCI_ANY_ID || table->bus == bus) &&
551 (table->dev == PCI_ANY_ID || table->dev == dev) &&
552 (table->func == PCI_ANY_ID || table->func == func)) {
560 void pci_cfgfunc_config_device(struct pci_controller *hose,
562 struct pci_config_table *entry)
564 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
568 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
569 pci_dev_t dev, struct pci_config_table *entry)
574 * HJF: Changed this to return int. I think this is required
575 * to get the correct result when scanning bridges
577 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
579 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
580 const char * pci_class_str(u8 class)
583 case PCI_CLASS_NOT_DEFINED:
584 return "Build before PCI Rev2.0";
586 case PCI_BASE_CLASS_STORAGE:
587 return "Mass storage controller";
589 case PCI_BASE_CLASS_NETWORK:
590 return "Network controller";
592 case PCI_BASE_CLASS_DISPLAY:
593 return "Display controller";
595 case PCI_BASE_CLASS_MULTIMEDIA:
596 return "Multimedia device";
598 case PCI_BASE_CLASS_MEMORY:
599 return "Memory controller";
601 case PCI_BASE_CLASS_BRIDGE:
602 return "Bridge device";
604 case PCI_BASE_CLASS_COMMUNICATION:
605 return "Simple comm. controller";
607 case PCI_BASE_CLASS_SYSTEM:
608 return "Base system peripheral";
610 case PCI_BASE_CLASS_INPUT:
611 return "Input device";
613 case PCI_BASE_CLASS_DOCKING:
614 return "Docking station";
616 case PCI_BASE_CLASS_PROCESSOR:
619 case PCI_BASE_CLASS_SERIAL:
620 return "Serial bus controller";
622 case PCI_BASE_CLASS_INTELLIGENT:
623 return "Intelligent controller";
625 case PCI_BASE_CLASS_SATELLITE:
626 return "Satellite controller";
628 case PCI_BASE_CLASS_CRYPT:
629 return "Cryptographic device";
631 case PCI_BASE_CLASS_SIGNAL_PROCESSING:
634 case PCI_CLASS_OTHERS:
635 return "Does not fit any class";
642 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
644 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
647 * Check if pci device should be skipped in configuration
649 if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
650 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
652 * Only skip configuration if "pciconfighost" is not set
654 if (getenv("pciconfighost") == NULL)
664 #ifdef CONFIG_PCI_SCAN_SHOW
665 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
667 if (dev == PCI_BDF(hose->first_busno, 0, 0))
672 #endif /* CONFIG_PCI_SCAN_SHOW */
674 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
676 unsigned int sub_bus, found_multi = 0;
677 unsigned short vendor, device, class;
678 unsigned char header_type;
679 #ifndef CONFIG_PCI_PNP
680 struct pci_config_table *cfg;
683 #ifdef CONFIG_PCI_SCAN_SHOW
684 static int indent = 0;
689 for (dev = PCI_BDF(bus,0,0);
690 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
691 PCI_MAX_PCI_FUNCTIONS - 1);
692 dev += PCI_BDF(0, 0, 1)) {
694 if (pci_skip_dev(hose, dev))
697 if (PCI_FUNC(dev) && !found_multi)
700 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
702 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
704 if (vendor == 0xffff || vendor == 0x0000)
708 found_multi = header_type & 0x80;
710 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
711 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
713 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
714 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
716 #ifdef CONFIG_PCI_FIXUP_DEV
717 board_pci_fixup_dev(hose, dev, vendor, device, class);
720 #ifdef CONFIG_PCI_SCAN_SHOW
723 /* Print leading space, including bus indentation */
724 printf("%*c", indent + 1, ' ');
726 if (pci_print_dev(hose, dev)) {
727 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
728 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
729 vendor, device, pci_class_str(class >> 8));
733 #ifdef CONFIG_PCI_PNP
734 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
737 cfg = pci_find_config(hose, class, vendor, device,
738 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
740 cfg->config_device(hose, dev, cfg);
741 sub_bus = max(sub_bus,
742 (unsigned int)hose->current_busno);
746 #ifdef CONFIG_PCI_SCAN_SHOW
751 hose->fixup_irq(hose, dev);
757 int pci_hose_scan(struct pci_controller *hose)
759 #if defined(CONFIG_PCI_BOOTDELAY)
763 if (!gd->pcidelay_done) {
764 /* wait "pcidelay" ms (if defined)... */
765 s = getenv("pcidelay");
767 int val = simple_strtoul(s, NULL, 10);
768 for (i = 0; i < val; i++)
771 gd->pcidelay_done = 1;
773 #endif /* CONFIG_PCI_BOOTDELAY */
776 * Start scan at current_busno.
777 * PCIe will start scan at first_busno+1.
779 /* For legacy support, ensure current >= first */
780 if (hose->first_busno > hose->current_busno)
781 hose->current_busno = hose->first_busno;
782 #ifdef CONFIG_PCI_PNP
783 pciauto_config_init(hose);
785 return pci_hose_scan_bus(hose, hose->current_busno);
792 /* now call board specific pci_init()... */
796 /* Returns the address of the requested capability structure within the
797 * device's PCI configuration space or 0 in case the device does not
800 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
806 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
808 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
811 pos = pci_find_cap(hose, dev, pos, cap);
816 /* Find the header pointer to the Capabilities*/
817 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
822 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
824 if (!(status & PCI_STATUS_CAP_LIST))
828 case PCI_HEADER_TYPE_NORMAL:
829 case PCI_HEADER_TYPE_BRIDGE:
830 return PCI_CAPABILITY_LIST;
831 case PCI_HEADER_TYPE_CARDBUS:
832 return PCI_CB_CAPABILITY_LIST;
838 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
840 int ttl = PCI_FIND_CAP_TTL;
845 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
846 if (next_pos < CAP_START_POS)
849 pos = (int) next_pos;
850 pci_hose_read_config_byte(hose, dev,
851 pos + PCI_CAP_LIST_ID, &id);
856 pos += PCI_CAP_LIST_NEXT;