git.sur5r.net Git - u-boot/blob - drivers/pci/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * PCI routines
  29  */
  30
  31 #include <common.h>
  32
  33 #include <command.h>
  34 #include <asm/processor.h>
  35 #include <asm/io.h>
  36 #include <pci.h>
  37
  38 #define PCI_HOSE_OP(rw, size, type)                                     \
  39 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  40                                   pci_dev_t dev,                        \
  41                                   int offset, type value)               \
  42 {                                                                       \
  43         return hose->rw##_##size(hose, dev, offset, value);             \
  44 }
  45
  46 PCI_HOSE_OP(read, byte, u8 *)
  47 PCI_HOSE_OP(read, word, u16 *)
  48 PCI_HOSE_OP(read, dword, u32 *)
  49 PCI_HOSE_OP(write, byte, u8)
  50 PCI_HOSE_OP(write, word, u16)
  51 PCI_HOSE_OP(write, dword, u32)
  52
  53 #ifndef CONFIG_IXP425
  54 #define PCI_OP(rw, size, type, error_code)                              \
  55 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  56 {                                                                       \
  57         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  58                                                                         \
  59         if (!hose)                                                      \
  60         {                                                               \
  61                 error_code;                                             \
  62                 return -1;                                              \
  63         }                                                               \
  64                                                                         \
  65         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  66 }
  67
  68 PCI_OP(read, byte, u8 *, *value = 0xff)
  69 PCI_OP(read, word, u16 *, *value = 0xffff)
  70 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  71 PCI_OP(write, byte, u8, )
  72 PCI_OP(write, word, u16, )
  73 PCI_OP(write, dword, u32, )
  74 #endif  /* CONFIG_IXP425 */
  75
  76 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  77 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  78                                         pci_dev_t dev,                  \
  79                                         int offset, type val)           \
  80 {                                                                       \
  81         u32 val32;                                                      \
  82                                                                         \
  83         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  84                 *val = -1;                                              \
  85                 return -1;                                              \
  86         }                                                               \
  87                                                                         \
  88         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  89                                                                         \
  90         return 0;                                                       \
  91 }
  92
  93 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  94 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  95                                              pci_dev_t dev,             \
  96                                              int offset, type val)      \
  97 {                                                                       \
  98         u32 val32, mask, ldata, shift;                                  \
  99                                                                         \
 100         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
 101                 return -1;                                              \
 102                                                                         \
 103         shift = ((offset & (int)off_mask) * 8);                         \
 104         ldata = (((unsigned long)val) & val_mask) << shift;             \
 105         mask = val_mask << shift;                                       \
 106         val32 = (val32 & ~mask) | ldata;                                \
 107                                                                         \
 108         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 109                 return -1;                                              \
 110                                                                         \
 111         return 0;                                                       \
 112 }
 113
 114 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 115 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 116 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 117 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 118
 119 /* Get a virtual address associated with a BAR region */
 120 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 121 {
 122         pci_addr_t pci_bus_addr;
 123         u32 bar_response;
 124
 125         /* read BAR address */
 126         pci_read_config_dword(pdev, bar, &bar_response);
 127         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 128
 129         /*
 130          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
 131          * isn't actualy used on any platform because u-boot assumes a static
 132          * linear mapping.  In the future, this could read the BAR size
 133          * and pass that as the size if needed.
 134          */
 135         return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
 136 }
 137
 138 /*
 139  *
 140  */
 141
 142 static struct pci_controller* hose_head = NULL;
 143
 144 void pci_register_hose(struct pci_controller* hose)
 145 {
 146         struct pci_controller **phose = &hose_head;
 147
 148         while(*phose)
 149                 phose = &(*phose)->next;
 150
 151         hose->next = NULL;
 152
 153         *phose = hose;
 154 }
 155
 156 struct pci_controller *pci_bus_to_hose (int bus)
 157 {
 158         struct pci_controller *hose;
 159
 160         for (hose = hose_head; hose; hose = hose->next)
 161                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 162                         return hose;
 163
 164         printf("pci_bus_to_hose() failed\n");
 165         return NULL;
 166 }
 167
 168 #ifndef CONFIG_IXP425
 169 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 170 {
 171         struct pci_controller * hose;
 172         u16 vendor, device;
 173         u8 header_type;
 174         pci_dev_t bdf;
 175         int i, bus, found_multi = 0;
 176
 177         for (hose = hose_head; hose; hose = hose->next)
 178         {
 179 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 180                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 181 #else
 182                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 183 #endif
 184                         for (bdf = PCI_BDF(bus,0,0);
 185 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
 186                              bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 187 #else
 188                              bdf < PCI_BDF(bus+1,0,0);
 189 #endif
 190                              bdf += PCI_BDF(0,0,1))
 191                         {
 192                                 if (!PCI_FUNC(bdf)) {
 193                                         pci_read_config_byte(bdf,
 194                                                              PCI_HEADER_TYPE,
 195                                                              &header_type);
 196
 197                                         found_multi = header_type & 0x80;
 198                                 } else {
 199                                         if (!found_multi)
 200                                                 continue;
 201                                 }
 202
 203                                 pci_read_config_word(bdf,
 204                                                      PCI_VENDOR_ID,
 205                                                      &vendor);
 206                                 pci_read_config_word(bdf,
 207                                                      PCI_DEVICE_ID,
 208                                                      &device);
 209
 210                                 for (i=0; ids[i].vendor != 0; i++)
 211                                         if (vendor == ids[i].vendor &&
 212                                             device == ids[i].device)
 213                                         {
 214                                                 if (index <= 0)
 215                                                         return bdf;
 216
 217                                                 index--;
 218                                         }
 219                         }
 220         }
 221
 222         return (-1);
 223 }
 224 #endif  /* CONFIG_IXP425 */
 225
 226 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 227 {
 228         static struct pci_device_id ids[2] = {{}, {0, 0}};
 229
 230         ids[0].vendor = vendor;
 231         ids[0].device = device;
 232
 233         return pci_find_devices(ids, index);
 234 }
 235
 236 /*
 237  *
 238  */
 239
 240 int __pci_hose_phys_to_bus (struct pci_controller *hose,
 241                                 phys_addr_t phys_addr,
 242                                 unsigned long flags,
 243                                 unsigned long skip_mask,
 244                                 pci_addr_t *ba)
 245 {
 246         struct pci_region *res;
 247         pci_addr_t bus_addr;
 248         int i;
 249
 250         for (i = 0; i < hose->region_count; i++) {
 251                 res = &hose->regions[i];
 252
 253                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 254                         continue;
 255
 256                 if (res->flags & skip_mask)
 257                         continue;
 258
 259                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 260
 261                 if (bus_addr >= res->bus_start &&
 262                         bus_addr < res->bus_start + res->size) {
 263                         *ba = bus_addr;
 264                         return 0;
 265                 }
 266         }
 267
 268         return 1;
 269 }
 270
 271 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 272                                     phys_addr_t phys_addr,
 273                                     unsigned long flags)
 274 {
 275         pci_addr_t bus_addr = 0;
 276         int ret;
 277
 278         if (!hose) {
 279                 puts ("pci_hose_phys_to_bus: invalid hose\n");
 280                 return bus_addr;
 281         }
 282
 283         /* if PCI_REGION_MEM is set we do a two pass search with preference
 284          * on matches that don't have PCI_REGION_SYS_MEMORY set */
 285         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 286                 ret = __pci_hose_phys_to_bus(hose, phys_addr,
 287                                 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
 288                 if (!ret)
 289                         return bus_addr;
 290         }
 291
 292         ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
 293
 294         if (ret)
 295                 puts ("pci_hose_phys_to_bus: invalid physical address\n");
 296
 297         return bus_addr;
 298 }
 299
 300 int __pci_hose_bus_to_phys (struct pci_controller *hose,
 301                                 pci_addr_t bus_addr,
 302                                 unsigned long flags,
 303                                 unsigned long skip_mask,
 304                                 phys_addr_t *pa)
 305 {
 306         struct pci_region *res;
 307         int i;
 308
 309         for (i = 0; i < hose->region_count; i++) {
 310                 res = &hose->regions[i];
 311
 312                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 313                         continue;
 314
 315                 if (res->flags & skip_mask)
 316                         continue;
 317
 318                 if (bus_addr >= res->bus_start &&
 319                         bus_addr < res->bus_start + res->size) {
 320                         *pa = (bus_addr - res->bus_start + res->phys_start);
 321                         return 0;
 322                 }
 323         }
 324
 325         return 1;
 326 }
 327
 328 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 329                                  pci_addr_t bus_addr,
 330                                  unsigned long flags)
 331 {
 332         phys_addr_t phys_addr = 0;
 333         int ret;
 334
 335         if (!hose) {
 336                 puts ("pci_hose_bus_to_phys: invalid hose\n");
 337                 return phys_addr;
 338         }
 339
 340         /* if PCI_REGION_MEM is set we do a two pass search with preference
 341          * on matches that don't have PCI_REGION_SYS_MEMORY set */
 342         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 343                 ret = __pci_hose_bus_to_phys(hose, bus_addr,
 344                                 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
 345                 if (!ret)
 346                         return phys_addr;
 347         }
 348
 349         ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
 350
 351         if (ret)
 352                 puts ("pci_hose_bus_to_phys: invalid physical address\n");
 353
 354         return phys_addr;
 355 }
 356
 357 /*
 358  *
 359  */
 360
 361 int pci_hose_config_device(struct pci_controller *hose,
 362                            pci_dev_t dev,
 363                            unsigned long io,
 364                            pci_addr_t mem,
 365                            unsigned long command)
 366 {
 367         unsigned int bar_response, old_command;
 368         pci_addr_t bar_value;
 369         pci_size_t bar_size;
 370         unsigned char pin;
 371         int bar, found_mem64;
 372
 373         debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
 374                 io, (u64)mem, command);
 375
 376         pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
 377
 378         for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
 379                 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
 380                 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
 381
 382                 if (!bar_response)
 383                         continue;
 384
 385                 found_mem64 = 0;
 386
 387                 /* Check the BAR type and set our address mask */
 388                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 389                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 390                         /* round up region base address to a multiple of size */
 391                         io = ((io - 1) | (bar_size - 1)) + 1;
 392                         bar_value = io;
 393                         /* compute new region base address */
 394                         io = io + bar_size;
 395                 } else {
 396                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 397                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
 398                                 u32 bar_response_upper;
 399                                 u64 bar64;
 400                                 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
 401                                 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
 402
 403                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 404
 405                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 406                                 found_mem64 = 1;
 407                         } else {
 408                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 409                         }
 410
 411                         /* round up region base address to multiple of size */
 412                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 413                         bar_value = mem;
 414                         /* compute new region base address */
 415                         mem = mem + bar_size;
 416                 }
 417
 418                 /* Write it out and update our limit */
 419                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 420
 421                 if (found_mem64) {
 422                         bar += 4;
 423 #ifdef CONFIG_SYS_PCI_64BIT
 424                         pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 425 #else
 426                         pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
 427 #endif
 428                 }
 429         }
 430
 431         /* Configure Cache Line Size Register */
 432         pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 433
 434         /* Configure Latency Timer */
 435         pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
 436
 437         /* Disable interrupt line, if device says it wants to use interrupts */
 438         pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
 439         if (pin != 0) {
 440                 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
 441         }
 442
 443         pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
 444         pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
 445                                      (old_command & 0xffff0000) | command);
 446
 447         return 0;
 448 }
 449
 450 /*
 451  *
 452  */
 453
 454 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 455                                          unsigned short class,
 456                                          unsigned int vendor,
 457                                          unsigned int device,
 458                                          unsigned int bus,
 459                                          unsigned int dev,
 460                                          unsigned int func)
 461 {
 462         struct pci_config_table *table;
 463
 464         for (table = hose->config_table; table && table->vendor; table++) {
 465                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 466                     (table->device == PCI_ANY_ID || table->device == device) &&
 467                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 468                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 469                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 470                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 471                         return table;
 472                 }
 473         }
 474
 475         return NULL;
 476 }
 477
 478 void pci_cfgfunc_config_device(struct pci_controller *hose,
 479                                pci_dev_t dev,
 480                                struct pci_config_table *entry)
 481 {
 482         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
 483 }
 484
 485 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 486                             pci_dev_t dev, struct pci_config_table *entry)
 487 {
 488 }
 489
 490 /*
 491  *
 492  */
 493
 494 /* HJF: Changed this to return int. I think this is required
 495  * to get the correct result when scanning bridges
 496  */
 497 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 498 extern void pciauto_config_init(struct pci_controller *hose);
 499
 500 int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 501 {
 502         /*
 503          * Check if pci device should be skipped in configuration
 504          */
 505         if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
 506 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
 507                 /*
 508                  * Only skip configuration if "pciconfighost" is not set
 509                  */
 510                 if (getenv("pciconfighost") == NULL)
 511                         return 1;
 512 #else
 513                 return 1;
 514 #endif
 515         }
 516
 517         return 0;
 518 }
 519 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 520         __attribute__((weak, alias("__pci_skip_dev")));
 521
 522 #ifdef CONFIG_PCI_SCAN_SHOW
 523 int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 524 {
 525         if (dev == PCI_BDF(hose->first_busno, 0, 0))
 526                 return 0;
 527
 528         return 1;
 529 }
 530 int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 531         __attribute__((weak, alias("__pci_print_dev")));
 532 #endif /* CONFIG_PCI_SCAN_SHOW */
 533
 534 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 535 {
 536         unsigned int sub_bus, found_multi=0;
 537         unsigned short vendor, device, class;
 538         unsigned char header_type;
 539         struct pci_config_table *cfg;
 540         pci_dev_t dev;
 541
 542         sub_bus = bus;
 543
 544         for (dev =  PCI_BDF(bus,0,0);
 545              dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 546              dev += PCI_BDF(0,0,1)) {
 547
 548                 if (pci_skip_dev(hose, dev))
 549                         continue;
 550
 551                 if (PCI_FUNC(dev) && !found_multi)
 552                         continue;
 553
 554                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 555
 556                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 557
 558                 if (vendor != 0xffff && vendor != 0x0000) {
 559
 560                         if (!PCI_FUNC(dev))
 561                                 found_multi = header_type & 0x80;
 562
 563                         debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 564                                 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 565
 566                         pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 567                         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 568
 569                         cfg = pci_find_config(hose, class, vendor, device,
 570                                               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 571                         if (cfg) {
 572                                 cfg->config_device(hose, dev, cfg);
 573                                 sub_bus = max(sub_bus, hose->current_busno);
 574 #ifdef CONFIG_PCI_PNP
 575                         } else {
 576                                 int n = pciauto_config_device(hose, dev);
 577
 578                                 sub_bus = max(sub_bus, n);
 579 #endif
 580                         }
 581                         if (hose->fixup_irq)
 582                                 hose->fixup_irq(hose, dev);
 583
 584 #ifdef CONFIG_PCI_SCAN_SHOW
 585                         if (pci_print_dev(hose, dev)) {
 586                                 unsigned char int_line;
 587
 588                                 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 589                                                           &int_line);
 590                                 printf("        %02x  %02x  %04x  %04x  %04x  %02x\n",
 591                                        PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
 592                                        int_line);
 593                         }
 594 #endif
 595                 }
 596         }
 597
 598         return sub_bus;
 599 }
 600
 601 int pci_hose_scan(struct pci_controller *hose)
 602 {
 603         /* Start scan at current_busno.
 604          * PCIe will start scan at first_busno+1.
 605          */
 606         /* For legacy support, ensure current>=first */
 607         if (hose->first_busno > hose->current_busno)
 608                 hose->current_busno = hose->first_busno;
 609 #ifdef CONFIG_PCI_PNP
 610         pciauto_config_init(hose);
 611 #endif
 612         return pci_hose_scan_bus(hose, hose->current_busno);
 613 }
 614
 615 void pci_init(void)
 616 {
 617 #if defined(CONFIG_PCI_BOOTDELAY)
 618         char *s;
 619         int i;
 620
 621         /* wait "pcidelay" ms (if defined)... */
 622         s = getenv ("pcidelay");
 623         if (s) {
 624                 int val = simple_strtoul (s, NULL, 10);
 625                 for (i=0; i<val; i++)
 626                         udelay (1000);
 627         }
 628 #endif /* CONFIG_PCI_BOOTDELAY */
 629
 630         /* now call board specific pci_init()... */
 631         pci_init_board();
 632 }