git.sur5r.net Git - u-boot/blob - drivers/pci/pci_auto.c

   1 /*
   2  * arch/powerpc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <errno.h>
  15 #include <pci.h>
  16
  17 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  18 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  19 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  20 #endif
  21
  22 /*
  23  *
  24  */
  25
  26 void pciauto_region_init(struct pci_region *res)
  27 {
  28         /*
  29          * Avoid allocating PCI resources from address 0 -- this is illegal
  30          * according to PCI 2.1 and moreover, this is known to cause Linux IDE
  31          * drivers to fail. Use a reasonable starting value of 0x1000 instead.
  32          */
  33         res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
  34 }
  35
  36 void pciauto_region_align(struct pci_region *res, pci_size_t size)
  37 {
  38         res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
  39 }
  40
  41 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
  42         pci_addr_t *bar)
  43 {
  44         pci_addr_t addr;
  45
  46         if (!res) {
  47                 debug("No resource");
  48                 goto error;
  49         }
  50
  51         addr = ((res->bus_lower - 1) | (size - 1)) + 1;
  52
  53         if (addr - res->bus_start + size > res->size) {
  54                 debug("No room in resource");
  55                 goto error;
  56         }
  57
  58         res->bus_lower = addr + size;
  59
  60         debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr,
  61               (unsigned long long)res->bus_lower);
  62
  63         *bar = addr;
  64         return 0;
  65
  66  error:
  67         *bar = (pci_addr_t)-1;
  68         return -1;
  69 }
  70
  71 /*
  72  *
  73  */
  74
  75 void pciauto_setup_device(struct pci_controller *hose,
  76                           pci_dev_t dev, int bars_num,
  77                           struct pci_region *mem,
  78                           struct pci_region *prefetch,
  79                           struct pci_region *io)
  80 {
  81         u32 bar_response;
  82         pci_size_t bar_size;
  83         u16 cmdstat = 0;
  84         int bar, bar_nr = 0;
  85 #ifndef CONFIG_PCI_ENUM_ONLY
  86         u8 header_type;
  87         int rom_addr;
  88         pci_addr_t bar_value;
  89         struct pci_region *bar_res;
  90         int found_mem64 = 0;
  91 #endif
  92
  93         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  94         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
  95
  96         for (bar = PCI_BASE_ADDRESS_0;
  97                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  98                 /* Tickle the BAR and get the response */
  99 #ifndef CONFIG_PCI_ENUM_ONLY
 100                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 101 #endif
 102                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 103
 104                 /* If BAR is not implemented go to the next BAR */
 105                 if (!bar_response)
 106                         continue;
 107
 108 #ifndef CONFIG_PCI_ENUM_ONLY
 109                 found_mem64 = 0;
 110 #endif
 111
 112                 /* Check the BAR type and set our address mask */
 113                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 114                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
 115                                    & 0xffff) + 1;
 116 #ifndef CONFIG_PCI_ENUM_ONLY
 117                         bar_res = io;
 118 #endif
 119
 120                         debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
 121                               bar_nr, (unsigned long long)bar_size);
 122                 } else {
 123                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 124                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
 125                                 u32 bar_response_upper;
 126                                 u64 bar64;
 127
 128 #ifndef CONFIG_PCI_ENUM_ONLY
 129                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 130                                         0xffffffff);
 131 #endif
 132                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 133                                         &bar_response_upper);
 134
 135                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 136
 137                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 138 #ifndef CONFIG_PCI_ENUM_ONLY
 139                                 found_mem64 = 1;
 140 #endif
 141                         } else {
 142                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 143                         }
 144 #ifndef CONFIG_PCI_ENUM_ONLY
 145                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
 146                                 bar_res = prefetch;
 147                         else
 148                                 bar_res = mem;
 149 #endif
 150
 151                         debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
 152                               bar_nr, bar_res == prefetch ? "Prf" : "Mem",
 153                               (unsigned long long)bar_size);
 154                 }
 155
 156 #ifndef CONFIG_PCI_ENUM_ONLY
 157                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 158                         /* Write it out and update our limit */
 159                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 160
 161                         if (found_mem64) {
 162                                 bar += 4;
 163 #ifdef CONFIG_SYS_PCI_64BIT
 164                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 165 #else
 166                                 /*
 167                                  * If we are a 64-bit decoder then increment to the
 168                                  * upper 32 bits of the bar and force it to locate
 169                                  * in the lower 4GB of memory.
 170                                  */
 171                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 172 #endif
 173                         }
 174
 175                 }
 176 #endif
 177                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 178                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 179
 180                 debug("\n");
 181
 182                 bar_nr++;
 183         }
 184
 185 #ifndef CONFIG_PCI_ENUM_ONLY
 186         /* Configure the expansion ROM address */
 187         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 188         header_type &= 0x7f;
 189         if (header_type != PCI_HEADER_TYPE_CARDBUS) {
 190                 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
 191                            PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
 192                 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
 193                 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
 194                 if (bar_response) {
 195                         bar_size = -(bar_response & ~1);
 196                         debug("PCI Autoconfig: ROM, size=%#x, ",
 197                               (unsigned int)bar_size);
 198                         if (pciauto_region_allocate(mem, bar_size,
 199                                                     &bar_value) == 0) {
 200                                 pci_hose_write_config_dword(hose, dev, rom_addr,
 201                                                             bar_value);
 202                         }
 203                         cmdstat |= PCI_COMMAND_MEMORY;
 204                         debug("\n");
 205                 }
 206         }
 207 #endif
 208
 209         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 210         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 211                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 212         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 213 }
 214
 215 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 216                                          pci_dev_t dev, int sub_bus)
 217 {
 218         struct pci_region *pci_mem;
 219         struct pci_region *pci_prefetch;
 220         struct pci_region *pci_io;
 221         u16 cmdstat, prefechable_64;
 222
 223 #ifdef CONFIG_DM_PCI
 224         /* The root controller has the region information */
 225         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 226
 227         pci_mem = ctlr_hose->pci_mem;
 228         pci_prefetch = ctlr_hose->pci_prefetch;
 229         pci_io = ctlr_hose->pci_io;
 230 #else
 231         pci_mem = hose->pci_mem;
 232         pci_prefetch = hose->pci_prefetch;
 233         pci_io = hose->pci_io;
 234 #endif
 235
 236         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 237         pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 238                                 &prefechable_64);
 239         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 240
 241         /* Configure bus number registers */
 242 #ifdef CONFIG_DM_PCI
 243         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
 244         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
 245 #else
 246         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 247                                    PCI_BUS(dev) - hose->first_busno);
 248         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 249                                    sub_bus - hose->first_busno);
 250 #endif
 251         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 252
 253         if (pci_mem) {
 254                 /* Round memory allocator to 1MB boundary */
 255                 pciauto_region_align(pci_mem, 0x100000);
 256
 257                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 258                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 259                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 260
 261                 cmdstat |= PCI_COMMAND_MEMORY;
 262         }
 263
 264         if (pci_prefetch) {
 265                 /* Round memory allocator to 1MB boundary */
 266                 pciauto_region_align(pci_prefetch, 0x100000);
 267
 268                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 269                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 270                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 271                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 272 #ifdef CONFIG_SYS_PCI_64BIT
 273                         pci_hose_write_config_dword(hose, dev,
 274                                         PCI_PREF_BASE_UPPER32,
 275                                         pci_prefetch->bus_lower >> 32);
 276 #else
 277                         pci_hose_write_config_dword(hose, dev,
 278                                         PCI_PREF_BASE_UPPER32,
 279                                         0x0);
 280 #endif
 281
 282                 cmdstat |= PCI_COMMAND_MEMORY;
 283         } else {
 284                 /* We don't support prefetchable memory for now, so disable */
 285                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 286                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 287                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 288                         pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
 289                         pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 290                 }
 291         }
 292
 293         if (pci_io) {
 294                 /* Round I/O allocator to 4KB boundary */
 295                 pciauto_region_align(pci_io, 0x1000);
 296
 297                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 298                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 299                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 300                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 301
 302                 cmdstat |= PCI_COMMAND_IO;
 303         }
 304
 305         /* Enable memory and I/O accesses, enable bus master */
 306         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 307                                         cmdstat | PCI_COMMAND_MASTER);
 308 }
 309
 310 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 311                                           pci_dev_t dev, int sub_bus)
 312 {
 313         struct pci_region *pci_mem;
 314         struct pci_region *pci_prefetch;
 315         struct pci_region *pci_io;
 316
 317 #ifdef CONFIG_DM_PCI
 318         /* The root controller has the region information */
 319         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 320
 321         pci_mem = ctlr_hose->pci_mem;
 322         pci_prefetch = ctlr_hose->pci_prefetch;
 323         pci_io = ctlr_hose->pci_io;
 324 #else
 325         pci_mem = hose->pci_mem;
 326         pci_prefetch = hose->pci_prefetch;
 327         pci_io = hose->pci_io;
 328 #endif
 329
 330         /* Configure bus number registers */
 331 #ifdef CONFIG_DM_PCI
 332         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
 333 #else
 334         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 335                                    sub_bus - hose->first_busno);
 336 #endif
 337
 338         if (pci_mem) {
 339                 /* Round memory allocator to 1MB boundary */
 340                 pciauto_region_align(pci_mem, 0x100000);
 341
 342                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 343                                 (pci_mem->bus_lower - 1) >> 16);
 344         }
 345
 346         if (pci_prefetch) {
 347                 u16 prefechable_64;
 348
 349                 pci_hose_read_config_word(hose, dev,
 350                                         PCI_PREF_MEMORY_LIMIT,
 351                                         &prefechable_64);
 352                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 353
 354                 /* Round memory allocator to 1MB boundary */
 355                 pciauto_region_align(pci_prefetch, 0x100000);
 356
 357                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 358                                 (pci_prefetch->bus_lower - 1) >> 16);
 359                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 360 #ifdef CONFIG_SYS_PCI_64BIT
 361                         pci_hose_write_config_dword(hose, dev,
 362                                         PCI_PREF_LIMIT_UPPER32,
 363                                         (pci_prefetch->bus_lower - 1) >> 32);
 364 #else
 365                         pci_hose_write_config_dword(hose, dev,
 366                                         PCI_PREF_LIMIT_UPPER32,
 367                                         0x0);
 368 #endif
 369         }
 370
 371         if (pci_io) {
 372                 /* Round I/O allocator to 4KB boundary */
 373                 pciauto_region_align(pci_io, 0x1000);
 374
 375                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 376                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 377                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 378                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 379         }
 380 }
 381
 382 /*
 383  *
 384  */
 385
 386 void pciauto_config_init(struct pci_controller *hose)
 387 {
 388         int i;
 389
 390         hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
 391
 392         for (i = 0; i < hose->region_count; i++) {
 393                 switch(hose->regions[i].flags) {
 394                 case PCI_REGION_IO:
 395                         if (!hose->pci_io ||
 396                             hose->pci_io->size < hose->regions[i].size)
 397                                 hose->pci_io = hose->regions + i;
 398                         break;
 399                 case PCI_REGION_MEM:
 400                         if (!hose->pci_mem ||
 401                             hose->pci_mem->size < hose->regions[i].size)
 402                                 hose->pci_mem = hose->regions + i;
 403                         break;
 404                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
 405                         if (!hose->pci_prefetch ||
 406                             hose->pci_prefetch->size < hose->regions[i].size)
 407                                 hose->pci_prefetch = hose->regions + i;
 408                         break;
 409                 }
 410         }
 411
 412
 413         if (hose->pci_mem) {
 414                 pciauto_region_init(hose->pci_mem);
 415
 416                 debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
 417                        "\t\tPhysical Memory [%llx-%llxx]\n",
 418                     (u64)hose->pci_mem->bus_start,
 419                     (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
 420                     (u64)hose->pci_mem->phys_start,
 421                     (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
 422         }
 423
 424         if (hose->pci_prefetch) {
 425                 pciauto_region_init(hose->pci_prefetch);
 426
 427                 debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
 428                        "\t\tPhysical Memory [%llx-%llx]\n",
 429                     (u64)hose->pci_prefetch->bus_start,
 430                     (u64)(hose->pci_prefetch->bus_start +
 431                             hose->pci_prefetch->size - 1),
 432                     (u64)hose->pci_prefetch->phys_start,
 433                     (u64)(hose->pci_prefetch->phys_start +
 434                             hose->pci_prefetch->size - 1));
 435         }
 436
 437         if (hose->pci_io) {
 438                 pciauto_region_init(hose->pci_io);
 439
 440                 debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
 441                        "\t\tPhysical Memory: [%llx-%llx]\n",
 442                     (u64)hose->pci_io->bus_start,
 443                     (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
 444                     (u64)hose->pci_io->phys_start,
 445                     (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
 446
 447         }
 448 }
 449
 450 /*
 451  * HJF: Changed this to return int. I think this is required
 452  * to get the correct result when scanning bridges
 453  */
 454 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 455 {
 456         struct pci_region *pci_mem;
 457         struct pci_region *pci_prefetch;
 458         struct pci_region *pci_io;
 459         unsigned int sub_bus = PCI_BUS(dev);
 460         unsigned short class;
 461         int n;
 462
 463 #ifdef CONFIG_DM_PCI
 464         /* The root controller has the region information */
 465         struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
 466
 467         pci_mem = ctlr_hose->pci_mem;
 468         pci_prefetch = ctlr_hose->pci_prefetch;
 469         pci_io = ctlr_hose->pci_io;
 470 #else
 471         pci_mem = hose->pci_mem;
 472         pci_prefetch = hose->pci_prefetch;
 473         pci_io = hose->pci_io;
 474 #endif
 475
 476         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 477
 478         switch (class) {
 479         case PCI_CLASS_BRIDGE_PCI:
 480                 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
 481                       PCI_DEV(dev));
 482
 483                 pciauto_setup_device(hose, dev, 2, pci_mem,
 484                                      pci_prefetch, pci_io);
 485
 486 #ifdef CONFIG_DM_PCI
 487                 n = dm_pci_hose_probe_bus(hose, dev);
 488                 if (n < 0)
 489                         return n;
 490                 sub_bus = (unsigned int)n;
 491 #else
 492                 /* Passing in current_busno allows for sibling P2P bridges */
 493                 hose->current_busno++;
 494                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 495                 /*
 496                  * need to figure out if this is a subordinate bridge on the bus
 497                  * to be able to properly set the pri/sec/sub bridge registers.
 498                  */
 499                 n = pci_hose_scan_bus(hose, hose->current_busno);
 500
 501                 /* figure out the deepest we've gone for this leg */
 502                 sub_bus = max((unsigned int)n, sub_bus);
 503                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 504
 505                 sub_bus = hose->current_busno;
 506 #endif
 507                 break;
 508
 509         case PCI_CLASS_BRIDGE_CARDBUS:
 510                 /*
 511                  * just do a minimal setup of the bridge,
 512                  * let the OS take care of the rest
 513                  */
 514                 pciauto_setup_device(hose, dev, 0, pci_mem,
 515                                      pci_prefetch, pci_io);
 516
 517                 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 518                       PCI_DEV(dev));
 519
 520 #ifndef CONFIG_DM_PCI
 521                 hose->current_busno++;
 522 #endif
 523                 break;
 524
 525 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 526         case PCI_CLASS_BRIDGE_OTHER:
 527                 debug("PCI Autoconfig: Skipping bridge device %d\n",
 528                       PCI_DEV(dev));
 529                 break;
 530 #endif
 531 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 532         case PCI_CLASS_BRIDGE_OTHER:
 533                 /*
 534                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 535                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 536                  * device claiming resources io/mem/irq.. we only allow for
 537                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 538                  */
 539                 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
 540                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 541                         hose->pci_prefetch, hose->pci_io);
 542                 break;
 543 #endif
 544
 545         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 546                 debug("PCI AutoConfig: Found PowerPC device\n");
 547
 548         default:
 549                 pciauto_setup_device(hose, dev, 6, pci_mem,
 550                                      pci_prefetch, pci_io);
 551                 break;
 552         }
 553
 554         return sub_bus;
 555 }