2 * arch/powerpc/kernel/pci_auto.c
4 * PCI autoconfiguration library
6 * Author: Matt Porter <mporter@mvista.com>
8 * Copyright 2000 MontaVista Software Inc.
10 * SPDX-License-Identifier: GPL-2.0+
18 #define DEBUGF(x...) printf(x)
23 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
24 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
25 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
32 void pciauto_region_init(struct pci_region *res)
35 * Avoid allocating PCI resources from address 0 -- this is illegal
36 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
37 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
39 res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
42 void pciauto_region_align(struct pci_region *res, pci_size_t size)
44 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
47 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
53 DEBUGF("No resource");
57 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
59 if (addr - res->bus_start + size > res->size) {
60 DEBUGF("No room in resource");
64 res->bus_lower = addr + size;
66 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
72 *bar = (pci_addr_t)-1;
80 void pciauto_setup_device(struct pci_controller *hose,
81 pci_dev_t dev, int bars_num,
82 struct pci_region *mem,
83 struct pci_region *prefetch,
84 struct pci_region *io)
90 #ifndef CONFIG_PCI_ENUM_ONLY
92 struct pci_region *bar_res;
96 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
97 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
99 for (bar = PCI_BASE_ADDRESS_0;
100 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
101 /* Tickle the BAR and get the response */
102 #ifndef CONFIG_PCI_ENUM_ONLY
103 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
105 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
107 /* If BAR is not implemented go to the next BAR */
111 #ifndef CONFIG_PCI_ENUM_ONLY
115 /* Check the BAR type and set our address mask */
116 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
117 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
119 #ifndef CONFIG_PCI_ENUM_ONLY
123 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
125 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
126 PCI_BASE_ADDRESS_MEM_TYPE_64) {
127 u32 bar_response_upper;
130 #ifndef CONFIG_PCI_ENUM_ONLY
131 pci_hose_write_config_dword(hose, dev, bar + 4,
134 pci_hose_read_config_dword(hose, dev, bar + 4,
135 &bar_response_upper);
137 bar64 = ((u64)bar_response_upper << 32) | bar_response;
139 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
140 #ifndef CONFIG_PCI_ENUM_ONLY
144 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
146 #ifndef CONFIG_PCI_ENUM_ONLY
147 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
153 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
156 #ifndef CONFIG_PCI_ENUM_ONLY
157 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
158 /* Write it out and update our limit */
159 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
163 #ifdef CONFIG_SYS_PCI_64BIT
164 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
167 * If we are a 64-bit decoder then increment to the
168 * upper 32 bits of the bar and force it to locate
169 * in the lower 4GB of memory.
171 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
177 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
178 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
185 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
186 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
187 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
188 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
191 int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
193 pci_addr_t bar_value;
198 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe);
199 pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response);
203 bar_size = -(bar_response & ~1);
204 DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
205 if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) {
206 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
210 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
211 cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
212 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
217 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
218 pci_dev_t dev, int sub_bus)
220 struct pci_region *pci_mem = hose->pci_mem;
221 struct pci_region *pci_prefetch = hose->pci_prefetch;
222 struct pci_region *pci_io = hose->pci_io;
223 u16 cmdstat, prefechable_64;
225 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
226 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
228 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
230 /* Configure bus number registers */
231 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
232 PCI_BUS(dev) - hose->first_busno);
233 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
234 sub_bus - hose->first_busno);
235 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
238 /* Round memory allocator to 1MB boundary */
239 pciauto_region_align(pci_mem, 0x100000);
241 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
242 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
243 (pci_mem->bus_lower & 0xfff00000) >> 16);
245 cmdstat |= PCI_COMMAND_MEMORY;
249 /* Round memory allocator to 1MB boundary */
250 pciauto_region_align(pci_prefetch, 0x100000);
252 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
253 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
254 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
255 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
256 #ifdef CONFIG_SYS_PCI_64BIT
257 pci_hose_write_config_dword(hose, dev,
258 PCI_PREF_BASE_UPPER32,
259 pci_prefetch->bus_lower >> 32);
261 pci_hose_write_config_dword(hose, dev,
262 PCI_PREF_BASE_UPPER32,
266 cmdstat |= PCI_COMMAND_MEMORY;
268 /* We don't support prefetchable memory for now, so disable */
269 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
270 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
271 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
272 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
273 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
278 /* Round I/O allocator to 4KB boundary */
279 pciauto_region_align(pci_io, 0x1000);
281 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
282 (pci_io->bus_lower & 0x0000f000) >> 8);
283 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
284 (pci_io->bus_lower & 0xffff0000) >> 16);
286 cmdstat |= PCI_COMMAND_IO;
289 /* Enable memory and I/O accesses, enable bus master */
290 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
291 cmdstat | PCI_COMMAND_MASTER);
294 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
295 pci_dev_t dev, int sub_bus)
297 struct pci_region *pci_mem = hose->pci_mem;
298 struct pci_region *pci_prefetch = hose->pci_prefetch;
299 struct pci_region *pci_io = hose->pci_io;
301 /* Configure bus number registers */
302 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
303 sub_bus - hose->first_busno);
306 /* Round memory allocator to 1MB boundary */
307 pciauto_region_align(pci_mem, 0x100000);
309 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
310 (pci_mem->bus_lower - 1) >> 16);
316 pci_hose_read_config_word(hose, dev,
317 PCI_PREF_MEMORY_LIMIT,
319 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
321 /* Round memory allocator to 1MB boundary */
322 pciauto_region_align(pci_prefetch, 0x100000);
324 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
325 (pci_prefetch->bus_lower - 1) >> 16);
326 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
327 #ifdef CONFIG_SYS_PCI_64BIT
328 pci_hose_write_config_dword(hose, dev,
329 PCI_PREF_LIMIT_UPPER32,
330 (pci_prefetch->bus_lower - 1) >> 32);
332 pci_hose_write_config_dword(hose, dev,
333 PCI_PREF_LIMIT_UPPER32,
339 /* Round I/O allocator to 4KB boundary */
340 pciauto_region_align(pci_io, 0x1000);
342 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
343 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
344 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
345 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
353 void pciauto_config_init(struct pci_controller *hose)
357 hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
359 for (i = 0; i < hose->region_count; i++) {
360 switch(hose->regions[i].flags) {
363 hose->pci_io->size < hose->regions[i].size)
364 hose->pci_io = hose->regions + i;
367 if (!hose->pci_mem ||
368 hose->pci_mem->size < hose->regions[i].size)
369 hose->pci_mem = hose->regions + i;
371 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
372 if (!hose->pci_prefetch ||
373 hose->pci_prefetch->size < hose->regions[i].size)
374 hose->pci_prefetch = hose->regions + i;
381 pciauto_region_init(hose->pci_mem);
383 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
384 "\t\tPhysical Memory [%llx-%llxx]\n",
385 (u64)hose->pci_mem->bus_start,
386 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
387 (u64)hose->pci_mem->phys_start,
388 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
391 if (hose->pci_prefetch) {
392 pciauto_region_init(hose->pci_prefetch);
394 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
395 "\t\tPhysical Memory [%llx-%llx]\n",
396 (u64)hose->pci_prefetch->bus_start,
397 (u64)(hose->pci_prefetch->bus_start +
398 hose->pci_prefetch->size - 1),
399 (u64)hose->pci_prefetch->phys_start,
400 (u64)(hose->pci_prefetch->phys_start +
401 hose->pci_prefetch->size - 1));
405 pciauto_region_init(hose->pci_io);
407 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
408 "\t\tPhysical Memory: [%llx-%llx]\n",
409 (u64)hose->pci_io->bus_start,
410 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
411 (u64)hose->pci_io->phys_start,
412 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
418 * HJF: Changed this to return int. I think this is required
419 * to get the correct result when scanning bridges
421 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
423 unsigned int sub_bus = PCI_BUS(dev);
424 unsigned short class;
427 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
430 case PCI_CLASS_BRIDGE_PCI:
431 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n",
434 pciauto_setup_device(hose, dev, 2, hose->pci_mem,
435 hose->pci_prefetch, hose->pci_io);
438 n = dm_pci_hose_probe_bus(hose, dev);
441 sub_bus = (unsigned int)n;
443 /* Passing in current_busno allows for sibling P2P bridges */
444 hose->current_busno++;
445 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
447 * need to figure out if this is a subordinate bridge on the bus
448 * to be able to properly set the pri/sec/sub bridge registers.
450 n = pci_hose_scan_bus(hose, hose->current_busno);
452 /* figure out the deepest we've gone for this leg */
453 sub_bus = max((unsigned int)n, sub_bus);
454 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
456 sub_bus = hose->current_busno;
460 case PCI_CLASS_BRIDGE_CARDBUS:
462 * just do a minimal setup of the bridge,
463 * let the OS take care of the rest
465 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
466 hose->pci_prefetch, hose->pci_io);
468 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
471 #ifndef CONFIG_DM_PCI
472 hose->current_busno++;
476 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
477 case PCI_CLASS_BRIDGE_OTHER:
478 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
482 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
483 case PCI_CLASS_BRIDGE_OTHER:
485 * The host/PCI bridge 1 seems broken in 8349 - it presents
486 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
487 * device claiming resources io/mem/irq.. we only allow for
488 * the PIMMR window to be allocated (BAR0 - 1MB size)
490 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
491 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
492 hose->pci_prefetch, hose->pci_io);
496 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
497 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
500 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
501 hose->pci_prefetch, hose->pci_io);