git.sur5r.net Git - u-boot/blob - drivers/pci/pci_auto.c

   1 /*
   2  * arch/powerpc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <common.h>
  17
  18 #include <pci.h>
  19
  20 #undef DEBUG
  21 #ifdef DEBUG
  22 #define DEBUGF(x...) printf(x)
  23 #else
  24 #define DEBUGF(x...)
  25 #endif /* DEBUG */
  26
  27 #define PCIAUTO_IDE_MODE_MASK           0x05
  28
  29 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  30 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  31 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  32 #endif
  33
  34 /*
  35  *
  36  */
  37
  38 void pciauto_region_init(struct pci_region *res)
  39 {
  40         /*
  41          * Avoid allocating PCI resources from address 0 -- this is illegal
  42          * according to PCI 2.1 and moreover, this is known to cause Linux IDE
  43          * drivers to fail. Use a reasonable starting value of 0x1000 instead.
  44          */
  45         res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
  46 }
  47
  48 void pciauto_region_align(struct pci_region *res, pci_size_t size)
  49 {
  50         res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
  51 }
  52
  53 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
  54         pci_addr_t *bar)
  55 {
  56         pci_addr_t addr;
  57
  58         if (!res) {
  59                 DEBUGF("No resource");
  60                 goto error;
  61         }
  62
  63         addr = ((res->bus_lower - 1) | (size - 1)) + 1;
  64
  65         if (addr - res->bus_start + size > res->size) {
  66                 DEBUGF("No room in resource");
  67                 goto error;
  68         }
  69
  70         res->bus_lower = addr + size;
  71
  72         DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
  73
  74         *bar = addr;
  75         return 0;
  76
  77  error:
  78         *bar = (pci_addr_t)-1;
  79         return -1;
  80 }
  81
  82 /*
  83  *
  84  */
  85
  86 void pciauto_setup_device(struct pci_controller *hose,
  87                           pci_dev_t dev, int bars_num,
  88                           struct pci_region *mem,
  89                           struct pci_region *prefetch,
  90                           struct pci_region *io)
  91 {
  92         pci_addr_t bar_response;
  93         pci_addr_t bar_value;
  94         pci_size_t bar_size;
  95         u16 cmdstat = 0;
  96         struct pci_region *bar_res;
  97         int bar, bar_nr = 0;
  98         int found_mem64 = 0;
  99
 100         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 101         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
 102
 103         for (bar = PCI_BASE_ADDRESS_0;
 104                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
 105                 /* Tickle the BAR and get the response */
 106                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 107                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 108
 109                 /* If BAR is not implemented go to the next BAR */
 110                 if (!bar_response)
 111                         continue;
 112
 113                 found_mem64 = 0;
 114
 115                 /* Check the BAR type and set our address mask */
 116                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 117                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
 118                                    & 0xffff) + 1;
 119                         bar_res = io;
 120
 121                         DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
 122                 } else {
 123                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 124                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
 125                                 u32 bar_response_upper;
 126                                 u64 bar64;
 127                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 128                                         0xffffffff);
 129                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 130                                         &bar_response_upper);
 131
 132                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 133
 134                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 135                                 found_mem64 = 1;
 136                         } else {
 137                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 138                         }
 139                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
 140                                 bar_res = prefetch;
 141                         else
 142                                 bar_res = mem;
 143
 144                         DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
 145                 }
 146
 147                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 148                         /* Write it out and update our limit */
 149                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 150
 151                         if (found_mem64) {
 152                                 bar += 4;
 153 #ifdef CONFIG_SYS_PCI_64BIT
 154                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 155 #else
 156                                 /*
 157                                  * If we are a 64-bit decoder then increment to the
 158                                  * upper 32 bits of the bar and force it to locate
 159                                  * in the lower 4GB of memory.
 160                                  */
 161                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 162 #endif
 163                         }
 164
 165                         cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 166                                 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 167                 }
 168
 169                 DEBUGF("\n");
 170
 171                 bar_nr++;
 172         }
 173
 174         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 175         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 176                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 177         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 178 }
 179
 180 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 181                                          pci_dev_t dev, int sub_bus)
 182 {
 183         struct pci_region *pci_mem = hose->pci_mem;
 184         struct pci_region *pci_prefetch = hose->pci_prefetch;
 185         struct pci_region *pci_io = hose->pci_io;
 186         u16 cmdstat;
 187
 188         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 189
 190         /* Configure bus number registers */
 191         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 192                                    PCI_BUS(dev) - hose->first_busno);
 193         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 194                                    sub_bus - hose->first_busno);
 195         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 196
 197         if (pci_mem) {
 198                 /* Round memory allocator to 1MB boundary */
 199                 pciauto_region_align(pci_mem, 0x100000);
 200
 201                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 202                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 203                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 204
 205                 cmdstat |= PCI_COMMAND_MEMORY;
 206         }
 207
 208         if (pci_prefetch) {
 209                 /* Round memory allocator to 1MB boundary */
 210                 pciauto_region_align(pci_prefetch, 0x100000);
 211
 212                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 213                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 214                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 215
 216                 cmdstat |= PCI_COMMAND_MEMORY;
 217         } else {
 218                 /* We don't support prefetchable memory for now, so disable */
 219                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 220                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 221         }
 222
 223         if (pci_io) {
 224                 /* Round I/O allocator to 4KB boundary */
 225                 pciauto_region_align(pci_io, 0x1000);
 226
 227                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 228                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 229                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 230                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 231
 232                 cmdstat |= PCI_COMMAND_IO;
 233         }
 234
 235         /* Enable memory and I/O accesses, enable bus master */
 236         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 237                                         cmdstat | PCI_COMMAND_MASTER);
 238 }
 239
 240 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 241                                           pci_dev_t dev, int sub_bus)
 242 {
 243         struct pci_region *pci_mem = hose->pci_mem;
 244         struct pci_region *pci_prefetch = hose->pci_prefetch;
 245         struct pci_region *pci_io = hose->pci_io;
 246
 247         /* Configure bus number registers */
 248         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 249                                    sub_bus - hose->first_busno);
 250
 251         if (pci_mem) {
 252                 /* Round memory allocator to 1MB boundary */
 253                 pciauto_region_align(pci_mem, 0x100000);
 254
 255                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 256                                 (pci_mem->bus_lower - 1) >> 16);
 257         }
 258
 259         if (pci_prefetch) {
 260                 /* Round memory allocator to 1MB boundary */
 261                 pciauto_region_align(pci_prefetch, 0x100000);
 262
 263                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 264                                 (pci_prefetch->bus_lower - 1) >> 16);
 265         }
 266
 267         if (pci_io) {
 268                 /* Round I/O allocator to 4KB boundary */
 269                 pciauto_region_align(pci_io, 0x1000);
 270
 271                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 272                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 273                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 274                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 275         }
 276 }
 277
 278 /*
 279  *
 280  */
 281
 282 void pciauto_config_init(struct pci_controller *hose)
 283 {
 284         int i;
 285
 286         hose->pci_io = hose->pci_mem = NULL;
 287
 288         for (i = 0; i < hose->region_count; i++) {
 289                 switch(hose->regions[i].flags) {
 290                 case PCI_REGION_IO:
 291                         if (!hose->pci_io ||
 292                             hose->pci_io->size < hose->regions[i].size)
 293                                 hose->pci_io = hose->regions + i;
 294                         break;
 295                 case PCI_REGION_MEM:
 296                         if (!hose->pci_mem ||
 297                             hose->pci_mem->size < hose->regions[i].size)
 298                                 hose->pci_mem = hose->regions + i;
 299                         break;
 300                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
 301                         if (!hose->pci_prefetch ||
 302                             hose->pci_prefetch->size < hose->regions[i].size)
 303                                 hose->pci_prefetch = hose->regions + i;
 304                         break;
 305                 }
 306         }
 307
 308
 309         if (hose->pci_mem) {
 310                 pciauto_region_init(hose->pci_mem);
 311
 312                 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
 313                        "\t\tPhysical Memory [%llx-%llxx]\n",
 314                     (u64)hose->pci_mem->bus_start,
 315                     (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
 316                     (u64)hose->pci_mem->phys_start,
 317                     (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
 318         }
 319
 320         if (hose->pci_prefetch) {
 321                 pciauto_region_init(hose->pci_prefetch);
 322
 323                 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
 324                        "\t\tPhysical Memory [%llx-%llx]\n",
 325                     (u64)hose->pci_prefetch->bus_start,
 326                     (u64)(hose->pci_prefetch->bus_start +
 327                             hose->pci_prefetch->size - 1),
 328                     (u64)hose->pci_prefetch->phys_start,
 329                     (u64)(hose->pci_prefetch->phys_start +
 330                             hose->pci_prefetch->size - 1));
 331         }
 332
 333         if (hose->pci_io) {
 334                 pciauto_region_init(hose->pci_io);
 335
 336                 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
 337                        "\t\tPhysical Memory: [%llx-%llx]\n",
 338                     (u64)hose->pci_io->bus_start,
 339                     (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
 340                     (u64)hose->pci_io->phys_start,
 341                     (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
 342
 343         }
 344 }
 345
 346 /*
 347  * HJF: Changed this to return int. I think this is required
 348  * to get the correct result when scanning bridges
 349  */
 350 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 351 {
 352         unsigned int sub_bus = PCI_BUS(dev);
 353         unsigned short class;
 354         unsigned char prg_iface;
 355         int n;
 356
 357         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 358
 359         switch (class) {
 360         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 361                 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
 362                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 363                                      hose->pci_prefetch, hose->pci_io);
 364                 break;
 365
 366         case PCI_CLASS_BRIDGE_PCI:
 367                 hose->current_busno++;
 368                 pciauto_setup_device(hose, dev, 2, hose->pci_mem,
 369                         hose->pci_prefetch, hose->pci_io);
 370
 371                 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
 372
 373                 /* Passing in current_busno allows for sibling P2P bridges */
 374                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 375                 /*
 376                  * need to figure out if this is a subordinate bridge on the bus
 377                  * to be able to properly set the pri/sec/sub bridge registers.
 378                  */
 379                 n = pci_hose_scan_bus(hose, hose->current_busno);
 380
 381                 /* figure out the deepest we've gone for this leg */
 382                 sub_bus = max(n, sub_bus);
 383                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 384
 385                 sub_bus = hose->current_busno;
 386                 break;
 387
 388         case PCI_CLASS_STORAGE_IDE:
 389                 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
 390                 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 391                         DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
 392                         return sub_bus;
 393                 }
 394
 395                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 396                         hose->pci_prefetch, hose->pci_io);
 397                 break;
 398
 399         case PCI_CLASS_BRIDGE_CARDBUS:
 400                 /*
 401                  * just do a minimal setup of the bridge,
 402                  * let the OS take care of the rest
 403                  */
 404                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 405                         hose->pci_prefetch, hose->pci_io);
 406
 407                 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 408                         PCI_DEV(dev));
 409
 410                 hose->current_busno++;
 411                 break;
 412
 413 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 414         case PCI_CLASS_BRIDGE_OTHER:
 415                 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
 416                        PCI_DEV(dev));
 417                 break;
 418 #endif
 419 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 420         case PCI_CLASS_BRIDGE_OTHER:
 421                 /*
 422                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 423                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 424                  * device claiming resources io/mem/irq.. we only allow for
 425                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 426                  */
 427                 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
 428                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 429                         hose->pci_prefetch, hose->pci_io);
 430                 break;
 431 #endif
 432         default:
 433                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 434                         hose->pci_prefetch, hose->pci_io);
 435                 break;
 436         }
 437
 438         return sub_bus;
 439 }