git.sur5r.net Git - u-boot/blob - drivers/pci/pci_auto.c

   1 /*
   2  * arch/powerpc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <errno.h>
  15 #include <pci.h>
  16
  17 #ifdef DEBUG
  18 #define DEBUGF(x...) printf(x)
  19 #else
  20 #define DEBUGF(x...)
  21 #endif /* DEBUG */
  22
  23 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  24 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  25 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  26 #endif
  27
  28 /*
  29  *
  30  */
  31
  32 void pciauto_region_init(struct pci_region *res)
  33 {
  34         /*
  35          * Avoid allocating PCI resources from address 0 -- this is illegal
  36          * according to PCI 2.1 and moreover, this is known to cause Linux IDE
  37          * drivers to fail. Use a reasonable starting value of 0x1000 instead.
  38          */
  39         res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
  40 }
  41
  42 void pciauto_region_align(struct pci_region *res, pci_size_t size)
  43 {
  44         res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
  45 }
  46
  47 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
  48         pci_addr_t *bar)
  49 {
  50         pci_addr_t addr;
  51
  52         if (!res) {
  53                 DEBUGF("No resource");
  54                 goto error;
  55         }
  56
  57         addr = ((res->bus_lower - 1) | (size - 1)) + 1;
  58
  59         if (addr - res->bus_start + size > res->size) {
  60                 DEBUGF("No room in resource");
  61                 goto error;
  62         }
  63
  64         res->bus_lower = addr + size;
  65
  66         DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
  67
  68         *bar = addr;
  69         return 0;
  70
  71  error:
  72         *bar = (pci_addr_t)-1;
  73         return -1;
  74 }
  75
  76 /*
  77  *
  78  */
  79
  80 void pciauto_setup_device(struct pci_controller *hose,
  81                           pci_dev_t dev, int bars_num,
  82                           struct pci_region *mem,
  83                           struct pci_region *prefetch,
  84                           struct pci_region *io)
  85 {
  86         u32 bar_response;
  87         pci_size_t bar_size;
  88         u16 cmdstat = 0;
  89         int bar, bar_nr = 0;
  90         u8 header_type;
  91         int rom_addr;
  92 #ifndef CONFIG_PCI_ENUM_ONLY
  93         pci_addr_t bar_value;
  94         struct pci_region *bar_res;
  95         int found_mem64 = 0;
  96 #endif
  97
  98         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  99         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
 100
 101         for (bar = PCI_BASE_ADDRESS_0;
 102                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
 103                 /* Tickle the BAR and get the response */
 104 #ifndef CONFIG_PCI_ENUM_ONLY
 105                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 106 #endif
 107                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 108
 109                 /* If BAR is not implemented go to the next BAR */
 110                 if (!bar_response)
 111                         continue;
 112
 113 #ifndef CONFIG_PCI_ENUM_ONLY
 114                 found_mem64 = 0;
 115 #endif
 116
 117                 /* Check the BAR type and set our address mask */
 118                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 119                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
 120                                    & 0xffff) + 1;
 121 #ifndef CONFIG_PCI_ENUM_ONLY
 122                         bar_res = io;
 123 #endif
 124
 125                         DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
 126                 } else {
 127                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 128                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
 129                                 u32 bar_response_upper;
 130                                 u64 bar64;
 131
 132 #ifndef CONFIG_PCI_ENUM_ONLY
 133                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 134                                         0xffffffff);
 135 #endif
 136                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 137                                         &bar_response_upper);
 138
 139                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 140
 141                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 142 #ifndef CONFIG_PCI_ENUM_ONLY
 143                                 found_mem64 = 1;
 144 #endif
 145                         } else {
 146                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 147                         }
 148 #ifndef CONFIG_PCI_ENUM_ONLY
 149                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
 150                                 bar_res = prefetch;
 151                         else
 152                                 bar_res = mem;
 153 #endif
 154
 155                         DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
 156                 }
 157
 158 #ifndef CONFIG_PCI_ENUM_ONLY
 159                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 160                         /* Write it out and update our limit */
 161                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 162
 163                         if (found_mem64) {
 164                                 bar += 4;
 165 #ifdef CONFIG_SYS_PCI_64BIT
 166                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 167 #else
 168                                 /*
 169                                  * If we are a 64-bit decoder then increment to the
 170                                  * upper 32 bits of the bar and force it to locate
 171                                  * in the lower 4GB of memory.
 172                                  */
 173                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 174 #endif
 175                         }
 176
 177                 }
 178 #endif
 179                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 180                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 181
 182                 DEBUGF("\n");
 183
 184                 bar_nr++;
 185         }
 186
 187         /* Configure the expansion ROM address */
 188         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 189         if (header_type != PCI_HEADER_TYPE_CARDBUS) {
 190                 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
 191                            PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
 192                 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
 193                 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
 194                 if (bar_response) {
 195                         bar_size = -(bar_response & ~1);
 196                         DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
 197                         if (pciauto_region_allocate(mem, bar_size,
 198                                                     &bar_value) == 0) {
 199                                 pci_hose_write_config_dword(hose, dev, rom_addr,
 200                                                             bar_value);
 201                         }
 202                         cmdstat |= PCI_COMMAND_MEMORY;
 203                         DEBUGF("\n");
 204                 }
 205         }
 206
 207         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 208         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 209                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 210         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 211 }
 212
 213 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 214                                          pci_dev_t dev, int sub_bus)
 215 {
 216         struct pci_region *pci_mem = hose->pci_mem;
 217         struct pci_region *pci_prefetch = hose->pci_prefetch;
 218         struct pci_region *pci_io = hose->pci_io;
 219         u16 cmdstat, prefechable_64;
 220
 221         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 222         pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 223                                 &prefechable_64);
 224         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 225
 226         /* Configure bus number registers */
 227         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 228                                    PCI_BUS(dev) - hose->first_busno);
 229         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 230                                    sub_bus - hose->first_busno);
 231         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 232
 233         if (pci_mem) {
 234                 /* Round memory allocator to 1MB boundary */
 235                 pciauto_region_align(pci_mem, 0x100000);
 236
 237                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 238                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 239                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 240
 241                 cmdstat |= PCI_COMMAND_MEMORY;
 242         }
 243
 244         if (pci_prefetch) {
 245                 /* Round memory allocator to 1MB boundary */
 246                 pciauto_region_align(pci_prefetch, 0x100000);
 247
 248                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 249                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 250                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 251                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 252 #ifdef CONFIG_SYS_PCI_64BIT
 253                         pci_hose_write_config_dword(hose, dev,
 254                                         PCI_PREF_BASE_UPPER32,
 255                                         pci_prefetch->bus_lower >> 32);
 256 #else
 257                         pci_hose_write_config_dword(hose, dev,
 258                                         PCI_PREF_BASE_UPPER32,
 259                                         0x0);
 260 #endif
 261
 262                 cmdstat |= PCI_COMMAND_MEMORY;
 263         } else {
 264                 /* We don't support prefetchable memory for now, so disable */
 265                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 266                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 267                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 268                         pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
 269                         pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 270                 }
 271         }
 272
 273         if (pci_io) {
 274                 /* Round I/O allocator to 4KB boundary */
 275                 pciauto_region_align(pci_io, 0x1000);
 276
 277                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 278                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 279                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 280                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 281
 282                 cmdstat |= PCI_COMMAND_IO;
 283         }
 284
 285         /* Enable memory and I/O accesses, enable bus master */
 286         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 287                                         cmdstat | PCI_COMMAND_MASTER);
 288 }
 289
 290 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 291                                           pci_dev_t dev, int sub_bus)
 292 {
 293         struct pci_region *pci_mem = hose->pci_mem;
 294         struct pci_region *pci_prefetch = hose->pci_prefetch;
 295         struct pci_region *pci_io = hose->pci_io;
 296
 297         /* Configure bus number registers */
 298         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 299                                    sub_bus - hose->first_busno);
 300
 301         if (pci_mem) {
 302                 /* Round memory allocator to 1MB boundary */
 303                 pciauto_region_align(pci_mem, 0x100000);
 304
 305                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 306                                 (pci_mem->bus_lower - 1) >> 16);
 307         }
 308
 309         if (pci_prefetch) {
 310                 u16 prefechable_64;
 311
 312                 pci_hose_read_config_word(hose, dev,
 313                                         PCI_PREF_MEMORY_LIMIT,
 314                                         &prefechable_64);
 315                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 316
 317                 /* Round memory allocator to 1MB boundary */
 318                 pciauto_region_align(pci_prefetch, 0x100000);
 319
 320                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 321                                 (pci_prefetch->bus_lower - 1) >> 16);
 322                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 323 #ifdef CONFIG_SYS_PCI_64BIT
 324                         pci_hose_write_config_dword(hose, dev,
 325                                         PCI_PREF_LIMIT_UPPER32,
 326                                         (pci_prefetch->bus_lower - 1) >> 32);
 327 #else
 328                         pci_hose_write_config_dword(hose, dev,
 329                                         PCI_PREF_LIMIT_UPPER32,
 330                                         0x0);
 331 #endif
 332         }
 333
 334         if (pci_io) {
 335                 /* Round I/O allocator to 4KB boundary */
 336                 pciauto_region_align(pci_io, 0x1000);
 337
 338                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 339                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 340                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 341                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 342         }
 343 }
 344
 345 /*
 346  *
 347  */
 348
 349 void pciauto_config_init(struct pci_controller *hose)
 350 {
 351         int i;
 352
 353         hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
 354
 355         for (i = 0; i < hose->region_count; i++) {
 356                 switch(hose->regions[i].flags) {
 357                 case PCI_REGION_IO:
 358                         if (!hose->pci_io ||
 359                             hose->pci_io->size < hose->regions[i].size)
 360                                 hose->pci_io = hose->regions + i;
 361                         break;
 362                 case PCI_REGION_MEM:
 363                         if (!hose->pci_mem ||
 364                             hose->pci_mem->size < hose->regions[i].size)
 365                                 hose->pci_mem = hose->regions + i;
 366                         break;
 367                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
 368                         if (!hose->pci_prefetch ||
 369                             hose->pci_prefetch->size < hose->regions[i].size)
 370                                 hose->pci_prefetch = hose->regions + i;
 371                         break;
 372                 }
 373         }
 374
 375
 376         if (hose->pci_mem) {
 377                 pciauto_region_init(hose->pci_mem);
 378
 379                 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
 380                        "\t\tPhysical Memory [%llx-%llxx]\n",
 381                     (u64)hose->pci_mem->bus_start,
 382                     (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
 383                     (u64)hose->pci_mem->phys_start,
 384                     (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
 385         }
 386
 387         if (hose->pci_prefetch) {
 388                 pciauto_region_init(hose->pci_prefetch);
 389
 390                 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
 391                        "\t\tPhysical Memory [%llx-%llx]\n",
 392                     (u64)hose->pci_prefetch->bus_start,
 393                     (u64)(hose->pci_prefetch->bus_start +
 394                             hose->pci_prefetch->size - 1),
 395                     (u64)hose->pci_prefetch->phys_start,
 396                     (u64)(hose->pci_prefetch->phys_start +
 397                             hose->pci_prefetch->size - 1));
 398         }
 399
 400         if (hose->pci_io) {
 401                 pciauto_region_init(hose->pci_io);
 402
 403                 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
 404                        "\t\tPhysical Memory: [%llx-%llx]\n",
 405                     (u64)hose->pci_io->bus_start,
 406                     (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
 407                     (u64)hose->pci_io->phys_start,
 408                     (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
 409
 410         }
 411 }
 412
 413 /*
 414  * HJF: Changed this to return int. I think this is required
 415  * to get the correct result when scanning bridges
 416  */
 417 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 418 {
 419         unsigned int sub_bus = PCI_BUS(dev);
 420         unsigned short class;
 421         int n;
 422
 423         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 424
 425         switch (class) {
 426         case PCI_CLASS_BRIDGE_PCI:
 427                 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n",
 428                        PCI_DEV(dev));
 429
 430                 pciauto_setup_device(hose, dev, 2, hose->pci_mem,
 431                         hose->pci_prefetch, hose->pci_io);
 432
 433 #ifdef CONFIG_DM_PCI
 434                 n = dm_pci_hose_probe_bus(hose, dev);
 435                 if (n < 0)
 436                         return n;
 437                 sub_bus = (unsigned int)n;
 438 #else
 439                 /* Passing in current_busno allows for sibling P2P bridges */
 440                 hose->current_busno++;
 441                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 442                 /*
 443                  * need to figure out if this is a subordinate bridge on the bus
 444                  * to be able to properly set the pri/sec/sub bridge registers.
 445                  */
 446                 n = pci_hose_scan_bus(hose, hose->current_busno);
 447
 448                 /* figure out the deepest we've gone for this leg */
 449                 sub_bus = max((unsigned int)n, sub_bus);
 450                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 451
 452                 sub_bus = hose->current_busno;
 453 #endif
 454                 break;
 455
 456         case PCI_CLASS_BRIDGE_CARDBUS:
 457                 /*
 458                  * just do a minimal setup of the bridge,
 459                  * let the OS take care of the rest
 460                  */
 461                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 462                         hose->pci_prefetch, hose->pci_io);
 463
 464                 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 465                         PCI_DEV(dev));
 466
 467 #ifndef CONFIG_DM_PCI
 468                 hose->current_busno++;
 469 #endif
 470                 break;
 471
 472 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 473         case PCI_CLASS_BRIDGE_OTHER:
 474                 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
 475                        PCI_DEV(dev));
 476                 break;
 477 #endif
 478 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 479         case PCI_CLASS_BRIDGE_OTHER:
 480                 /*
 481                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 482                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 483                  * device claiming resources io/mem/irq.. we only allow for
 484                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 485                  */
 486                 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
 487                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 488                         hose->pci_prefetch, hose->pci_io);
 489                 break;
 490 #endif
 491
 492         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 493                 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
 494
 495         default:
 496                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 497                         hose->pci_prefetch, hose->pci_io);
 498                 break;
 499         }
 500
 501         return sub_bus;
 502 }