2 * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
4 * Copyright (C) 2011 Andes Technology Corporation
5 * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
6 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <faraday/ftpci100.h>
17 #include <asm/types.h> /* u32, u16.... used by pci.h */
19 struct ftpci100_data {
20 unsigned int reg_base;
22 unsigned int mem_base;
23 unsigned int mmio_base;
27 static struct pci_config devs[FTPCI100_MAX_FUNCTIONS];
28 static struct pci_controller local_hose;
30 static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func,
31 unsigned char header, struct ftpci100_data *priv)
33 struct pci_controller *hose = (struct pci_controller *)&local_hose;
34 unsigned int i, tmp32, bar_no, iovsmem = 1;
37 /* A device is present, add an entry to the array */
38 devs[priv->ndevs].bus = bus;
39 devs[priv->ndevs].dev = dev;
40 devs[priv->ndevs].func = func;
42 dev_nu = PCI_BDF(bus, dev, func);
44 if ((header & 0x7f) == 0x01)
50 /* Allocate address spaces by configuring BARs */
51 for (i = 0; i < bar_no; i++) {
52 pci_hose_write_config_dword(hose, dev_nu,
53 PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff);
54 pci_hose_read_config_dword(hose, dev_nu,
55 PCI_BASE_ADDRESS_0 + i * 4, &tmp32);
63 unsigned int size_mask = ~(tmp32 & 0xfffffffc);
65 if (priv->io_base & size_mask)
66 priv->io_base = (priv->io_base & ~size_mask) + \
69 devs[priv->ndevs].bar[i].addr = priv->io_base;
70 devs[priv->ndevs].bar[i].size = size_mask + 1;
72 pci_hose_write_config_dword(hose, dev_nu,
73 PCI_BASE_ADDRESS_0 + i * 4,
76 debug("Allocated IO address 0x%X-" \
77 "0x%X for Bus %d, Device %d, Function %d\n",
79 priv->io_base + size_mask, bus, dev, func);
81 priv->io_base += size_mask + 1;
84 unsigned int is_64bit = ((tmp32 & 0x6) == 0x4);
85 unsigned int is_pref = tmp32 & 0x8;
86 unsigned int size_mask = ~(tmp32 & 0xfffffff0);
87 unsigned int alloc_base;
88 unsigned int *addr_mem_base;
91 addr_mem_base = &priv->mem_base;
93 addr_mem_base = &priv->mmio_base;
95 alloc_base = *addr_mem_base;
97 if (alloc_base & size_mask)
98 alloc_base = (alloc_base & ~size_mask) \
101 pci_hose_write_config_dword(hose, dev_nu,
102 PCI_BASE_ADDRESS_0 + i * 4, alloc_base);
104 debug("Allocated %s address 0x%X-" \
105 "0x%X for Bus %d, Device %d, Function %d\n",
106 is_pref ? "MEM" : "MMIO", alloc_base,
107 alloc_base + size_mask, bus, dev, func);
109 devs[priv->ndevs].bar[i].addr = alloc_base;
110 devs[priv->ndevs].bar[i].size = size_mask + 1;
112 debug("BAR address BAR size\n");
113 debug("%010x %08d\n",
114 devs[priv->ndevs].bar[0].addr,
115 devs[priv->ndevs].bar[0].size);
117 alloc_base += size_mask + 1;
118 *addr_mem_base = alloc_base;
122 pci_hose_write_config_dword(hose, dev_nu,
123 PCI_BASE_ADDRESS_0 + i * 4, 0x0);
128 /* Enable Bus Master, Memory Space, and IO Space */
129 pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
130 pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08);
131 pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
133 pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32);
142 pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32);
145 static void pci_bus_scan(struct ftpci100_data *priv)
147 struct pci_controller *hose = (struct pci_controller *)&local_hose;
148 unsigned int bus, dev, func;
152 unsigned char header;
153 unsigned char int_pin;
154 unsigned int niobars;
162 for (bus = 0; bus < MAX_BUS_NUM; bus++)
163 for (dev = 0; dev < MAX_DEV_NUM; dev++)
164 for (func = 0; func < MAX_FUN_NUM; func++) {
165 dev_nu = PCI_BDF(bus, dev, func);
166 pci_hose_read_config_dword(hose, dev_nu,
167 PCI_VENDOR_ID, &data32);
170 * some broken boards return 0 or ~0,
171 * if a slot is empty.
173 if (data32 == 0xffffffff ||
174 data32 == 0x00000000 ||
175 data32 == 0x0000ffff ||
176 data32 == 0xffff0000)
179 pci_hose_read_config_dword(hose, dev_nu,
180 PCI_HEADER_TYPE, &tmp);
181 header = (unsigned char)tmp;
182 setup_pci_bar(bus, dev, func, header, priv);
184 devs[priv->ndevs].v_id = (u16)(data32 & \
187 devs[priv->ndevs].d_id = (u16)((data32 & \
190 /* Figure out what INTX# line the card uses */
191 pci_hose_read_config_byte(hose, dev_nu,
192 PCI_INTERRUPT_PIN, &int_pin);
194 /* assign the appropriate irq line */
195 if (int_pin > PCI_IRQ_LINES) {
196 printf("more irq lines than expect\n");
197 } else if (int_pin != 0) {
198 /* This device uses an interrupt line */
199 devs[priv->ndevs].pin = int_pin;
202 pci_hose_read_config_dword(hose, dev_nu,
203 PCI_CLASS_DEVICE, &data32);
205 debug("%06d %03d %03d " \
207 "%03d %08x %06d %08x\n",
208 priv->ndevs, devs[priv->ndevs].bus,
209 devs[priv->ndevs].dev,
210 devs[priv->ndevs].func,
211 devs[priv->ndevs].d_id,
212 devs[priv->ndevs].v_id,
213 devs[priv->ndevs].pin,
214 devs[priv->ndevs].bar[0].addr,
215 devs[priv->ndevs].bar[0].size,
222 static void ftpci_preinit(struct ftpci100_data *priv)
224 struct ftpci100_ahbc *ftpci100;
225 struct pci_controller *hose = (struct pci_controller *)&local_hose;
229 priv->reg_base = CONFIG_FTPCI100_BASE;
230 priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE;
231 priv->mmio_base = CONFIG_FTPCI100_MEM_BASE;
232 priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE;
234 ftpci100 = (struct ftpci100_ahbc *)priv->reg_base;
236 pci_config_addr = (u32) &ftpci100->conf;
237 pci_config_data = (u32) &ftpci100->data;
239 /* print device name */
240 printf("FTPCI100\n");
242 /* dump basic configuration */
243 debug("%s: Config addr is %08X, data port is %08X\n",
244 __func__, pci_config_addr, pci_config_data);
246 /* PCI memory space */
247 pci_set_region(hose->regions + 0,
252 hose->region_count++;
255 pci_set_region(hose->regions + 1,
260 hose->region_count++;
262 #if defined(CONFIG_PCI_SYS_BUS)
263 /* PCI System Memory space */
264 pci_set_region(hose->regions + 2,
268 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
269 hose->region_count++;
272 /* setup indirect read/write function */
273 pci_setup_indirect(hose, pci_config_addr, pci_config_data);
276 pci_register_hose(hose);
279 void pci_ftpci_init(void)
281 struct ftpci100_data *priv = NULL;
282 struct pci_controller *hose = (struct pci_controller *)&local_hose;
283 pci_dev_t bridge_num;
285 struct pci_device_id bridge_ids[] = {
286 {FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID},
290 priv = malloc(sizeof(struct ftpci100_data));
293 printf("%s(): failed to malloc priv\n", __func__);
297 memset(priv, 0, sizeof(struct ftpci100_data));
301 debug("Device bus dev func deviceID vendorID pin address" \
307 * Setup the PCI Bridge Window to 1GB,
308 * it will cause USB OHCI Host controller Unrecoverable Error
311 bridge_num = pci_find_devices(bridge_ids, 0);
312 if (bridge_num == -1) {
313 printf("PCI Bridge not found\n");
316 pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1,
317 FTPCI100_BASE_ADR_SIZE(1024));