5 * Michael Schwingen, michael@schwingen.org
6 * (C) Copyright 2004 eslab.whut.edu.cn
7 * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/processor.h>
16 #include <asm/arch/ixp425.h>
17 #include <asm/arch/ixp425pci.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static void non_prefetch_read(unsigned int addr, unsigned int cmd,
23 static void non_prefetch_write(unsigned int addr, unsigned int cmd,
26 /*define the sub vendor and subsystem to be used */
27 #define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
29 #define PCI_MEMORY_BUS 0x00000000
30 #define PCI_MEMORY_PHY 0x00000000
31 #define PCI_MEMORY_SIZE 0x04000000
33 #define PCI_MEM_BUS 0x48000000
34 #define PCI_MEM_PHY 0x00000000
35 #define PCI_MEM_SIZE 0x04000000
37 #define PCI_IO_BUS 0x00000000
38 #define PCI_IO_PHY 0x00000000
39 #define PCI_IO_SIZE 0x00010000
41 /* build address value for config sycle */
42 static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg)
44 unsigned int bus = PCI_BUS(bdf);
45 unsigned int dev = PCI_DEV(bdf);
46 unsigned int func = PCI_FUNC(bdf);
49 if (bus) { /* secondary bus, use type 1 config cycle */
50 addr = bdf | (reg & ~3) | 1;
53 primary bus, type 0 config cycle. address bits 31:28
54 specify the device 10:8 specify the function
56 addr = BIT((31 - dev)) | (func << 8) | (reg & ~3);
62 static int pci_config_status(void)
66 regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET);
67 if ((regval & PCI_ISR_PFE) == 0)
70 /* no device present, make sure that the master abort bit is reset */
71 writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET);
75 static int pci_ixp_hose_read_config_dword(struct pci_controller *hose,
76 pci_dev_t bdf, int where, unsigned int *val)
82 debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where);
83 /*Set the address to be read */
84 addr = pci_config_addr(bdf, where);
85 non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval);
88 stat = pci_config_status();
91 debug("-> val %x, status %x\n", *val, stat);
95 static int pci_ixp_hose_read_config_word(struct pci_controller *hose,
96 pci_dev_t bdf, int where, unsigned short *val)
101 unsigned int byteEnables;
104 debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where);
106 /*byte enables are 4 bits active low, the position of each
107 bit maps to the byte that it enables */
109 (~(BIT(n) | BIT((n + 1)))) &
110 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
111 byteEnables = byteEnables << PCI_NP_CBE_BESL;
112 /*Set the address to be read */
113 addr = pci_config_addr(bdf, where);
114 non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
116 /*Pick out the word we are interested in */
117 *val = retval >> (8 * n);
119 stat = pci_config_status();
122 debug("-> val %x, status %x\n", *val, stat);
126 static int pci_ixp_hose_read_config_byte(struct pci_controller *hose,
127 pci_dev_t bdf, int where, unsigned char *val)
131 unsigned int byteEnables;
135 debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where);
137 /*byte enables are 4 bits, active low, the position of each
138 bit maps to the byte that it enables */
139 byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
140 byteEnables = byteEnables << PCI_NP_CBE_BESL;
142 /*Set the address to be read */
143 addr = pci_config_addr(bdf, where);
144 non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
145 /*Pick out the byte we are interested in */
146 *val = retval >> (8 * n);
148 stat = pci_config_status();
151 debug("-> val %x, status %x\n", *val, stat);
155 static int pci_ixp_hose_write_config_byte(struct pci_controller *hose,
156 pci_dev_t bdf, int where, unsigned char val)
159 unsigned int byteEnables;
164 debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x",
167 /*byte enables are 4 bits active low, the position of each
168 bit maps to the byte that it enables */
169 byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
170 byteEnables = byteEnables << PCI_NP_CBE_BESL;
171 ldata = val << (8 * n);
172 /*Set the address to be written */
173 addr = pci_config_addr(bdf, where);
174 non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
176 stat = pci_config_status();
177 debug("-> status %x\n", stat);
181 static int pci_ixp_hose_write_config_word(struct pci_controller *hose,
182 pci_dev_t bdf, int where, unsigned short val)
185 unsigned int byteEnables;
190 debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x",
193 /*byte enables are 4 bits active low, the position of each
194 bit maps to the byte that it enables */
196 (~(BIT(n) | BIT((n + 1)))) &
197 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
198 byteEnables = byteEnables << PCI_NP_CBE_BESL;
199 ldata = val << (8 * n);
200 /*Set the address to be written */
201 addr = pci_config_addr(bdf, where);
202 non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
204 stat = pci_config_status();
205 debug("-> status %x\n", stat);
209 static int pci_ixp_hose_write_config_dword(struct pci_controller *hose,
210 pci_dev_t bdf, int where, unsigned int val)
215 debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x",
217 /*Set the address to be written */
218 addr = pci_config_addr(bdf, where);
219 non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val);
221 stat = pci_config_status();
222 debug("-> status %x\n", stat);
226 static void non_prefetch_read(unsigned int addr,
227 unsigned int cmd, unsigned int *data)
229 writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
231 /*set up and execute the read */
232 writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
234 /*The result of the read is now in np_rdata */
235 *data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET);
240 static void non_prefetch_write(unsigned int addr,
241 unsigned int cmd, unsigned int data)
244 writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
245 /*set up the write */
246 writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
247 /*Execute the write by writing to NP_WDATA */
248 writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET);
253 static void crp_write(unsigned int offset, unsigned int data)
256 * The CRP address register bit 16 indicates that we want to do a
259 writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET);
260 writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET);
263 void pci_ixp_init(struct pci_controller *hose)
268 * Specify that the AHB bus is operating in big endian mode. Set up
269 * byte lane swapping between little-endian PCI and the big-endian
273 csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
277 writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
279 writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET);
282 * We configure the PCI inbound memory windows to be
283 * 1:1 mapped to SDRAM
285 crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000);
286 crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000);
287 crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000);
288 crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000);
291 * Enable CSR window at 64 MiB to allow PCI masters
292 * to continue prefetching past 64 MiB boundary.
294 crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000);
296 * Enable the IO window to be way up high, at 0xfffffc00
298 crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01);
300 /*Setup PCI-AHB and AHB-PCI address mappings */
301 writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET);
303 writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET);
305 writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET);
307 crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
309 crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
312 /* clear error bits in status register */
313 writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE,
314 PCI_CSR_BASE + PCI_ISR_OFFSET);
317 * Set Initialize Complete in PCI Control Register: allow IXP4XX to
318 * respond to PCI configuration cycles.
321 writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
323 hose->first_busno = 0;
324 hose->last_busno = 0;
326 /* System memory space */
327 pci_set_region(hose->regions + 0,
329 PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
331 /* PCI memory space */
332 pci_set_region(hose->regions + 1,
334 PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
336 pci_set_region(hose->regions + 2,
337 PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
339 hose->region_count = 3;
342 pci_ixp_hose_read_config_byte,
343 pci_ixp_hose_read_config_word,
344 pci_ixp_hose_read_config_dword,
345 pci_ixp_hose_write_config_byte,
346 pci_ixp_hose_write_config_word,
347 pci_ixp_hose_write_config_dword);
349 pci_register_hose(hose);
350 hose->last_busno = pci_hose_scan(hose);