2 * Copyright (c) 2010, CompuLab, Ltd.
3 * Author: Mike Rapoport <mike@compulab.co.il>
5 * Based on NVIDIA PCIe driver
6 * Copyright (c) 2008-2009, NVIDIA Corporation.
8 * Copyright (c) 2013-2014, NVIDIA Corporation.
10 * SPDX-License-Identifier: GPL-2.0
14 #define pr_fmt(fmt) "tegra-pcie: " fmt
25 #include <asm/arch/clock.h>
26 #include <asm/arch/powergate.h>
27 #include <asm/arch-tegra/xusb-padctl.h>
29 #include <linux/list.h>
31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define AFI_AXI_BAR0_SZ 0x00
36 #define AFI_AXI_BAR1_SZ 0x04
37 #define AFI_AXI_BAR2_SZ 0x08
38 #define AFI_AXI_BAR3_SZ 0x0c
39 #define AFI_AXI_BAR4_SZ 0x10
40 #define AFI_AXI_BAR5_SZ 0x14
42 #define AFI_AXI_BAR0_START 0x18
43 #define AFI_AXI_BAR1_START 0x1c
44 #define AFI_AXI_BAR2_START 0x20
45 #define AFI_AXI_BAR3_START 0x24
46 #define AFI_AXI_BAR4_START 0x28
47 #define AFI_AXI_BAR5_START 0x2c
49 #define AFI_FPCI_BAR0 0x30
50 #define AFI_FPCI_BAR1 0x34
51 #define AFI_FPCI_BAR2 0x38
52 #define AFI_FPCI_BAR3 0x3c
53 #define AFI_FPCI_BAR4 0x40
54 #define AFI_FPCI_BAR5 0x44
56 #define AFI_CACHE_BAR0_SZ 0x48
57 #define AFI_CACHE_BAR0_ST 0x4c
58 #define AFI_CACHE_BAR1_SZ 0x50
59 #define AFI_CACHE_BAR1_ST 0x54
61 #define AFI_MSI_BAR_SZ 0x60
62 #define AFI_MSI_FPCI_BAR_ST 0x64
63 #define AFI_MSI_AXI_BAR_ST 0x68
65 #define AFI_CONFIGURATION 0xac
66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
68 #define AFI_FPCI_ERROR_MASKS 0xb0
70 #define AFI_INTR_MASK 0xb4
71 #define AFI_INTR_MASK_INT_MASK (1 << 0)
72 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
74 #define AFI_SM_INTR_ENABLE 0xc4
75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
84 #define AFI_AFI_INTR_ENABLE 0xc8
85 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
86 #define AFI_INTR_EN_INI_DECERR (1 << 1)
87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
88 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
89 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
91 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
95 #define AFI_PCIE_CONFIG 0x0f8
96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
107 #define AFI_FUSE 0x104
108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
110 #define AFI_PEX0_CTRL 0x110
111 #define AFI_PEX1_CTRL 0x118
112 #define AFI_PEX2_CTRL 0x128
113 #define AFI_PEX_CTRL_RST (1 << 0)
114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
118 #define AFI_PLLE_CONTROL 0x160
119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
122 #define AFI_PEXBIAS_CTRL_0 0x168
124 #define PADS_CTL_SEL 0x0000009C
126 #define PADS_CTL 0x000000A0
127 #define PADS_CTL_IDDQ_1L (1 << 0)
128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
131 #define PADS_PLL_CTL_TEGRA20 0x000000B8
132 #define PADS_PLL_CTL_TEGRA30 0x000000B4
133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
144 #define PADS_REFCLK_CFG0 0x000000C8
145 #define PADS_REFCLK_CFG1 0x000000CC
148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
149 * entries, one entry per PCIe port. These field definitions and desired
150 * values aren't in the TRM, but do come from NVIDIA.
152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
157 /* Default value provided by HW engineering is 0xfa5c */
158 #define PADS_REFCLK_CFG_VALUE \
160 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
161 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
162 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
163 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
166 #define RP_VEND_XP 0x00000F00
167 #define RP_VEND_XP_DL_UP (1 << 30)
169 #define RP_VEND_CTL2 0x00000FA8
170 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
172 #define RP_PRIV_MISC 0x00000FE0
173 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
174 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
176 #define RP_LINK_CONTROL_STATUS 0x00000090
177 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
178 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
182 struct tegra_pcie_port {
183 struct tegra_pcie *pcie;
185 struct fdt_resource regs;
186 unsigned int num_lanes;
189 struct list_head list;
192 struct tegra_pcie_soc {
193 unsigned int num_ports;
194 unsigned long pads_pll_ctl;
195 unsigned long tx_ref_sel;
196 bool has_pex_clkreq_en;
197 bool has_pex_bias_ctrl;
200 bool force_pca_enable;
204 struct pci_controller hose;
206 struct fdt_resource pads;
207 struct fdt_resource afi;
208 struct fdt_resource cs;
210 struct fdt_resource prefetch;
211 struct fdt_resource mem;
212 struct fdt_resource io;
214 struct list_head ports;
217 const struct tegra_pcie_soc *soc;
218 struct tegra_xusb_phy *phy;
221 static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose)
223 return container_of(hose, struct tegra_pcie, hose);
226 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
227 unsigned long offset)
229 writel(value, pcie->afi.start + offset);
232 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
234 return readl(pcie->afi.start + offset);
237 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
238 unsigned long offset)
240 writel(value, pcie->pads.start + offset);
243 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
245 return readl(pcie->pads.start + offset);
248 static unsigned long rp_readl(struct tegra_pcie_port *port,
249 unsigned long offset)
251 return readl(port->regs.start + offset);
254 static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
255 unsigned long offset)
257 writel(value, port->regs.start + offset);
260 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
262 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
263 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
267 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
268 int where, unsigned long *address)
270 unsigned int bus = PCI_BUS(bdf);
273 unsigned int dev = PCI_DEV(bdf);
274 struct tegra_pcie_port *port;
276 list_for_each_entry(port, &pcie->ports, list) {
277 if (port->index + 1 == dev) {
278 *address = port->regs.start + (where & ~3);
283 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
290 static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf,
291 int where, u32 *value)
293 struct tegra_pcie *pcie = to_tegra_pcie(hose);
294 unsigned long address;
297 err = tegra_pcie_conf_address(pcie, bdf, where, &address);
303 *value = readl(address);
305 /* fixup root port class */
306 if (PCI_BUS(bdf) == 0) {
307 if (where == PCI_CLASS_REVISION) {
308 *value &= ~0x00ff0000;
309 *value |= PCI_CLASS_BRIDGE_PCI << 16;
316 static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf,
317 int where, u32 value)
319 struct tegra_pcie *pcie = to_tegra_pcie(hose);
320 unsigned long address;
323 err = tegra_pcie_conf_address(pcie, bdf, where, &address);
327 writel(value, address);
332 static int tegra_pcie_port_parse_dt(const void *fdt, int node,
333 struct tegra_pcie_port *port)
338 addr = fdt_getprop(fdt, node, "assigned-addresses", &len);
340 error("property \"assigned-addresses\" not found");
341 return -FDT_ERR_NOTFOUND;
344 port->regs.start = fdt32_to_cpu(addr[2]);
345 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
350 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
353 enum fdt_compat_id id = fdtdec_lookup(fdt, node);
356 case COMPAT_NVIDIA_TEGRA20_PCIE:
359 debug("single-mode configuration\n");
360 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
364 debug("dual-mode configuration\n");
365 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
370 case COMPAT_NVIDIA_TEGRA30_PCIE:
373 debug("4x1, 2x1 configuration\n");
374 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
378 debug("2x3 configuration\n");
379 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
383 debug("4x1, 1x2 configuration\n");
384 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
389 case COMPAT_NVIDIA_TEGRA124_PCIE:
390 case COMPAT_NVIDIA_TEGRA210_PCIE:
393 debug("4x1, 1x1 configuration\n");
394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
398 debug("2x1, 1x1 configuration\n");
399 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
408 return -FDT_ERR_NOTFOUND;
411 static int tegra_pcie_parse_dt_ranges(const void *fdt, int node,
412 struct tegra_pcie *pcie)
414 int parent, na_parent, na_pcie, ns_pcie;
415 const u32 *ptr, *end;
418 parent = fdt_parent_offset(fdt, node);
420 error("Can't find PCI parent node\n");
421 return -FDT_ERR_NOTFOUND;
424 na_parent = fdt_address_cells(fdt, parent);
426 error("bad #address-cells for PCIE parent\n");
427 return -FDT_ERR_NOTFOUND;
430 na_pcie = fdt_address_cells(fdt, node);
432 error("bad #address-cells for PCIE\n");
433 return -FDT_ERR_NOTFOUND;
436 ns_pcie = fdt_size_cells(fdt, node);
438 error("bad #size-cells for PCIE\n");
439 return -FDT_ERR_NOTFOUND;
442 ptr = fdt_getprop(fdt, node, "ranges", &len);
444 error("missing \"ranges\" property");
445 return -FDT_ERR_NOTFOUND;
451 struct fdt_resource *res = NULL;
452 u32 space = fdt32_to_cpu(*ptr);
454 switch ((space >> 24) & 0x3) {
459 case 0x02: /* 32 bit */
460 case 0x03: /* 64 bit */
461 if (space & (1 << 30))
462 res = &pcie->prefetch;
470 int start_low = na_pcie + (na_parent - 1);
471 int size_low = na_pcie + na_parent + (ns_pcie - 1);
472 res->start = fdt32_to_cpu(ptr[start_low]);
473 res->end = res->start + fdt32_to_cpu(ptr[size_low]);
476 ptr += na_pcie + na_parent + ns_pcie;
479 debug("PCI regions:\n");
480 debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end);
481 debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start,
483 debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start,
484 &pcie->prefetch.end);
489 static int tegra_pcie_parse_port_info(const void *fdt, int node,
493 struct fdt_pci_addr addr;
496 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
498 error("failed to parse \"nvidia,num-lanes\" property");
504 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr);
506 error("failed to parse \"reg\" property");
510 *index = PCI_DEV(addr.phys_hi) - 1;
515 static int tegra_pcie_parse_dt(const void *fdt, int node,
516 struct tegra_pcie *pcie)
521 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads",
524 error("resource \"pads\" not found");
528 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi",
531 error("resource \"afi\" not found");
535 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs",
538 error("resource \"cs\" not found");
542 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
544 err = tegra_xusb_phy_prepare(pcie->phy);
546 error("failed to prepare PHY: %d", err);
551 err = tegra_pcie_parse_dt_ranges(fdt, node, pcie);
553 error("failed to parse \"ranges\" property");
557 fdt_for_each_subnode(fdt, subnode, node) {
558 unsigned int index = 0, num_lanes = 0;
559 struct tegra_pcie_port *port;
561 err = tegra_pcie_parse_port_info(fdt, subnode, &index,
564 error("failed to obtain root port info");
568 lanes |= num_lanes << (index << 3);
570 if (!fdtdec_get_is_enabled(fdt, subnode))
573 port = malloc(sizeof(*port));
577 memset(port, 0, sizeof(*port));
578 port->num_lanes = num_lanes;
581 err = tegra_pcie_port_parse_dt(fdt, subnode, port);
587 list_add_tail(&port->list, &pcie->ports);
591 err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar);
593 error("invalid lane configuration");
600 int __weak tegra_pcie_board_init(void)
605 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
607 const struct tegra_pcie_soc *soc = pcie->soc;
611 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
612 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
613 reset_set_enable(PERIPH_ID_AFI, 1);
614 reset_set_enable(PERIPH_ID_PCIE, 1);
616 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
618 error("failed to power off PCIe partition: %d", err);
622 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
625 error("failed to power up PCIe partition: %d", err);
629 /* take AFI controller out of reset */
630 reset_set_enable(PERIPH_ID_AFI, 0);
632 /* enable AFI clock */
633 clock_enable(PERIPH_ID_AFI);
635 if (soc->has_cml_clk) {
636 /* enable CML clock */
637 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
640 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
643 err = tegra_plle_enable();
645 error("failed to enable PLLE: %d\n", err);
652 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
654 const struct tegra_pcie_soc *soc = pcie->soc;
655 unsigned long start = get_timer(0);
658 while (get_timer(start) < timeout) {
659 value = pads_readl(pcie, soc->pads_pll_ctl);
660 if (value & PADS_PLL_CTL_LOCKDET)
667 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
669 const struct tegra_pcie_soc *soc = pcie->soc;
673 /* initialize internal PHY, enable up to 16 PCIe lanes */
674 pads_writel(pcie, 0, PADS_CTL_SEL);
676 /* override IDDQ to 1 on all 4 lanes */
677 value = pads_readl(pcie, PADS_CTL);
678 value |= PADS_CTL_IDDQ_1L;
679 pads_writel(pcie, value, PADS_CTL);
682 * Set up PHY PLL inputs select PLLE output as refclock, set TX
683 * ref sel to div10 (not div5).
685 value = pads_readl(pcie, soc->pads_pll_ctl);
686 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
687 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
688 pads_writel(pcie, value, soc->pads_pll_ctl);
691 value = pads_readl(pcie, soc->pads_pll_ctl);
692 value &= ~PADS_PLL_CTL_RST_B4SM;
693 pads_writel(pcie, value, soc->pads_pll_ctl);
697 /* take PLL out of reset */
698 value = pads_readl(pcie, soc->pads_pll_ctl);
699 value |= PADS_PLL_CTL_RST_B4SM;
700 pads_writel(pcie, value, soc->pads_pll_ctl);
702 /* configure the reference clock driver */
703 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
704 pads_writel(pcie, value, PADS_REFCLK_CFG0);
706 if (soc->num_ports > 2)
707 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
709 /* wait for the PLL to lock */
710 err = tegra_pcie_pll_wait(pcie, 500);
712 error("PLL failed to lock: %d", err);
716 /* turn off IDDQ override */
717 value = pads_readl(pcie, PADS_CTL);
718 value &= ~PADS_CTL_IDDQ_1L;
719 pads_writel(pcie, value, PADS_CTL);
721 /* enable TX/RX data */
722 value = pads_readl(pcie, PADS_CTL);
723 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
724 pads_writel(pcie, value, PADS_CTL);
729 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
731 const struct tegra_pcie_soc *soc = pcie->soc;
732 struct tegra_pcie_port *port;
737 value = afi_readl(pcie, AFI_PLLE_CONTROL);
738 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
739 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
740 afi_writel(pcie, value, AFI_PLLE_CONTROL);
743 if (soc->has_pex_bias_ctrl)
744 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
746 value = afi_readl(pcie, AFI_PCIE_CONFIG);
747 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
748 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
750 list_for_each_entry(port, &pcie->ports, list)
751 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
753 afi_writel(pcie, value, AFI_PCIE_CONFIG);
755 value = afi_readl(pcie, AFI_FUSE);
758 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
760 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
762 afi_writel(pcie, value, AFI_FUSE);
765 err = tegra_xusb_phy_enable(pcie->phy);
767 err = tegra_pcie_phy_enable(pcie);
770 error("failed to power on PHY: %d\n", err);
774 /* take the PCIEXCLK logic out of reset */
775 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
777 /* finally enable PCIe */
778 value = afi_readl(pcie, AFI_CONFIGURATION);
779 value |= AFI_CONFIGURATION_EN_FPCI;
780 afi_writel(pcie, value, AFI_CONFIGURATION);
782 /* disable all interrupts */
783 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
784 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
785 afi_writel(pcie, 0, AFI_INTR_MASK);
786 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
791 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
793 unsigned long fpci, axi, size;
795 /* BAR 0: type 1 extended configuration space */
797 size = fdt_resource_size(&pcie->cs);
798 axi = pcie->cs.start;
800 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
801 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
802 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
804 /* BAR 1: downstream I/O */
806 size = fdt_resource_size(&pcie->io);
807 axi = pcie->io.start;
809 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
810 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
811 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
813 /* BAR 2: prefetchable memory */
814 fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
815 size = fdt_resource_size(&pcie->prefetch);
816 axi = pcie->prefetch.start;
818 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
819 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
820 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
822 /* BAR 3: non-prefetchable memory */
823 fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
824 size = fdt_resource_size(&pcie->mem);
825 axi = pcie->mem.start;
827 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
828 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
829 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
831 /* NULL out the remaining BARs as they are not used */
832 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
833 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
834 afi_writel(pcie, 0, AFI_FPCI_BAR4);
836 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
837 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
838 afi_writel(pcie, 0, AFI_FPCI_BAR5);
840 /* map all upstream transactions as uncached */
841 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
842 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
843 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
844 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
846 /* MSI translations are setup only when needed */
847 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
848 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
849 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
850 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
853 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
855 unsigned long ret = 0;
857 switch (port->index) {
874 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
876 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
879 /* pulse reset signel */
880 value = afi_readl(port->pcie, ctrl);
881 value &= ~AFI_PEX_CTRL_RST;
882 afi_writel(port->pcie, value, ctrl);
886 value = afi_readl(port->pcie, ctrl);
887 value |= AFI_PEX_CTRL_RST;
888 afi_writel(port->pcie, value, ctrl);
891 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
893 const struct tegra_pcie_soc *soc = port->pcie->soc;
894 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
897 /* enable reference clock */
898 value = afi_readl(port->pcie, ctrl);
899 value |= AFI_PEX_CTRL_REFCLK_EN;
901 if (port->pcie->soc->has_pex_clkreq_en)
902 value |= AFI_PEX_CTRL_CLKREQ_EN;
904 value |= AFI_PEX_CTRL_OVERRIDE_EN;
906 afi_writel(port->pcie, value, ctrl);
908 tegra_pcie_port_reset(port);
910 if (soc->force_pca_enable) {
911 value = rp_readl(port, RP_VEND_CTL2);
912 value |= RP_VEND_CTL2_PCA_ENABLE;
913 rp_writel(port, value, RP_VEND_CTL2);
917 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
919 unsigned int retries = 3;
922 value = rp_readl(port, RP_PRIV_MISC);
923 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
924 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
925 rp_writel(port, value, RP_PRIV_MISC);
928 unsigned int timeout = 200;
931 value = rp_readl(port, RP_VEND_XP);
932 if (value & RP_VEND_XP_DL_UP)
939 debug("link %u down, retrying\n", port->index);
946 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
947 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
954 tegra_pcie_port_reset(port);
960 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
962 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
965 /* assert port reset */
966 value = afi_readl(port->pcie, ctrl);
967 value &= ~AFI_PEX_CTRL_RST;
968 afi_writel(port->pcie, value, ctrl);
970 /* disable reference clock */
971 value = afi_readl(port->pcie, ctrl);
972 value &= ~AFI_PEX_CTRL_REFCLK_EN;
973 afi_writel(port->pcie, value, ctrl);
976 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
978 list_del(&port->list);
982 static int tegra_pcie_enable(struct tegra_pcie *pcie)
984 struct tegra_pcie_port *port, *tmp;
986 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
987 debug("probing port %u, using %u lanes\n", port->index,
990 tegra_pcie_port_enable(port);
992 if (tegra_pcie_port_check_link(port))
995 debug("link %u down, ignoring\n", port->index);
997 tegra_pcie_port_disable(port);
998 tegra_pcie_port_free(port);
1004 static const struct tegra_pcie_soc tegra20_pcie_soc = {
1006 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1007 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
1008 .has_pex_clkreq_en = false,
1009 .has_pex_bias_ctrl = false,
1010 .has_cml_clk = false,
1012 .force_pca_enable = false,
1015 static const struct tegra_pcie_soc tegra30_pcie_soc = {
1017 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1018 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1019 .has_pex_clkreq_en = true,
1020 .has_pex_bias_ctrl = true,
1021 .has_cml_clk = true,
1023 .force_pca_enable = false,
1026 static const struct tegra_pcie_soc tegra124_pcie_soc = {
1028 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1029 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1030 .has_pex_clkreq_en = true,
1031 .has_pex_bias_ctrl = true,
1032 .has_cml_clk = true,
1034 .force_pca_enable = false,
1037 static const struct tegra_pcie_soc tegra210_pcie_soc = {
1039 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1040 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1041 .has_pex_clkreq_en = true,
1042 .has_pex_bias_ctrl = true,
1043 .has_cml_clk = true,
1045 .force_pca_enable = true,
1048 static int process_nodes(const void *fdt, int nodes[], unsigned int count)
1052 uint32_t pci_dram_size;
1054 /* Clip PCI-accessible DRAM to 32-bits */
1055 dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size;
1056 if (dram_end > 0x100000000)
1057 dram_end = 0x100000000;
1058 pci_dram_size = dram_end - NV_PA_SDRAM_BASE;
1060 for (i = 0; i < count; i++) {
1061 const struct tegra_pcie_soc *soc;
1062 struct tegra_pcie *pcie;
1063 enum fdt_compat_id id;
1066 if (!fdtdec_get_is_enabled(fdt, nodes[i]))
1069 id = fdtdec_lookup(fdt, nodes[i]);
1071 case COMPAT_NVIDIA_TEGRA20_PCIE:
1072 soc = &tegra20_pcie_soc;
1075 case COMPAT_NVIDIA_TEGRA30_PCIE:
1076 soc = &tegra30_pcie_soc;
1079 case COMPAT_NVIDIA_TEGRA124_PCIE:
1080 soc = &tegra124_pcie_soc;
1083 case COMPAT_NVIDIA_TEGRA210_PCIE:
1084 soc = &tegra210_pcie_soc;
1088 error("unsupported compatible: %s",
1089 fdtdec_get_compatible(id));
1093 pcie = malloc(sizeof(*pcie));
1095 error("failed to allocate controller");
1099 memset(pcie, 0, sizeof(*pcie));
1102 INIT_LIST_HEAD(&pcie->ports);
1104 err = tegra_pcie_parse_dt(fdt, nodes[i], pcie);
1110 err = tegra_pcie_power_on(pcie);
1112 error("failed to power on");
1116 err = tegra_pcie_enable_controller(pcie);
1118 error("failed to enable controller");
1122 tegra_pcie_setup_translations(pcie);
1124 err = tegra_pcie_enable(pcie);
1126 error("failed to enable PCIe");
1130 pcie->hose.first_busno = 0;
1131 pcie->hose.current_busno = 0;
1132 pcie->hose.last_busno = 0;
1134 pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE,
1135 NV_PA_SDRAM_BASE, pci_dram_size,
1136 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1138 pci_set_region(&pcie->hose.regions[1], pcie->io.start,
1139 pcie->io.start, fdt_resource_size(&pcie->io),
1142 pci_set_region(&pcie->hose.regions[2], pcie->mem.start,
1143 pcie->mem.start, fdt_resource_size(&pcie->mem),
1146 pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start,
1147 pcie->prefetch.start,
1148 fdt_resource_size(&pcie->prefetch),
1149 PCI_REGION_MEM | PCI_REGION_PREFETCH);
1151 pcie->hose.region_count = 4;
1153 pci_set_ops(&pcie->hose,
1154 pci_hose_read_config_byte_via_dword,
1155 pci_hose_read_config_word_via_dword,
1156 tegra_pcie_read_conf,
1157 pci_hose_write_config_byte_via_dword,
1158 pci_hose_write_config_word_via_dword,
1159 tegra_pcie_write_conf);
1161 pci_register_hose(&pcie->hose);
1163 #ifdef CONFIG_PCI_SCAN_SHOW
1164 printf("PCI: Enumerating devices...\n");
1165 printf("---------------------------------------\n");
1166 printf(" Device ID Description\n");
1167 printf(" ------ -- -----------\n");
1170 pcie->hose.last_busno = pci_hose_scan(&pcie->hose);
1176 void pci_init_board(void)
1178 const void *fdt = gd->fdt_blob;
1179 int count, nodes[1];
1181 tegra_pcie_board_init();
1183 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
1184 COMPAT_NVIDIA_TEGRA210_PCIE,
1185 nodes, ARRAY_SIZE(nodes));
1186 if (process_nodes(fdt, nodes, count))
1189 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
1190 COMPAT_NVIDIA_TEGRA124_PCIE,
1191 nodes, ARRAY_SIZE(nodes));
1192 if (process_nodes(fdt, nodes, count))
1195 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
1196 COMPAT_NVIDIA_TEGRA30_PCIE,
1197 nodes, ARRAY_SIZE(nodes));
1198 if (process_nodes(fdt, nodes, count))
1201 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
1202 COMPAT_NVIDIA_TEGRA20_PCIE,
1203 nodes, ARRAY_SIZE(nodes));
1204 if (process_nodes(fdt, nodes, count))
1208 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
1210 if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0)