2 * Copyright (c) 2010, CompuLab, Ltd.
3 * Author: Mike Rapoport <mike@compulab.co.il>
5 * Based on NVIDIA PCIe driver
6 * Copyright (c) 2008-2009, NVIDIA Corporation.
8 * Copyright (c) 2013-2014, NVIDIA Corporation.
10 * SPDX-License-Identifier: GPL-2.0
13 #define pr_fmt(fmt) "tegra-pcie: " fmt
25 #include <asm/arch/clock.h>
26 #include <asm/arch/powergate.h>
27 #include <asm/arch-tegra/xusb-padctl.h>
29 #include <linux/list.h>
31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define AFI_AXI_BAR0_SZ 0x00
36 #define AFI_AXI_BAR1_SZ 0x04
37 #define AFI_AXI_BAR2_SZ 0x08
38 #define AFI_AXI_BAR3_SZ 0x0c
39 #define AFI_AXI_BAR4_SZ 0x10
40 #define AFI_AXI_BAR5_SZ 0x14
42 #define AFI_AXI_BAR0_START 0x18
43 #define AFI_AXI_BAR1_START 0x1c
44 #define AFI_AXI_BAR2_START 0x20
45 #define AFI_AXI_BAR3_START 0x24
46 #define AFI_AXI_BAR4_START 0x28
47 #define AFI_AXI_BAR5_START 0x2c
49 #define AFI_FPCI_BAR0 0x30
50 #define AFI_FPCI_BAR1 0x34
51 #define AFI_FPCI_BAR2 0x38
52 #define AFI_FPCI_BAR3 0x3c
53 #define AFI_FPCI_BAR4 0x40
54 #define AFI_FPCI_BAR5 0x44
56 #define AFI_CACHE_BAR0_SZ 0x48
57 #define AFI_CACHE_BAR0_ST 0x4c
58 #define AFI_CACHE_BAR1_SZ 0x50
59 #define AFI_CACHE_BAR1_ST 0x54
61 #define AFI_MSI_BAR_SZ 0x60
62 #define AFI_MSI_FPCI_BAR_ST 0x64
63 #define AFI_MSI_AXI_BAR_ST 0x68
65 #define AFI_CONFIGURATION 0xac
66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
68 #define AFI_FPCI_ERROR_MASKS 0xb0
70 #define AFI_INTR_MASK 0xb4
71 #define AFI_INTR_MASK_INT_MASK (1 << 0)
72 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
74 #define AFI_SM_INTR_ENABLE 0xc4
75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
84 #define AFI_AFI_INTR_ENABLE 0xc8
85 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
86 #define AFI_INTR_EN_INI_DECERR (1 << 1)
87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
88 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
89 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
91 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
95 #define AFI_PCIE_CONFIG 0x0f8
96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
107 #define AFI_FUSE 0x104
108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
110 #define AFI_PEX0_CTRL 0x110
111 #define AFI_PEX1_CTRL 0x118
112 #define AFI_PEX2_CTRL 0x128
113 #define AFI_PEX_CTRL_RST (1 << 0)
114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
118 #define AFI_PLLE_CONTROL 0x160
119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
122 #define AFI_PEXBIAS_CTRL_0 0x168
124 #define PADS_CTL_SEL 0x0000009C
126 #define PADS_CTL 0x000000A0
127 #define PADS_CTL_IDDQ_1L (1 << 0)
128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
131 #define PADS_PLL_CTL_TEGRA20 0x000000B8
132 #define PADS_PLL_CTL_TEGRA30 0x000000B4
133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
144 #define PADS_REFCLK_CFG0 0x000000C8
145 #define PADS_REFCLK_CFG1 0x000000CC
148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
149 * entries, one entry per PCIe port. These field definitions and desired
150 * values aren't in the TRM, but do come from NVIDIA.
152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
157 /* Default value provided by HW engineering is 0xfa5c */
158 #define PADS_REFCLK_CFG_VALUE \
160 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
161 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
162 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
163 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
166 #define RP_VEND_XP 0x00000F00
167 #define RP_VEND_XP_DL_UP (1 << 30)
169 #define RP_VEND_CTL2 0x00000FA8
170 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
172 #define RP_PRIV_MISC 0x00000FE0
173 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
174 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
176 #define RP_LINK_CONTROL_STATUS 0x00000090
177 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
178 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
187 struct tegra_pcie_port {
188 struct tegra_pcie *pcie;
190 struct fdt_resource regs;
191 unsigned int num_lanes;
194 struct list_head list;
197 struct tegra_pcie_soc {
198 unsigned int num_ports;
199 unsigned long pads_pll_ctl;
200 unsigned long tx_ref_sel;
201 bool has_pex_clkreq_en;
202 bool has_pex_bias_ctrl;
205 bool force_pca_enable;
209 struct pci_controller hose;
211 struct fdt_resource pads;
212 struct fdt_resource afi;
213 struct fdt_resource cs;
215 struct list_head ports;
218 const struct tegra_pcie_soc *soc;
219 struct tegra_xusb_phy *phy;
222 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
223 unsigned long offset)
225 writel(value, pcie->afi.start + offset);
228 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
230 return readl(pcie->afi.start + offset);
233 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
234 unsigned long offset)
236 writel(value, pcie->pads.start + offset);
239 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
241 return readl(pcie->pads.start + offset);
244 static unsigned long rp_readl(struct tegra_pcie_port *port,
245 unsigned long offset)
247 return readl(port->regs.start + offset);
250 static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
251 unsigned long offset)
253 writel(value, port->regs.start + offset);
256 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
258 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
259 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
263 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
264 int where, unsigned long *address)
266 unsigned int bus = PCI_BUS(bdf);
269 unsigned int dev = PCI_DEV(bdf);
270 struct tegra_pcie_port *port;
272 list_for_each_entry(port, &pcie->ports, list) {
273 if (port->index + 1 == dev) {
274 *address = port->regs.start + (where & ~3);
280 #ifdef CONFIG_TEGRA20
281 unsigned int dev = PCI_DEV(bdf);
286 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
291 static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
292 uint offset, ulong *valuep,
293 enum pci_size_t size)
295 struct tegra_pcie *pcie = dev_get_priv(bus);
296 unsigned long address, value;
299 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
305 value = readl(address);
307 #ifdef CONFIG_TEGRA20
308 /* fixup root port class */
309 if (PCI_BUS(bdf) == 0) {
310 if ((offset & ~3) == PCI_CLASS_REVISION) {
311 value &= ~0x00ff0000;
312 value |= PCI_CLASS_BRIDGE_PCI << 16;
318 *valuep = pci_conv_32_to_size(value, offset, size);
323 static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
324 uint offset, ulong value,
325 enum pci_size_t size)
327 struct tegra_pcie *pcie = dev_get_priv(bus);
328 unsigned long address;
332 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
336 old = readl(address);
337 value = pci_conv_size_to_32(old, value, offset, size);
338 writel(value, address);
343 static int tegra_pcie_port_parse_dt(const void *fdt, int node,
344 struct tegra_pcie_port *port)
349 addr = fdt_getprop(fdt, node, "assigned-addresses", &len);
351 error("property \"assigned-addresses\" not found");
352 return -FDT_ERR_NOTFOUND;
355 port->regs.start = fdt32_to_cpu(addr[2]);
356 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
361 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
362 enum tegra_pci_id id, unsigned long *xbar)
368 debug("single-mode configuration\n");
369 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
373 debug("dual-mode configuration\n");
374 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
381 debug("4x1, 2x1 configuration\n");
382 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
386 debug("2x3 configuration\n");
387 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
391 debug("4x1, 1x2 configuration\n");
392 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
400 debug("4x1, 1x1 configuration\n");
401 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
405 debug("2x1, 1x1 configuration\n");
406 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
414 return -FDT_ERR_NOTFOUND;
417 static int tegra_pcie_parse_port_info(const void *fdt, int node,
421 struct fdt_pci_addr addr;
424 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
426 error("failed to parse \"nvidia,num-lanes\" property");
432 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr);
434 error("failed to parse \"reg\" property");
438 *index = PCI_DEV(addr.phys_hi) - 1;
443 int __weak tegra_pcie_board_init(void)
448 static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
449 struct tegra_pcie *pcie)
454 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads",
457 error("resource \"pads\" not found");
461 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi",
464 error("resource \"afi\" not found");
468 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs",
471 error("resource \"cs\" not found");
475 err = tegra_pcie_board_init();
477 error("tegra_pcie_board_init() failed: err=%d", err);
481 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
483 err = tegra_xusb_phy_prepare(pcie->phy);
485 error("failed to prepare PHY: %d", err);
490 fdt_for_each_subnode(fdt, subnode, node) {
491 unsigned int index = 0, num_lanes = 0;
492 struct tegra_pcie_port *port;
494 err = tegra_pcie_parse_port_info(fdt, subnode, &index,
497 error("failed to obtain root port info");
501 lanes |= num_lanes << (index << 3);
503 if (!fdtdec_get_is_enabled(fdt, subnode))
506 port = malloc(sizeof(*port));
510 memset(port, 0, sizeof(*port));
511 port->num_lanes = num_lanes;
514 err = tegra_pcie_port_parse_dt(fdt, subnode, port);
520 list_add_tail(&port->list, &pcie->ports);
524 err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar);
526 error("invalid lane configuration");
533 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
535 const struct tegra_pcie_soc *soc = pcie->soc;
539 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
540 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
541 reset_set_enable(PERIPH_ID_AFI, 1);
542 reset_set_enable(PERIPH_ID_PCIE, 1);
544 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
546 error("failed to power off PCIe partition: %d", err);
550 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
553 error("failed to power up PCIe partition: %d", err);
557 /* take AFI controller out of reset */
558 reset_set_enable(PERIPH_ID_AFI, 0);
560 /* enable AFI clock */
561 clock_enable(PERIPH_ID_AFI);
563 if (soc->has_cml_clk) {
564 /* enable CML clock */
565 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
568 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
571 err = tegra_plle_enable();
573 error("failed to enable PLLE: %d\n", err);
580 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
582 const struct tegra_pcie_soc *soc = pcie->soc;
583 unsigned long start = get_timer(0);
586 while (get_timer(start) < timeout) {
587 value = pads_readl(pcie, soc->pads_pll_ctl);
588 if (value & PADS_PLL_CTL_LOCKDET)
595 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
597 const struct tegra_pcie_soc *soc = pcie->soc;
601 /* initialize internal PHY, enable up to 16 PCIe lanes */
602 pads_writel(pcie, 0, PADS_CTL_SEL);
604 /* override IDDQ to 1 on all 4 lanes */
605 value = pads_readl(pcie, PADS_CTL);
606 value |= PADS_CTL_IDDQ_1L;
607 pads_writel(pcie, value, PADS_CTL);
610 * Set up PHY PLL inputs select PLLE output as refclock, set TX
611 * ref sel to div10 (not div5).
613 value = pads_readl(pcie, soc->pads_pll_ctl);
614 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
615 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
616 pads_writel(pcie, value, soc->pads_pll_ctl);
619 value = pads_readl(pcie, soc->pads_pll_ctl);
620 value &= ~PADS_PLL_CTL_RST_B4SM;
621 pads_writel(pcie, value, soc->pads_pll_ctl);
625 /* take PLL out of reset */
626 value = pads_readl(pcie, soc->pads_pll_ctl);
627 value |= PADS_PLL_CTL_RST_B4SM;
628 pads_writel(pcie, value, soc->pads_pll_ctl);
630 /* configure the reference clock driver */
631 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
632 pads_writel(pcie, value, PADS_REFCLK_CFG0);
634 if (soc->num_ports > 2)
635 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
637 /* wait for the PLL to lock */
638 err = tegra_pcie_pll_wait(pcie, 500);
640 error("PLL failed to lock: %d", err);
644 /* turn off IDDQ override */
645 value = pads_readl(pcie, PADS_CTL);
646 value &= ~PADS_CTL_IDDQ_1L;
647 pads_writel(pcie, value, PADS_CTL);
649 /* enable TX/RX data */
650 value = pads_readl(pcie, PADS_CTL);
651 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
652 pads_writel(pcie, value, PADS_CTL);
657 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
659 const struct tegra_pcie_soc *soc = pcie->soc;
660 struct tegra_pcie_port *port;
665 value = afi_readl(pcie, AFI_PLLE_CONTROL);
666 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
667 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
668 afi_writel(pcie, value, AFI_PLLE_CONTROL);
671 if (soc->has_pex_bias_ctrl)
672 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
674 value = afi_readl(pcie, AFI_PCIE_CONFIG);
675 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
676 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
678 list_for_each_entry(port, &pcie->ports, list)
679 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
681 afi_writel(pcie, value, AFI_PCIE_CONFIG);
683 value = afi_readl(pcie, AFI_FUSE);
686 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
688 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
690 afi_writel(pcie, value, AFI_FUSE);
693 err = tegra_xusb_phy_enable(pcie->phy);
695 err = tegra_pcie_phy_enable(pcie);
698 error("failed to power on PHY: %d\n", err);
702 /* take the PCIEXCLK logic out of reset */
703 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
705 /* finally enable PCIe */
706 value = afi_readl(pcie, AFI_CONFIGURATION);
707 value |= AFI_CONFIGURATION_EN_FPCI;
708 afi_writel(pcie, value, AFI_CONFIGURATION);
710 /* disable all interrupts */
711 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
712 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
713 afi_writel(pcie, 0, AFI_INTR_MASK);
714 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
719 static int tegra_pcie_setup_translations(struct udevice *bus)
721 struct tegra_pcie *pcie = dev_get_priv(bus);
722 unsigned long fpci, axi, size;
723 struct pci_region *io, *mem, *pref;
726 /* BAR 0: type 1 extended configuration space */
728 size = fdt_resource_size(&pcie->cs);
729 axi = pcie->cs.start;
731 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
732 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
733 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
735 count = pci_get_regions(bus, &io, &mem, &pref);
739 /* BAR 1: downstream I/O */
742 axi = io->phys_start;
744 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
745 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
746 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
748 /* BAR 2: prefetchable memory */
749 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
751 axi = pref->phys_start;
753 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
754 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
755 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
757 /* BAR 3: non-prefetchable memory */
758 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
760 axi = mem->phys_start;
762 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
763 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
764 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
766 /* NULL out the remaining BARs as they are not used */
767 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
768 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
769 afi_writel(pcie, 0, AFI_FPCI_BAR4);
771 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
772 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
773 afi_writel(pcie, 0, AFI_FPCI_BAR5);
775 /* map all upstream transactions as uncached */
776 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
777 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
778 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
779 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
781 /* MSI translations are setup only when needed */
782 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
783 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
784 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
785 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
790 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
792 unsigned long ret = 0;
794 switch (port->index) {
811 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
813 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
816 /* pulse reset signel */
817 value = afi_readl(port->pcie, ctrl);
818 value &= ~AFI_PEX_CTRL_RST;
819 afi_writel(port->pcie, value, ctrl);
823 value = afi_readl(port->pcie, ctrl);
824 value |= AFI_PEX_CTRL_RST;
825 afi_writel(port->pcie, value, ctrl);
828 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
830 const struct tegra_pcie_soc *soc = port->pcie->soc;
831 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
834 /* enable reference clock */
835 value = afi_readl(port->pcie, ctrl);
836 value |= AFI_PEX_CTRL_REFCLK_EN;
838 if (port->pcie->soc->has_pex_clkreq_en)
839 value |= AFI_PEX_CTRL_CLKREQ_EN;
841 value |= AFI_PEX_CTRL_OVERRIDE_EN;
843 afi_writel(port->pcie, value, ctrl);
845 tegra_pcie_port_reset(port);
847 if (soc->force_pca_enable) {
848 value = rp_readl(port, RP_VEND_CTL2);
849 value |= RP_VEND_CTL2_PCA_ENABLE;
850 rp_writel(port, value, RP_VEND_CTL2);
854 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
856 unsigned int retries = 3;
859 value = rp_readl(port, RP_PRIV_MISC);
860 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
861 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
862 rp_writel(port, value, RP_PRIV_MISC);
865 unsigned int timeout = 200;
868 value = rp_readl(port, RP_VEND_XP);
869 if (value & RP_VEND_XP_DL_UP)
876 debug("link %u down, retrying\n", port->index);
883 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
884 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
891 tegra_pcie_port_reset(port);
897 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
899 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
902 /* assert port reset */
903 value = afi_readl(port->pcie, ctrl);
904 value &= ~AFI_PEX_CTRL_RST;
905 afi_writel(port->pcie, value, ctrl);
907 /* disable reference clock */
908 value = afi_readl(port->pcie, ctrl);
909 value &= ~AFI_PEX_CTRL_REFCLK_EN;
910 afi_writel(port->pcie, value, ctrl);
913 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
915 list_del(&port->list);
919 static int tegra_pcie_enable(struct tegra_pcie *pcie)
921 struct tegra_pcie_port *port, *tmp;
923 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
924 debug("probing port %u, using %u lanes\n", port->index,
927 tegra_pcie_port_enable(port);
929 if (tegra_pcie_port_check_link(port))
932 debug("link %u down, ignoring\n", port->index);
934 tegra_pcie_port_disable(port);
935 tegra_pcie_port_free(port);
941 static const struct tegra_pcie_soc pci_tegra_soc[] = {
944 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
945 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
946 .has_pex_clkreq_en = false,
947 .has_pex_bias_ctrl = false,
948 .has_cml_clk = false,
953 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
954 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
955 .has_pex_clkreq_en = true,
956 .has_pex_bias_ctrl = true,
962 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
963 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
964 .has_pex_clkreq_en = true,
965 .has_pex_bias_ctrl = true,
971 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
972 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
973 .has_pex_clkreq_en = true,
974 .has_pex_bias_ctrl = true,
977 .force_pca_enable = true,
981 static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
983 struct tegra_pcie *pcie = dev_get_priv(dev);
984 enum tegra_pci_id id;
986 id = dev_get_driver_data(dev);
987 pcie->soc = &pci_tegra_soc[id];
989 INIT_LIST_HEAD(&pcie->ports);
991 if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie))
997 static int pci_tegra_probe(struct udevice *dev)
999 struct tegra_pcie *pcie = dev_get_priv(dev);
1002 err = tegra_pcie_power_on(pcie);
1004 error("failed to power on");
1008 err = tegra_pcie_enable_controller(pcie);
1010 error("failed to enable controller");
1014 err = tegra_pcie_setup_translations(dev);
1016 error("failed to decode ranges");
1020 err = tegra_pcie_enable(pcie);
1022 error("failed to enable PCIe");
1029 static const struct dm_pci_ops pci_tegra_ops = {
1030 .read_config = pci_tegra_read_config,
1031 .write_config = pci_tegra_write_config,
1034 static const struct udevice_id pci_tegra_ids[] = {
1035 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1036 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1037 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1038 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
1042 U_BOOT_DRIVER(pci_tegra) = {
1043 .name = "pci_tegra",
1045 .of_match = pci_tegra_ids,
1046 .ops = &pci_tegra_ops,
1047 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
1048 .probe = pci_tegra_probe,
1049 .priv_auto_alloc_size = sizeof(struct tegra_pcie),