2 * Copyright (C) 2015 Marvell International Ltd.
4 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
7 * - drivers/pci/pcie_imx.c
8 * - drivers/pci/pci_mvebu.c
9 * - drivers/pci/pcie_xilinx.c
11 * SPDX-License-Identifier: GPL-2.0+
19 DECLARE_GLOBAL_DATA_PTR;
21 /* PCI Config space registers */
22 #define PCIE_CONFIG_BAR0 0x10
23 #define PCIE_LINK_STATUS_REG 0x80
24 #define PCIE_LINK_STATUS_SPEED_OFF 16
25 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
26 #define PCIE_LINK_STATUS_WIDTH_OFF 20
27 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
29 /* Resizable bar capability registers */
30 #define RESIZABLE_BAR_CAP 0x250
31 #define RESIZABLE_BAR_CTL0 0x254
32 #define RESIZABLE_BAR_CTL1 0x258
35 #define PCIE_ATU_VIEWPORT 0x900
36 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
37 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
38 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
39 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
40 #define PCIE_ATU_CR1 0x904
41 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
42 #define PCIE_ATU_TYPE_IO (0x2 << 0)
43 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
44 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
45 #define PCIE_ATU_CR2 0x908
46 #define PCIE_ATU_ENABLE (0x1 << 31)
47 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
48 #define PCIE_ATU_LOWER_BASE 0x90C
49 #define PCIE_ATU_UPPER_BASE 0x910
50 #define PCIE_ATU_LIMIT 0x914
51 #define PCIE_ATU_LOWER_TARGET 0x918
52 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
53 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
54 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
55 #define PCIE_ATU_UPPER_TARGET 0x91C
57 #define PCIE_LINK_CAPABILITY 0x7C
58 #define PCIE_LINK_CTL_2 0xA0
59 #define TARGET_LINK_SPEED_MASK 0xF
60 #define LINK_SPEED_GEN_1 0x1
61 #define LINK_SPEED_GEN_2 0x2
62 #define LINK_SPEED_GEN_3 0x3
64 #define PCIE_GEN3_RELATED 0x890
65 #define GEN3_EQU_DISABLE (1 << 16)
66 #define GEN3_ZRXDC_NON_COMP (1 << 0)
68 #define PCIE_GEN3_EQU_CTRL 0x8A8
69 #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
71 #define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
73 #define PCIE_LINK_UP_TIMEOUT_MS 100
75 #define PCIE_GLOBAL_CONTROL 0x8000
76 #define PCIE_APP_LTSSM_EN (1 << 2)
77 #define PCIE_DEVICE_TYPE_OFFSET (4)
78 #define PCIE_DEVICE_TYPE_MASK (0xF)
79 #define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
80 #define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
81 #define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
83 #define PCIE_GLOBAL_STATUS 0x8008
84 #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
85 #define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
87 #define PCIE_ARCACHE_TRC 0x8050
88 #define PCIE_AWCACHE_TRC 0x8054
89 #define ARCACHE_SHAREABLE_CACHEABLE 0x3511
90 #define AWCACHE_SHAREABLE_CACHEABLE 0x5311
92 #define LINK_SPEED_GEN_1 0x1
93 #define LINK_SPEED_GEN_2 0x2
94 #define LINK_SPEED_GEN_3 0x3
97 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
99 * @ctrl_base: The base address of the register space
100 * @cfg_base: The base address of the configuration space
101 * @cfg_size: The size of the configuration space which is needed
102 * as it gets written into the PCIE_ATU_LIMIT register
103 * @first_busno: This driver supports multiple PCIe controllers.
104 * first_busno stores the bus number of the PCIe root-port
105 * number which may vary depending on the PCIe setup
106 * (PEX switches etc).
108 struct pcie_dw_mvebu {
115 static int pcie_dw_get_link_speed(const void *regs_base)
117 return (readl(regs_base + PCIE_LINK_STATUS_REG) &
118 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
121 static int pcie_dw_get_link_width(const void *regs_base)
123 return (readl(regs_base + PCIE_LINK_STATUS_REG) &
124 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
128 * set_cfg_address() - Configure the PCIe controller config space access
130 * @pcie: Pointer to the PCI controller state
131 * @d: PCI device to access
132 * @where: Offset in the configuration space
134 * Configures the PCIe controller to access the configuration space of
135 * a specific PCIe device and returns the address to use for this
138 * Return: Address that can be used to access the configation space
139 * of the requested device / offset
141 static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
142 pci_dev_t d, uint where)
144 uintptr_t va_address;
147 * Region #0 is used for Outbound CFG space access.
148 * Direction = Outbound
151 writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT);
153 if (PCI_BUS(d) == (pcie->first_busno + 1))
154 /* For local bus, change TLP Type field to 4. */
155 writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1);
157 /* Otherwise, change TLP Type field to 5. */
158 writel(PCIE_ATU_TYPE_CFG1, pcie->ctrl_base + PCIE_ATU_CR1);
160 if (PCI_BUS(d) == pcie->first_busno) {
161 /* Accessing root port configuration space. */
162 va_address = (uintptr_t)pcie->ctrl_base;
164 writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
165 va_address = (uintptr_t)pcie->cfg_base;
168 va_address += where & ~0x3;
174 * pcie_dw_addr_valid() - Check for valid bus address
176 * @d: The PCI device to access
177 * @first_busno: Bus number of the PCIe controller root complex
179 * Return 1 (true) if the PCI device can be accessed by this controller.
181 * Return: 1 on valid, 0 on invalid
183 static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
185 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
187 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
194 * pcie_dw_mvebu_read_config() - Read from configuration space
196 * @bus: Pointer to the PCI bus
197 * @bdf: Identifies the PCIe device to access
198 * @offset: The offset into the device's configuration space
199 * @valuep: A pointer at which to store the read value
200 * @size: Indicates the size of access to perform
202 * Read a value of size @size from offset @offset within the configuration
203 * space of the device identified by the bus, device & function numbers in @bdf
204 * on the PCI bus @bus.
206 * Return: 0 on success
208 static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf,
209 uint offset, ulong *valuep,
210 enum pci_size_t size)
212 struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
213 uintptr_t va_address;
216 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
217 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
219 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
220 debug("- out of range\n");
221 *valuep = pci_get_ff(size);
225 va_address = set_cfg_address(pcie, bdf, offset);
227 value = readl(va_address);
229 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
230 *valuep = pci_conv_32_to_size(value, offset, size);
236 * pcie_dw_mvebu_write_config() - Write to configuration space
238 * @bus: Pointer to the PCI bus
239 * @bdf: Identifies the PCIe device to access
240 * @offset: The offset into the device's configuration space
241 * @value: The value to write
242 * @size: Indicates the size of access to perform
244 * Write the value @value of size @size from offset @offset within the
245 * configuration space of the device identified by the bus, device & function
246 * numbers in @bdf on the PCI bus @bus.
248 * Return: 0 on success
250 static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
251 uint offset, ulong value,
252 enum pci_size_t size)
254 struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
255 uintptr_t va_address;
258 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
259 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
260 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
262 if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
263 debug("- out of range\n");
267 va_address = set_cfg_address(pcie, bdf, offset);
269 old = readl(va_address);
270 value = pci_conv_size_to_32(old, value, offset, size);
271 writel(value, va_address);
277 * pcie_dw_configure() - Configure link capabilities and speed
279 * @regs_base: A pointer to the PCIe controller registers
280 * @cap_speed: The capabilities and speed to configure
282 * Configure the link capabilities and speed in the PCIe root complex.
284 static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
287 * TODO (shadi@marvell.com, sr@denx.de):
288 * Need to read the serdes speed from the dts and according to it
289 * configure the PCIe gen
292 /* Set link to GEN 3 */
293 clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
294 TARGET_LINK_SPEED_MASK, cap_speed);
295 clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
296 TARGET_LINK_SPEED_MASK, cap_speed);
297 setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
301 * is_link_up() - Return the link state
303 * @regs_base: A pointer to the PCIe controller registers
305 * Return: 1 (true) for active line and 0 (false) for no link
307 static int is_link_up(const void *regs_base)
309 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
312 reg = readl(regs_base + PCIE_GLOBAL_STATUS);
313 if ((reg & mask) == mask)
320 * wait_link_up() - Wait for the link to come up
322 * @regs_base: A pointer to the PCIe controller registers
324 * Return: 1 (true) for active line and 0 (false) for no link (timeout)
326 static int wait_link_up(const void *regs_base)
328 unsigned long timeout;
330 timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
331 while (!is_link_up(regs_base)) {
332 if (get_timer(0) > timeout)
340 * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
342 * @regs_base: A pointer to the PCIe controller registers
343 * @cap_speed: The capabilities and speed to configure
345 * Configure the PCIe controller root complex depending on the
346 * requested link capabilities and speed.
348 * Return: 1 (true) for active line and 0 (false) for no link
350 static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
352 if (!is_link_up(regs_base)) {
353 /* Disable LTSSM state machine to enable configuration */
354 clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
358 clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
359 PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
360 PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
362 /* Set the PCIe master AXI attributes */
363 writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
364 writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
366 /* DW pre link configurations */
367 pcie_dw_configure(regs_base, cap_speed);
369 if (!is_link_up(regs_base)) {
370 /* Configuration done. Start LTSSM */
371 setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
375 /* Check that link was established */
376 if (!wait_link_up(regs_base))
380 * Link can be established in Gen 1. still need to wait
381 * till MAC nagaotiation is completed
389 * pcie_dw_regions_setup() - iATU region setup
391 * @pcie: Pointer to the PCI controller state
393 * Configure the iATU regions in the PCIe controller for outbound access.
395 static void pcie_dw_regions_setup(struct pcie_dw_mvebu *pcie)
398 * Region #0 is used for Outbound CFG space access.
399 * Direction = Outbound
402 writel(0, pcie->ctrl_base + PCIE_ATU_VIEWPORT);
404 writel((u32)(uintptr_t)pcie->cfg_base, pcie->ctrl_base
405 + PCIE_ATU_LOWER_BASE);
406 writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
407 writel((u32)(uintptr_t)pcie->cfg_base + pcie->cfg_size,
408 pcie->ctrl_base + PCIE_ATU_LIMIT);
410 writel(0, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
411 writel(0, pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
412 writel(PCIE_ATU_TYPE_CFG0, pcie->ctrl_base + PCIE_ATU_CR1);
413 writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
417 * pcie_dw_set_host_bars() - Configure the host BARs
419 * @regs_base: A pointer to the PCIe controller registers
421 * Configure the host BARs of the PCIe controller root port so that
422 * PCI(e) devices may access the system memory.
424 static void pcie_dw_set_host_bars(const void *regs_base)
426 u32 size = gd->ram_size;
431 /* Verify the maximal BAR size */
432 reg = readl(regs_base + RESIZABLE_BAR_CAP);
433 max_size = 1ULL << (5 + (reg + (1 << 4)));
435 if (size > max_size) {
437 printf("Warning: PCIe BARs can't map all DRAM space\n");
440 /* Set the BAR base and size towards DDR */
441 bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
442 bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
443 writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
445 reg = ((size >> 20) - 1) << 12;
446 writel(size, regs_base + RESIZABLE_BAR_CTL0);
450 * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
452 * @dev: A pointer to the device being operated on
454 * Probe for an active link on the PCIe bus and configure the controller
455 * to enable this port.
457 * Return: 0 on success, else -ENODEV
459 static int pcie_dw_mvebu_probe(struct udevice *dev)
461 struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
462 struct udevice *ctlr = pci_get_controller(dev);
463 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
465 pcie->first_busno = dev->seq;
467 /* Don't register host if link is down */
468 if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
469 printf("PCIE-%d: Link down\n", dev->seq);
473 printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
474 pcie_dw_get_link_speed(pcie->ctrl_base),
475 pcie_dw_get_link_width(pcie->ctrl_base), hose->first_busno);
477 pcie_dw_regions_setup(pcie);
479 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
480 clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
481 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
483 pcie_dw_set_host_bars(pcie->ctrl_base);
489 * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state
491 * @dev: A pointer to the device being operated on
493 * Translate relevant data from the device tree pertaining to device @dev into
494 * state that the driver will later make use of. This state is stored in the
495 * device's private data structure.
497 * Return: 0 on success, else -EINVAL
499 static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev)
501 struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
503 /* Get the controller base address */
504 pcie->ctrl_base = (void *)dev_get_addr_index(dev, 0);
505 if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
508 /* Get the config space base address and size */
509 pcie->cfg_base = (void *)dev_get_addr_size_index(dev, 1,
511 if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
517 static const struct dm_pci_ops pcie_dw_mvebu_ops = {
518 .read_config = pcie_dw_mvebu_read_config,
519 .write_config = pcie_dw_mvebu_write_config,
522 static const struct udevice_id pcie_dw_mvebu_ids[] = {
523 { .compatible = "marvell,armada8k-pcie" },
527 U_BOOT_DRIVER(pcie_dw_mvebu) = {
528 .name = "pcie_dw_mvebu",
530 .of_match = pcie_dw_mvebu_ids,
531 .ops = &pcie_dw_mvebu_ops,
532 .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata,
533 .probe = pcie_dw_mvebu_probe,
534 .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu),