2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Layerscape PCIe driver
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch-fsl-lsch3/fdt.h>
16 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
17 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
20 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
21 #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
24 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
25 #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
29 #define PCIE_ATU_VIEWPORT 0x900
30 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
31 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
32 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
33 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
34 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
35 #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
36 #define PCIE_ATU_CR1 0x904
37 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
38 #define PCIE_ATU_TYPE_IO (0x2 << 0)
39 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
40 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
41 #define PCIE_ATU_CR2 0x908
42 #define PCIE_ATU_ENABLE (0x1 << 31)
43 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
44 #define PCIE_ATU_LOWER_BASE 0x90C
45 #define PCIE_ATU_UPPER_BASE 0x910
46 #define PCIE_ATU_LIMIT 0x914
47 #define PCIE_ATU_LOWER_TARGET 0x918
48 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
49 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
50 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
51 #define PCIE_ATU_UPPER_TARGET 0x91C
54 #define PCIE_LUT_BASE 0x80000
55 #define PCIE_LUT_DBG 0x7FC
57 #define PCIE_DBI_RO_WR_EN 0x8bc
59 #define PCIE_LINK_CAP 0x7c
60 #define PCIE_LINK_SPEED_MASK 0xf
61 #define PCIE_LINK_STA 0x82
63 #define LTSSM_STATE_MASK 0x3f
64 #define LTSSM_PCIE_L0 0x11 /* L0 state */
66 #define PCIE_DBI_SIZE 0x100000 /* 1M */
71 void __iomem *va_cfg0;
72 void __iomem *va_cfg1;
73 struct pci_controller hose;
91 #define SET_LS_PCIE_INFO(x, num) \
93 x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
94 x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
95 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
96 x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
97 x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
98 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
99 x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
100 x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
101 x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
102 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
103 x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
104 x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
105 x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
106 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
107 x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
111 #ifdef CONFIG_LS102XA
112 #include <asm/arch/immap_ls102xa.h>
114 /* PEX1/2 Misc Ports Status Register */
115 #define LTSSM_STATE_SHIFT 20
117 static int ls_pcie_link_state(struct ls_pcie *pcie)
120 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
122 state = in_be32(&scfg->pexmscportsr[pcie->idx]);
123 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
124 if (state < LTSSM_PCIE_L0) {
125 debug("....PCIe link error. LTSSM=0x%02x.\n", state);
132 static int ls_pcie_link_state(struct ls_pcie *pcie)
136 state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
138 if (state < LTSSM_PCIE_L0) {
139 debug("....PCIe link error. LTSSM=0x%02x.\n", state);
147 static int ls_pcie_link_up(struct ls_pcie *pcie)
152 state = ls_pcie_link_state(pcie);
156 /* Try to download speed to gen1 */
157 cap = readl(pcie->dbi + PCIE_LINK_CAP);
158 writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
160 * Notice: the following delay has critical impact on link training
161 * if too short (<30ms) the link doesn't get up.
164 state = ls_pcie_link_state(pcie);
168 writel(cap, pcie->dbi + PCIE_LINK_CAP);
173 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
175 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
176 pcie->dbi + PCIE_ATU_VIEWPORT);
177 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
180 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
182 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
183 pcie->dbi + PCIE_ATU_VIEWPORT);
184 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
187 static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
188 u64 phys, u64 bus_addr, pci_size_t size)
190 writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
191 writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
192 writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
193 writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
194 writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
195 writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
196 writel(type, pcie->dbi + PCIE_ATU_CR1);
197 writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
200 static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
206 /* ATU 0 : OUTBOUND : CFG0 */
207 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
212 /* ATU 1 : OUTBOUND : CFG1 */
213 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
218 /* ATU 2 : OUTBOUND : MEM */
219 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
224 /* ATU 3 : OUTBOUND : IO */
225 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
232 for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
233 writel(PCIE_ATU_REGION_OUTBOUND | i,
234 pcie->dbi + PCIE_ATU_VIEWPORT);
235 debug("iATU%d:\n", i);
236 debug("\tLOWER PHYS 0x%08x\n",
237 readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
238 debug("\tUPPER PHYS 0x%08x\n",
239 readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
240 debug("\tLOWER BUS 0x%08x\n",
241 readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
242 debug("\tUPPER BUS 0x%08x\n",
243 readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
244 debug("\tLIMIT 0x%08x\n",
245 readl(pcie->dbi + PCIE_ATU_LIMIT));
246 debug("\tCR1 0x%08x\n",
247 readl(pcie->dbi + PCIE_ATU_CR1));
248 debug("\tCR2 0x%08x\n",
249 readl(pcie->dbi + PCIE_ATU_CR2));
254 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
256 /* Do not skip controller */
260 static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
265 /* Controller does not support multi-function in RC mode */
266 if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
272 static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
275 struct ls_pcie *pcie = hose->priv_data;
278 if (ls_pcie_addr_valid(hose, d)) {
283 if (PCI_BUS(d) == hose->first_busno) {
284 addr = pcie->dbi + (where & ~0x3);
286 busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
287 PCIE_ATU_DEV(PCI_DEV(d)) |
288 PCIE_ATU_FUNC(PCI_FUNC(d));
290 if (PCI_BUS(d) == hose->first_busno + 1) {
291 ls_pcie_cfg0_set_busdev(pcie, busdev);
292 addr = pcie->va_cfg0 + (where & ~0x3);
294 ls_pcie_cfg1_set_busdev(pcie, busdev);
295 addr = pcie->va_cfg1 + (where & ~0x3);
304 static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
307 struct ls_pcie *pcie = hose->priv_data;
310 if (ls_pcie_addr_valid(hose, d))
313 if (PCI_BUS(d) == hose->first_busno) {
314 addr = pcie->dbi + (where & ~0x3);
316 busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
317 PCIE_ATU_DEV(PCI_DEV(d)) |
318 PCIE_ATU_FUNC(PCI_FUNC(d));
320 if (PCI_BUS(d) == hose->first_busno + 1) {
321 ls_pcie_cfg0_set_busdev(pcie, busdev);
322 addr = pcie->va_cfg0 + (where & ~0x3);
324 ls_pcie_cfg1_set_busdev(pcie, busdev);
325 addr = pcie->va_cfg1 + (where & ~0x3);
334 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
335 struct ls_pcie_info *info)
337 struct pci_controller *hose = &pcie->hose;
338 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
340 ls_pcie_setup_atu(pcie, info);
342 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
344 /* program correct class for RC */
345 writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
346 pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
347 PCI_CLASS_BRIDGE_PCI);
348 #ifndef CONFIG_LS102XA
349 writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
353 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
355 struct ls_pcie *pcie;
356 struct pci_controller *hose;
357 int num = dev - PCIE1;
358 pci_dev_t pdev = PCI_BDF(busno, 0, 0);
359 int i, linkup, ep_mode;
363 if (!is_serdes_configured(dev)) {
364 printf("PCIe%d: disabled\n", num + 1);
368 pcie = malloc(sizeof(*pcie));
371 memset(pcie, 0, sizeof(*pcie));
374 hose->priv_data = pcie;
375 hose->first_busno = busno;
377 pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
378 pcie->va_cfg0 = map_physmem(info->cfg0_phys,
381 pcie->va_cfg1 = map_physmem(info->cfg1_phys,
385 /* outbound memory */
386 pci_set_region(&hose->regions[0],
387 (pci_size_t)info->mem_bus,
388 (phys_size_t)info->mem_phys,
389 (pci_size_t)info->mem_size,
393 pci_set_region(&hose->regions[1],
394 (pci_size_t)info->io_bus,
395 (phys_size_t)info->io_phys,
396 (pci_size_t)info->io_size,
399 /* System memory space */
400 pci_set_region(&hose->regions[2],
401 CONFIG_SYS_PCI_MEMORY_BUS,
402 CONFIG_SYS_PCI_MEMORY_PHYS,
403 CONFIG_SYS_PCI_MEMORY_SIZE,
404 PCI_REGION_SYS_MEMORY);
406 hose->region_count = 3;
408 for (i = 0; i < hose->region_count; i++)
409 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
411 (u64)hose->regions[i].phys_start,
412 (u64)hose->regions[i].bus_start,
413 (u64)hose->regions[i].size,
414 hose->regions[i].flags);
417 pci_hose_read_config_byte_via_dword,
418 pci_hose_read_config_word_via_dword,
420 pci_hose_write_config_byte_via_dword,
421 pci_hose_write_config_word_via_dword,
422 ls_pcie_write_config);
424 pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
425 ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
426 printf("PCIe%u: %s ", info->pci_num,
427 ep_mode ? "Endpoint" : "Root Complex");
429 linkup = ls_pcie_link_up(pcie);
432 /* Let the user know there's no PCIe link */
433 printf("no link, regs @ 0x%lx\n", info->regs);
434 hose->last_busno = hose->first_busno;
438 /* Print the negotiated PCIe link width */
439 pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
440 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
441 (temp16 & 0xf), info->regs);
446 ls_pcie_setup_ctrl(pcie, info);
448 pci_register_hose(hose);
450 hose->last_busno = pci_hose_scan(hose);
452 printf("PCIe%x: Bus %02x - %02x\n",
453 info->pci_num, hose->first_busno, hose->last_busno);
455 return hose->last_busno + 1;
458 int ls_pcie_init_board(int busno)
460 struct ls_pcie_info info;
463 SET_LS_PCIE_INFO(info, 1);
464 busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
468 SET_LS_PCIE_INFO(info, 2);
469 busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
473 SET_LS_PCIE_INFO(info, 3);
474 busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
478 SET_LS_PCIE_INFO(info, 4);
479 busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
485 void pci_init_board(void)
487 ls_pcie_init_board(0);
490 #ifdef CONFIG_OF_BOARD_SETUP
492 #include <fdt_support.h>
494 static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
495 unsigned long ctrl_addr, enum srds_prtcl dev)
499 off = fdt_node_offset_by_compat_reg(blob, pci_compat,
500 (phys_addr_t)ctrl_addr);
504 if (!is_serdes_configured(dev))
505 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
508 void ft_pci_setup(void *blob, bd_t *bd)
511 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
515 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
519 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
523 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
528 void ft_pci_setup(void *blob, bd_t *bd)
533 #ifdef CONFIG_LS2085A
535 void pcie_set_available_streamids(void *blob, const char *pcie_path,
536 u32 *stream_ids, int count)
541 nodeoffset = fdt_path_offset(blob, pcie_path);
542 if (nodeoffset < 0) {
543 printf("\n%s: ERROR: unable to update PCIe node\n", __func__);
547 /* for each stream ID, append to mmu-masters */
548 for (i = 0; i < count; i++) {
549 fdt_appendprop_u32(blob, nodeoffset, "available-stream-ids",
554 #define MAX_STREAM_IDS 4
555 void fdt_fixup_smmu_pcie(void *blob)
558 u32 stream_ids[MAX_STREAM_IDS];
561 /* PEX1 stream ID fixup */
562 count = FSL_PEX1_STREAM_ID_END - FSL_PEX1_STREAM_ID_START + 1;
563 alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids,
565 pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count);
569 /* PEX2 stream ID fixup */
570 count = FSL_PEX2_STREAM_ID_END - FSL_PEX2_STREAM_ID_START + 1;
571 alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids,
573 pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count);
577 /* PEX3 stream ID fixup */
578 count = FSL_PEX3_STREAM_ID_END - FSL_PEX3_STREAM_ID_START + 1;
579 alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids,
581 pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count);
585 /* PEX4 stream ID fixup */
586 count = FSL_PEX4_STREAM_ID_END - FSL_PEX4_STREAM_ID_START + 1;
587 alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids,
589 pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count);