2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Layerscape PCIe driver
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/fsl_serdes.h>
15 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
16 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
19 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
20 #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
23 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
24 #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
28 #define PCIE_ATU_VIEWPORT 0x900
29 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
30 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
31 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
32 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
33 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
34 #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
35 #define PCIE_ATU_CR1 0x904
36 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
37 #define PCIE_ATU_TYPE_IO (0x2 << 0)
38 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
39 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
40 #define PCIE_ATU_CR2 0x908
41 #define PCIE_ATU_ENABLE (0x1 << 31)
42 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
43 #define PCIE_ATU_LOWER_BASE 0x90C
44 #define PCIE_ATU_UPPER_BASE 0x910
45 #define PCIE_ATU_LIMIT 0x914
46 #define PCIE_ATU_LOWER_TARGET 0x918
47 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
48 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
49 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
50 #define PCIE_ATU_UPPER_TARGET 0x91C
52 #define PCIE_LINK_CAP 0x7c
53 #define PCIE_LINK_SPEED_MASK 0xf
54 #define PCIE_LINK_STA 0x82
56 #define PCIE_DBI_SIZE (4 * 1024) /* 4K */
61 void __iomem *va_cfg0;
62 void __iomem *va_cfg1;
63 struct pci_controller hose;
81 #define SET_LS_PCIE_INFO(x, num) \
83 x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
84 x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
85 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
86 x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
87 x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
88 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
89 x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
90 x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
91 x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
92 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
93 x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
94 x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
95 x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
96 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
97 x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
101 #ifdef CONFIG_LS102XA
102 #include <asm/arch/immap_ls102xa.h>
104 /* PEX1/2 Misc Ports Status Register */
105 #define LTSSM_STATE_SHIFT 20
106 #define LTSSM_STATE_MASK 0x3f
107 #define LTSSM_PCIE_L0 0x11 /* L0 state */
109 static int ls_pcie_link_state(struct ls_pcie *pcie)
112 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
114 state = in_be32(&scfg->pexmscportsr[pcie->idx]);
115 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
116 if (state < LTSSM_PCIE_L0) {
117 debug("....PCIe link error. LTSSM=0x%02x.\n", state);
124 #define PCIE_LDBG 0x7FC
126 static int ls_pcie_link_state(struct ls_pcie *pcie)
130 state = readl(pcie->dbi + PCIE_LDBG);
134 debug("....PCIe link error.\n");
139 static int ls_pcie_link_up(struct ls_pcie *pcie)
144 state = ls_pcie_link_state(pcie);
148 /* Try to download speed to gen1 */
149 cap = readl(pcie->dbi + PCIE_LINK_CAP);
150 writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
152 state = ls_pcie_link_state(pcie);
156 writel(cap, pcie->dbi + PCIE_LINK_CAP);
161 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
163 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
164 pcie->dbi + PCIE_ATU_VIEWPORT);
165 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
168 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
170 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
171 pcie->dbi + PCIE_ATU_VIEWPORT);
172 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
175 static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
176 u64 phys, u64 bus_addr, pci_size_t size)
178 writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
179 writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
180 writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
181 writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
182 writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
183 writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
184 writel(type, pcie->dbi + PCIE_ATU_CR1);
185 writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
188 static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
194 /* ATU 0 : OUTBOUND : CFG0 */
195 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
200 /* ATU 1 : OUTBOUND : CFG1 */
201 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
206 /* ATU 2 : OUTBOUND : MEM */
207 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
212 /* ATU 3 : OUTBOUND : IO */
213 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
220 for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
221 writel(PCIE_ATU_REGION_OUTBOUND | i,
222 pcie->dbi + PCIE_ATU_VIEWPORT);
223 debug("iATU%d:\n", i);
224 debug("\tLOWER PHYS 0x%08x\n",
225 readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
226 debug("\tUPPER PHYS 0x%08x\n",
227 readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
228 debug("\tLOWER BUS 0x%08x\n",
229 readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
230 debug("\tUPPER BUS 0x%08x\n",
231 readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
232 debug("\tLIMIT 0x%08x\n",
233 readl(pcie->dbi + PCIE_ATU_LIMIT));
234 debug("\tCR1 0x%08x\n",
235 readl(pcie->dbi + PCIE_ATU_CR1));
236 debug("\tCR2 0x%08x\n",
237 readl(pcie->dbi + PCIE_ATU_CR2));
242 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
244 /* Do not skip controller */
248 static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
256 static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
259 struct ls_pcie *pcie = hose->priv_data;
262 if (ls_pcie_addr_valid(hose, d)) {
267 if (PCI_BUS(d) == hose->first_busno) {
268 addr = pcie->dbi + (where & ~0x3);
270 busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
271 PCIE_ATU_DEV(PCI_DEV(d)) |
272 PCIE_ATU_FUNC(PCI_FUNC(d));
274 if (PCI_BUS(d) == hose->first_busno + 1) {
275 ls_pcie_cfg0_set_busdev(pcie, busdev);
276 addr = pcie->va_cfg0 + (where & ~0x3);
278 ls_pcie_cfg1_set_busdev(pcie, busdev);
279 addr = pcie->va_cfg1 + (where & ~0x3);
288 static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
291 struct ls_pcie *pcie = hose->priv_data;
294 if (ls_pcie_addr_valid(hose, d))
297 if (PCI_BUS(d) == hose->first_busno) {
298 addr = pcie->dbi + (where & ~0x3);
300 busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
301 PCIE_ATU_DEV(PCI_DEV(d)) |
302 PCIE_ATU_FUNC(PCI_FUNC(d));
304 if (PCI_BUS(d) == hose->first_busno + 1) {
305 ls_pcie_cfg0_set_busdev(pcie, busdev);
306 addr = pcie->va_cfg0 + (where & ~0x3);
308 ls_pcie_cfg1_set_busdev(pcie, busdev);
309 addr = pcie->va_cfg1 + (where & ~0x3);
318 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
319 struct ls_pcie_info *info)
321 struct pci_controller *hose = &pcie->hose;
322 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
324 ls_pcie_setup_atu(pcie, info);
326 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
328 /* program correct class for RC */
329 pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
330 PCI_CLASS_BRIDGE_PCI);
333 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
335 struct ls_pcie *pcie;
336 struct pci_controller *hose;
337 int num = dev - PCIE1;
338 pci_dev_t pdev = PCI_BDF(busno, 0, 0);
339 int i, linkup, ep_mode;
343 if (!is_serdes_configured(dev)) {
344 printf("PCIe%d: disabled\n", num + 1);
348 pcie = malloc(sizeof(*pcie));
351 memset(pcie, 0, sizeof(*pcie));
354 hose->priv_data = pcie;
355 hose->first_busno = busno;
357 pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
358 pcie->va_cfg0 = map_physmem(info->cfg0_phys,
361 pcie->va_cfg1 = map_physmem(info->cfg1_phys,
365 /* outbound memory */
366 pci_set_region(&hose->regions[0],
367 (pci_size_t)info->mem_bus,
368 (phys_size_t)info->mem_phys,
369 (pci_size_t)info->mem_size,
373 pci_set_region(&hose->regions[1],
374 (pci_size_t)info->io_bus,
375 (phys_size_t)info->io_phys,
376 (pci_size_t)info->io_size,
379 /* System memory space */
380 pci_set_region(&hose->regions[2],
381 CONFIG_SYS_PCI_MEMORY_BUS,
382 CONFIG_SYS_PCI_MEMORY_PHYS,
383 CONFIG_SYS_PCI_MEMORY_SIZE,
384 PCI_REGION_SYS_MEMORY);
386 hose->region_count = 3;
388 for (i = 0; i < hose->region_count; i++)
389 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
391 (u64)hose->regions[i].phys_start,
392 (u64)hose->regions[i].bus_start,
393 (u64)hose->regions[i].size,
394 hose->regions[i].flags);
397 pci_hose_read_config_byte_via_dword,
398 pci_hose_read_config_word_via_dword,
400 pci_hose_write_config_byte_via_dword,
401 pci_hose_write_config_word_via_dword,
402 ls_pcie_write_config);
404 pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
405 ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
406 printf("PCIe%u: %s ", info->pci_num,
407 ep_mode ? "Endpoint" : "Root Complex");
409 linkup = ls_pcie_link_up(pcie);
412 /* Let the user know there's no PCIe link */
413 printf("no link, regs @ 0x%lx\n", info->regs);
414 hose->last_busno = hose->first_busno;
418 /* Print the negotiated PCIe link width */
419 pci_hose_read_config_word(hose, dev, PCIE_LINK_STA, &temp16);
420 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
421 (temp16 & 0xf), info->regs);
426 ls_pcie_setup_ctrl(pcie, info);
428 pci_register_hose(hose);
430 hose->last_busno = pci_hose_scan(hose);
432 printf("PCIe%x: Bus %02x - %02x\n",
433 info->pci_num, hose->first_busno, hose->last_busno);
435 return hose->last_busno + 1;
438 int ls_pcie_init_board(int busno)
440 struct ls_pcie_info info;
443 SET_LS_PCIE_INFO(info, 1);
444 busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
448 SET_LS_PCIE_INFO(info, 2);
449 busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
453 SET_LS_PCIE_INFO(info, 3);
454 busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
458 SET_LS_PCIE_INFO(info, 4);
459 busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
465 void pci_init_board(void)
467 ls_pcie_init_board(0);
470 #ifdef CONFIG_OF_BOARD_SETUP
472 #include <fdt_support.h>
474 static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
475 unsigned long ctrl_addr, enum srds_prtcl dev)
479 off = fdt_node_offset_by_compat_reg(blob, pci_compat,
480 (phys_addr_t)ctrl_addr);
484 if (!is_serdes_configured(dev))
485 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
488 void ft_pci_setup(void *blob, bd_t *bd)
491 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
495 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
499 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
503 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
508 void ft_pci_setup(void *blob, bd_t *bd)