3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * Layerscape PCIe driver
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/fsl_serdes.h>
14 #ifdef CONFIG_OF_BOARD_SETUP
16 #include <fdt_support.h>
18 #include <asm/arch/clock.h>
20 #include "pcie_layerscape.h"
22 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
24 * Return next available LUT index.
26 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
28 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
29 return pcie->next_lut_index++;
31 return -ENOSPC; /* LUT is full */
34 /* returns the next available streamid for pcie, -errno if failed */
35 static int ls_pcie_next_streamid(void)
37 static int next_stream_id = FSL_PEX_STREAM_ID_START;
39 if (next_stream_id > FSL_PEX_STREAM_ID_END)
42 return next_stream_id++;
45 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
49 out_be32(pcie->lut + offset, value);
51 out_le32(pcie->lut + offset, value);
55 * Program a single LUT entry
57 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
60 /* leave mask as all zeroes, want to match all bits */
61 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
62 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
66 * An msi-map is a property to be added to the pci controller
67 * node. It is a table, where each entry consists of 4 fields
70 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
71 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
73 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
74 u32 devid, u32 streamid)
82 /* find pci controller node */
83 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
86 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
87 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
88 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
89 svr == SVR_LS2048A || svr == SVR_LS2044A ||
90 svr == SVR_LS2081A || svr == SVR_LS2041A)
91 compat = "fsl,ls2088a-pcie";
93 compat = CONFIG_FSL_PCIE_COMPAT;
95 nodeoffset = fdt_node_offset_by_compat_reg(blob,
96 compat, pcie->dbi_res.start);
102 /* get phandle to MSI controller */
103 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
105 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
106 __func__, pcie->idx);
109 phandle = fdt32_to_cpu(*prop);
111 /* set one msi-map row */
112 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
113 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
114 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
115 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
119 * An iommu-map is a property to be added to the pci controller
120 * node. It is a table, where each entry consists of 4 fields
123 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
124 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
126 static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
127 u32 devid, u32 streamid)
136 /* find pci controller node */
137 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
138 pcie->dbi_res.start);
139 if (nodeoffset < 0) {
140 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
141 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
142 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
143 svr == SVR_LS2048A || svr == SVR_LS2044A ||
144 svr == SVR_LS2081A || svr == SVR_LS2041A)
145 compat = "fsl,ls2088a-pcie";
147 compat = CONFIG_FSL_PCIE_COMPAT;
150 nodeoffset = fdt_node_offset_by_compat_reg(blob,
151 compat, pcie->dbi_res.start);
157 /* get phandle to iommu controller */
158 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
160 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
161 __func__, pcie->idx);
165 /* set iommu-map row */
166 iommu_map[0] = cpu_to_fdt32(devid);
167 iommu_map[1] = *++prop;
168 iommu_map[2] = cpu_to_fdt32(streamid);
169 iommu_map[3] = cpu_to_fdt32(1);
172 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
175 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
179 static void fdt_fixup_pcie(void *blob)
181 struct udevice *dev, *bus;
182 struct ls_pcie *pcie;
187 /* Scan all known buses */
188 for (pci_find_first_device(&dev);
190 pci_find_next_device(&dev)) {
191 for (bus = dev; device_is_on_pci_bus(bus);)
193 pcie = dev_get_priv(bus);
195 streamid = ls_pcie_next_streamid();
197 debug("ERROR: no stream ids free\n");
201 index = ls_pcie_next_lut_index(pcie);
203 debug("ERROR: no LUT indexes free\n");
207 /* the DT fixup must be relative to the hose first_busno */
208 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
209 /* map PCI b.d.f to streamID in LUT */
210 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
212 /* update msi-map in device tree */
213 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
215 /* update iommu-map in device tree */
216 fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
222 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
228 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
229 pcie->dbi_res.start);
231 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
232 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
233 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
234 svr == SVR_LS2048A || svr == SVR_LS2044A ||
235 svr == SVR_LS2081A || svr == SVR_LS2041A)
236 compat = "fsl,ls2088a-pcie";
238 compat = CONFIG_FSL_PCIE_COMPAT;
240 off = fdt_node_offset_by_compat_reg(blob,
241 compat, pcie->dbi_res.start);
248 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
250 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
253 /* Fixup Kernel DT for PCIe */
254 void ft_pci_setup(void *blob, bd_t *bd)
256 struct ls_pcie *pcie;
258 list_for_each_entry(pcie, &ls_pcie_list, list)
259 ft_pcie_ls_setup(blob, pcie);
261 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
262 fdt_fixup_pcie(blob);
266 #else /* !CONFIG_OF_BOARD_SETUP */
267 void ft_pci_setup(void *blob, bd_t *bd)