3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * Layerscape PCIe driver
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/fsl_serdes.h>
14 #ifdef CONFIG_OF_BOARD_SETUP
16 #include <fdt_support.h>
17 #include "pcie_layerscape.h"
19 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
21 * Return next available LUT index.
23 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
25 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
26 return pcie->next_lut_index++;
28 return -ENOSPC; /* LUT is full */
31 /* returns the next available streamid for pcie, -errno if failed */
32 static int ls_pcie_next_streamid(void)
34 static int next_stream_id = FSL_PEX_STREAM_ID_START;
36 if (next_stream_id > FSL_PEX_STREAM_ID_END)
39 return next_stream_id++;
42 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
46 out_be32(pcie->lut + offset, value);
48 out_le32(pcie->lut + offset, value);
52 * Program a single LUT entry
54 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
57 /* leave mask as all zeroes, want to match all bits */
58 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
59 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
63 * An msi-map is a property to be added to the pci controller
64 * node. It is a table, where each entry consists of 4 fields
67 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
68 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
70 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
71 u32 devid, u32 streamid)
79 /* find pci controller node */
80 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
83 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
84 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
85 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
86 svr == SVR_LS2048A || svr == SVR_LS2044A ||
87 svr == SVR_LS2081A || svr == SVR_LS2041A)
88 compat = "fsl,ls2088a-pcie";
90 compat = CONFIG_FSL_PCIE_COMPAT;
92 nodeoffset = fdt_node_offset_by_compat_reg(blob,
93 compat, pcie->dbi_res.start);
99 /* get phandle to MSI controller */
100 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
102 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
103 __func__, pcie->idx);
106 phandle = fdt32_to_cpu(*prop);
108 /* set one msi-map row */
109 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
110 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
111 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
112 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
116 * An iommu-map is a property to be added to the pci controller
117 * node. It is a table, where each entry consists of 4 fields
120 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
121 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
123 static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
124 u32 devid, u32 streamid)
131 /* find pci controller node */
132 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
133 pcie->dbi_res.start);
134 if (nodeoffset < 0) {
135 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
136 nodeoffset = fdt_node_offset_by_compat_reg(blob,
137 CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
145 /* get phandle to iommu controller */
146 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
148 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
149 __func__, pcie->idx);
153 /* set iommu-map row */
154 iommu_map[0] = cpu_to_fdt32(devid);
155 iommu_map[1] = *++prop;
156 iommu_map[2] = cpu_to_fdt32(streamid);
157 iommu_map[3] = cpu_to_fdt32(1);
160 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
163 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
167 static void fdt_fixup_pcie(void *blob)
169 struct udevice *dev, *bus;
170 struct ls_pcie *pcie;
175 /* Scan all known buses */
176 for (pci_find_first_device(&dev);
178 pci_find_next_device(&dev)) {
179 for (bus = dev; device_is_on_pci_bus(bus);)
181 pcie = dev_get_priv(bus);
183 streamid = ls_pcie_next_streamid();
185 debug("ERROR: no stream ids free\n");
189 index = ls_pcie_next_lut_index(pcie);
191 debug("ERROR: no LUT indexes free\n");
195 /* the DT fixup must be relative to the hose first_busno */
196 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
197 /* map PCI b.d.f to streamID in LUT */
198 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
200 /* update msi-map in device tree */
201 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
203 /* update iommu-map in device tree */
204 fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
210 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
216 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
217 pcie->dbi_res.start);
219 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
220 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
221 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
222 svr == SVR_LS2048A || svr == SVR_LS2044A ||
223 svr == SVR_LS2081A || svr == SVR_LS2041A)
224 compat = "fsl,ls2088a-pcie";
226 compat = CONFIG_FSL_PCIE_COMPAT;
228 off = fdt_node_offset_by_compat_reg(blob,
229 compat, pcie->dbi_res.start);
236 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
238 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
241 /* Fixup Kernel DT for PCIe */
242 void ft_pci_setup(void *blob, bd_t *bd)
244 struct ls_pcie *pcie;
246 list_for_each_entry(pcie, &ls_pcie_list, list)
247 ft_pcie_ls_setup(blob, pcie);
249 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
250 fdt_fixup_pcie(blob);
254 #else /* !CONFIG_OF_BOARD_SETUP */
255 void ft_pci_setup(void *blob, bd_t *bd)