2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Layerscape PCIe driver
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
13 #ifdef CONFIG_OF_BOARD_SETUP
15 #include <fdt_support.h>
16 #include "pcie_layerscape.h"
18 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
20 * Return next available LUT index.
22 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
24 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
25 return pcie->next_lut_index++;
27 return -ENOSPC; /* LUT is full */
30 /* returns the next available streamid for pcie, -errno if failed */
31 static int ls_pcie_next_streamid(void)
33 static int next_stream_id = FSL_PEX_STREAM_ID_START;
35 if (next_stream_id > FSL_PEX_STREAM_ID_END)
38 return next_stream_id++;
41 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
45 out_be32(pcie->lut + offset, value);
47 out_le32(pcie->lut + offset, value);
51 * Program a single LUT entry
53 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
56 /* leave mask as all zeroes, want to match all bits */
57 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
58 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
62 * An msi-map is a property to be added to the pci controller
63 * node. It is a table, where each entry consists of 4 fields
66 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
67 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
69 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
70 u32 devid, u32 streamid)
78 /* find pci controller node */
79 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
82 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
83 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
84 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
85 svr == SVR_LS2048A || svr == SVR_LS2044A)
86 compat = "fsl,ls2088a-pcie";
88 compat = CONFIG_FSL_PCIE_COMPAT;
90 nodeoffset = fdt_node_offset_by_compat_reg(blob,
91 compat, pcie->dbi_res.start);
97 /* get phandle to MSI controller */
98 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
100 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
101 __func__, pcie->idx);
104 phandle = fdt32_to_cpu(*prop);
106 /* set one msi-map row */
107 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
108 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
109 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
110 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
114 * An iommu-map is a property to be added to the pci controller
115 * node. It is a table, where each entry consists of 4 fields
118 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
119 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
121 static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
122 u32 devid, u32 streamid)
129 /* find pci controller node */
130 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
131 pcie->dbi_res.start);
132 if (nodeoffset < 0) {
133 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
134 nodeoffset = fdt_node_offset_by_compat_reg(blob,
135 CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
143 /* get phandle to iommu controller */
144 prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
146 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
147 __func__, pcie->idx);
151 /* set iommu-map row */
152 iommu_map[0] = cpu_to_fdt32(devid);
153 iommu_map[1] = *++prop;
154 iommu_map[2] = cpu_to_fdt32(streamid);
155 iommu_map[3] = cpu_to_fdt32(1);
158 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
161 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
165 static void fdt_fixup_pcie(void *blob)
167 struct udevice *dev, *bus;
168 struct ls_pcie *pcie;
173 /* Scan all known buses */
174 for (pci_find_first_device(&dev);
176 pci_find_next_device(&dev)) {
177 for (bus = dev; device_is_on_pci_bus(bus);)
179 pcie = dev_get_priv(bus);
181 streamid = ls_pcie_next_streamid();
183 debug("ERROR: no stream ids free\n");
187 index = ls_pcie_next_lut_index(pcie);
189 debug("ERROR: no LUT indexes free\n");
193 /* the DT fixup must be relative to the hose first_busno */
194 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
195 /* map PCI b.d.f to streamID in LUT */
196 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
198 /* update msi-map in device tree */
199 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
201 /* update iommu-map in device tree */
202 fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
208 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
214 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
215 pcie->dbi_res.start);
217 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
218 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
219 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
220 svr == SVR_LS2048A || svr == SVR_LS2044A)
221 compat = "fsl,ls2088a-pcie";
223 compat = CONFIG_FSL_PCIE_COMPAT;
225 off = fdt_node_offset_by_compat_reg(blob,
226 compat, pcie->dbi_res.start);
233 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
235 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
238 /* Fixup Kernel DT for PCIe */
239 void ft_pci_setup(void *blob, bd_t *bd)
241 struct ls_pcie *pcie;
243 list_for_each_entry(pcie, &ls_pcie_list, list)
244 ft_pcie_ls_setup(blob, pcie);
246 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
247 fdt_fixup_pcie(blob);
251 #else /* !CONFIG_OF_BOARD_SETUP */
252 void ft_pci_setup(void *blob, bd_t *bd)