2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Layerscape PCIe driver
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
13 #ifdef CONFIG_OF_BOARD_SETUP
15 #include <fdt_support.h>
16 #include "pcie_layerscape.h"
18 #ifdef CONFIG_FSL_LSCH3
20 * Return next available LUT index.
22 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
24 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
25 return pcie->next_lut_index++;
27 return -ENOSPC; /* LUT is full */
30 /* returns the next available streamid for pcie, -errno if failed */
31 static int ls_pcie_next_streamid(void)
33 static int next_stream_id = FSL_PEX_STREAM_ID_START;
35 if (next_stream_id > FSL_PEX_STREAM_ID_END)
38 return next_stream_id++;
41 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
45 out_be32(pcie->lut + offset, value);
47 out_le32(pcie->lut + offset, value);
51 * Program a single LUT entry
53 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
56 /* leave mask as all zeroes, want to match all bits */
57 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
58 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
62 * An msi-map is a property to be added to the pci controller
63 * node. It is a table, where each entry consists of 4 fields
66 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
67 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
69 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
70 u32 devid, u32 streamid)
78 /* find pci controller node */
79 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
82 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
83 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
84 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
85 svr == SVR_LS2048A || svr == SVR_LS2044A)
86 compat = "fsl,ls2088a-pcie";
88 compat = CONFIG_FSL_PCIE_COMPAT;
90 nodeoffset = fdt_node_offset_by_compat_reg(blob,
91 compat, pcie->dbi_res.start);
97 /* get phandle to MSI controller */
98 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
100 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
101 __func__, pcie->idx);
104 phandle = fdt32_to_cpu(*prop);
106 /* set one msi-map row */
107 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
108 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
109 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
110 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
113 static void fdt_fixup_pcie(void *blob)
115 struct udevice *dev, *bus;
116 struct ls_pcie *pcie;
121 /* Scan all known buses */
122 for (pci_find_first_device(&dev);
124 pci_find_next_device(&dev)) {
125 for (bus = dev; device_is_on_pci_bus(bus);)
127 pcie = dev_get_priv(bus);
129 streamid = ls_pcie_next_streamid();
131 debug("ERROR: no stream ids free\n");
135 index = ls_pcie_next_lut_index(pcie);
137 debug("ERROR: no LUT indexes free\n");
141 /* the DT fixup must be relative to the hose first_busno */
142 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
143 /* map PCI b.d.f to streamID in LUT */
144 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
146 /* update msi-map in device tree */
147 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
153 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
159 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
160 pcie->dbi_res.start);
162 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
163 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
164 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
165 svr == SVR_LS2048A || svr == SVR_LS2044A)
166 compat = "fsl,ls2088a-pcie";
168 compat = CONFIG_FSL_PCIE_COMPAT;
170 off = fdt_node_offset_by_compat_reg(blob,
171 compat, pcie->dbi_res.start);
178 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
180 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
183 /* Fixup Kernel DT for PCIe */
184 void ft_pci_setup(void *blob, bd_t *bd)
186 struct ls_pcie *pcie;
188 list_for_each_entry(pcie, &ls_pcie_list, list)
189 ft_pcie_ls_setup(blob, pcie);
191 #ifdef CONFIG_FSL_LSCH3
192 fdt_fixup_pcie(blob);
196 #else /* !CONFIG_OF_BOARD_SETUP */
197 void ft_pci_setup(void *blob, bd_t *bd)