2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 ********************************************************************
25 * Lots of code copied from:
27 * i82365.c 1.352 - Linux driver for Intel 82365 and compatible
28 * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
29 * (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
39 #include <pcmcia/ss.h>
40 #include <pcmcia/i82365.h>
41 #include <pcmcia/yenta.h>
43 #include <pcmcia/cirrus.h>
45 #include <pcmcia/ti113x.h>
48 static struct pci_device_id supported[] = {
50 {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
52 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
57 #define CYCLE_TIME 120
60 extern int SPD67290Init (void);
64 static void i82365_dump_regions (pci_dev_t dev);
67 typedef struct socket_info_t {
70 u_char pci_lat, cb_lat, sub_bus, cache;
77 cirrus_state_t c_state;
84 /* These definitions must match the pcic table! */
85 typedef enum pcic_id {
86 IS_PD6710, IS_PD672X, IS_VT83C469
89 typedef struct pcic_t {
93 static pcic_t pcic[] = {
100 static socket_info_t socket;
101 static socket_state_t state;
102 static struct pccard_mem_map mem;
103 static struct pccard_io_map io;
105 /*====================================================================*/
107 /* Some PCI shortcuts */
109 static int pci_readb (socket_info_t * s, int r, u_char * v)
111 return pci_read_config_byte (s->dev, r, v);
113 static int pci_writeb (socket_info_t * s, int r, u_char v)
115 return pci_write_config_byte (s->dev, r, v);
117 static int pci_readw (socket_info_t * s, int r, u_short * v)
119 return pci_read_config_word (s->dev, r, v);
121 static int pci_writew (socket_info_t * s, int r, u_short v)
123 return pci_write_config_word (s->dev, r, v);
126 static int pci_readl (socket_info_t * s, int r, u_int * v)
128 return pci_read_config_dword (s->dev, r, v);
130 static int pci_writel (socket_info_t * s, int r, u_int v)
132 return pci_write_config_dword (s->dev, r, v);
134 #endif /* !CONFIG_CPC45 */
136 /*====================================================================*/
140 #define cb_readb(s) readb((s)->cb_phys + 1)
141 #define cb_writeb(s, v) writeb(v, (s)->cb_phys)
142 #define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
143 #define cb_readl(s, r) readl((s)->cb_phys + (r))
144 #define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
147 static u_char i365_get (socket_info_t * s, u_short reg)
150 #ifdef CONFIG_PCMCIA_SLOT_A
156 val = I365_REG (slot, reg);
161 debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
165 static void i365_set (socket_info_t * s, u_short reg, u_char data)
167 #ifdef CONFIG_PCMCIA_SLOT_A
174 val = I365_REG (slot, reg);
177 cb_writeb2 (s, data);
179 debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
182 #else /* ! CONFIG_CPC45 */
184 #define cb_readb(s, r) readb((s)->cb_phys + (r))
185 #define cb_readl(s, r) readl((s)->cb_phys + (r))
186 #define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
187 #define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
189 static u_char i365_get (socket_info_t * s, u_short reg)
191 return cb_readb (s, 0x0800 + reg);
194 static void i365_set (socket_info_t * s, u_short reg, u_char data)
196 cb_writeb (s, 0x0800 + reg, data);
198 #endif /* CONFIG_CPC45 */
200 static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
202 i365_set (s, reg, i365_get (s, reg) | mask);
205 static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
207 i365_set (s, reg, i365_get (s, reg) & ~mask);
211 static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
213 u_char d = i365_get (s, reg);
215 i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
218 static u_short i365_get_pair (socket_info_t * s, u_short reg)
220 return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
222 #endif /* not used */
224 static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
226 i365_set (s, reg, data & 0xff);
227 i365_set (s, reg + 1, data >> 8);
231 /*======================================================================
233 Code to save and restore global state information for Cirrus
234 PD67xx controllers, and to set and report global configuration
237 ======================================================================*/
239 #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
241 static void cirrus_get_state (socket_info_t * s)
244 cirrus_state_t *p = &s->c_state;
246 p->misc1 = i365_get (s, PD67_MISC_CTL_1);
247 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
248 p->misc2 = i365_get (s, PD67_MISC_CTL_2);
249 for (i = 0; i < 6; i++)
250 p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
254 static void cirrus_set_state (socket_info_t * s)
258 cirrus_state_t *p = &s->c_state;
260 misc = i365_get (s, PD67_MISC_CTL_2);
261 i365_set (s, PD67_MISC_CTL_2, p->misc2);
262 if (misc & PD67_MC2_SUSPEND)
264 misc = i365_get (s, PD67_MISC_CTL_1);
265 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
266 i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
267 for (i = 0; i < 6; i++)
268 i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
271 static u_int cirrus_set_opts (socket_info_t * s)
273 cirrus_state_t *p = &s->c_state;
279 flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
280 flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
282 if (p->misc2 & PD67_MC2_IRQ15_RI)
283 strcat (buf, " [ring]");
284 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
285 strcat (buf, " [dyn mode]");
286 if (p->misc1 & PD67_MC1_INPACK_ENA)
287 strcat (buf, " [inpack]");
290 if (p->misc2 & PD67_MC2_IRQ15_RI)
294 strcat (buf, " [led]");
300 strcat (buf, " [dma]");
303 flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
305 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
306 strcat (buf, " [freq bypass]");
311 p->timer[0] = p->timer[3] = setup_time;
313 p->timer[1] = cmd_time;
314 p->timer[4] = cmd_time * 2 + 4;
316 if (p->timer[1] == 0) {
319 if (p->timer[0] == 0)
320 p->timer[0] = p->timer[3] = 1;
323 p->timer[2] = p->timer[5] = recov_time;
325 debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
327 p->timer[0], p->timer[1], p->timer[2],
328 p->timer[3], p->timer[4], p->timer[5]);
333 #else /* !CONFIG_CPC45 */
335 /*======================================================================
337 Code to save and restore global state information for TI 1130 and
338 TI 1131 controllers, and to set and report global configuration
341 ======================================================================*/
343 static void ti113x_get_state (socket_info_t * s)
345 ti113x_state_t *p = &s->state;
347 pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
348 pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
349 pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
350 pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
351 pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
354 static void ti113x_set_state (socket_info_t * s)
356 ti113x_state_t *p = &s->state;
358 pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
359 pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
360 pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
361 pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
362 pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
363 pci_writel (s, TI12XX_IRQMUX, p->irqmux);
364 i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
365 i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
368 static u_int ti113x_set_opts (socket_info_t * s)
370 ti113x_state_t *p = &s->state;
373 p->cardctl &= ~TI113X_CCR_ZVENABLE;
374 p->cardctl |= TI113X_CCR_SPKROUTEN;
378 #endif /* CONFIG_CPC45 */
380 /*======================================================================
382 Routines to handle common CardBus options
384 ======================================================================*/
386 /* Default settings for PCI command configuration register */
387 #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
388 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
390 static void cb_get_state (socket_info_t * s)
392 pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
393 pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
394 pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
395 pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
396 pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
397 pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
400 static void cb_set_state (socket_info_t * s)
403 pci_writel (s, CB_LEGACY_MODE_BASE, 0);
404 pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
406 pci_writew (s, PCI_COMMAND, CMD_DFLT);
407 pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
408 pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
409 pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
410 pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
411 pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
412 pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
415 static void cb_set_opts (socket_info_t * s)
427 /*======================================================================
429 Power control for Cardbus controllers: used both for 16-bit and
432 ======================================================================*/
434 static int cb_set_power (socket_info_t * s, socket_state_t * state)
440 reg = I365_PWR_NORESET;
441 if (state->flags & SS_PWR_AUTO)
442 reg |= I365_PWR_AUTO;
443 if (state->flags & SS_OUTPUT_ENA)
445 if (state->Vpp != 0) {
446 if (state->Vpp == 120) {
447 reg |= I365_VPP1_12V;
448 puts (" 12V card found: ");
449 } else if (state->Vpp == state->Vcc) {
452 puts (" power not found: ");
456 if (state->Vcc != 0) {
458 if (state->Vcc == 33) {
459 puts (" 3.3V card found: ");
460 i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
461 } else if (state->Vcc == 50) {
462 puts (" 5V card found: ");
463 i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
465 puts (" power not found: ");
470 if (reg != i365_get (s, I365_POWER)) {
471 reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
472 i365_set (s, I365_POWER, reg);
475 #else /* ! CONFIG_CPC45 */
477 /* restart card voltage detection if it seems appropriate */
478 if ((state->Vcc == 0) && (state->Vpp == 0) &&
479 !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
480 cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
481 switch (state->Vcc) {
494 switch (state->Vpp) {
504 reg |= CB_SC_VPP_12V;
509 if (reg != cb_readl (s, CB_SOCKET_CONTROL))
510 cb_writel (s, CB_SOCKET_CONTROL, reg);
511 #endif /* CONFIG_CPC45 */
515 /*======================================================================
517 Generic routines to get and set controller options
519 ======================================================================*/
521 static void get_bridge_state (socket_info_t * s)
524 cirrus_get_state (s);
526 ti113x_get_state (s);
531 static void set_bridge_state (socket_info_t * s)
534 i365_set (s, I365_GBLCTL, 0x00);
535 i365_set (s, I365_GENCTL, 0x00);
537 cirrus_set_state (s);
539 ti113x_set_state (s);
543 static void set_bridge_opts (socket_info_t * s)
553 /*====================================================================*/
554 #define PD67_EXT_INDEX 0x2e /* Extension index */
555 #define PD67_EXT_DATA 0x2f /* Extension data */
556 #define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
558 #define pd67_ext_get(s, r) \
559 (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
561 static int i365_get_status (socket_info_t * s, u_int * value)
566 u_char power, vcc, vpp;
570 status = i365_get (s, I365_IDENT);
571 status = i365_get (s, I365_STATUS);
572 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
573 if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
574 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
576 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
577 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
579 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
580 *value |= (status & I365_CS_READY) ? SS_READY : 0;
581 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
584 /* Check for Cirrus CL-PD67xx chips */
585 i365_set (s, PD67_CHIP_INFO, 0);
586 val = i365_get (s, PD67_CHIP_INFO);
588 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
589 val = i365_get (s, PD67_CHIP_INFO);
590 if ((val & PD67_INFO_CHIP_ID) == 0) {
591 s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
592 i365_set (s, PD67_EXT_INDEX, 0xe5);
593 if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
594 s->type = IS_VT83C469;
597 printf ("no Cirrus Chip found\n");
602 power = i365_get (s, I365_POWER);
603 state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
604 state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
605 vcc = power & I365_VCC_MASK;
606 vpp = power & I365_VPP1_MASK;
607 state.Vcc = state.Vpp = 0;
608 if((vcc== 0) || (vpp == 0)) {
610 * On the Cirrus we get the info which card voltage
611 * we have in EXTERN DATA and write it to MISC_CTL1
613 powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
614 if (powerstate & PD67_EXD_VS1(0)) {
616 i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
619 i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
621 i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
622 power = i365_get (s, I365_POWER);
624 if (power & I365_VCC_5V) {
625 state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
628 if (power == I365_VPP1_12V)
631 /* IO card, RESET flags, IO interrupt */
632 power = i365_get (s, I365_INTCTL);
633 state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
634 if (power & I365_PC_IOCARD)
635 state.flags |= SS_IOCARD;
636 state.io_irq = power & I365_IRQ_MASK;
638 /* Card status change mask */
639 power = i365_get (s, I365_CSCINT);
640 state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
641 if (state.flags & SS_IOCARD)
642 state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
644 state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
645 state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
646 state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
648 debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
649 "io_irq %d, csc_mask %#2.2x\n", state.flags,
650 state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
652 #else /* !CONFIG_CPC45 */
654 status = cb_readl (s, CB_SOCKET_STATE);
655 *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
656 *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
657 *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
658 *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
659 /* For now, ignore cards with unsupported voltage keys */
660 if (*value & SS_XVCARD)
661 *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
662 #endif /* CONFIG_CPC45 */
664 } /* i365_get_status */
666 static int i365_set_socket (socket_info_t * s, socket_state_t * state)
670 set_bridge_state (s);
672 /* IO card, RESET flag */
674 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
675 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
676 i365_set (s, I365_INTCTL, reg);
679 cb_set_power (s, state);
682 /* Card status change interrupt mask */
683 reg = s->cs_irq << 4;
684 if (state->csc_mask & SS_DETECT)
685 reg |= I365_CSC_DETECT;
686 if (state->flags & SS_IOCARD) {
687 if (state->csc_mask & SS_STSCHG)
688 reg |= I365_CSC_STSCHG;
690 if (state->csc_mask & SS_BATDEAD)
691 reg |= I365_CSC_BVD1;
692 if (state->csc_mask & SS_BATWARN)
693 reg |= I365_CSC_BVD2;
694 if (state->csc_mask & SS_READY)
695 reg |= I365_CSC_READY;
697 i365_set (s, I365_CSCINT, reg);
698 i365_get (s, I365_CSC);
701 #else /* !CONFIG_CPC45 */
703 reg = I365_PWR_NORESET;
704 if (state->flags & SS_PWR_AUTO)
705 reg |= I365_PWR_AUTO;
706 if (state->flags & SS_OUTPUT_ENA)
709 cb_set_power (s, state);
710 reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
712 if (reg != i365_get (s, I365_POWER))
713 i365_set (s, I365_POWER, reg);
714 #endif /* CONFIG_CPC45 */
717 } /* i365_set_socket */
719 /*====================================================================*/
721 static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
726 debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
727 mem->map, mem->flags, mem->speed,
728 mem->sys_start, mem->sys_stop, mem->card_start);
732 (mem->card_start > 0x3ffffff) ||
733 (mem->sys_start > mem->sys_stop) ||
734 (mem->speed > 1000)) {
738 /* Turn off the window before changing anything */
739 if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
740 i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
742 /* Take care of high byte, for PCI controllers */
743 i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
745 base = I365_MEM (map);
746 i = (mem->sys_start >> 12) & 0x0fff;
747 if (mem->flags & MAP_16BIT)
749 if (mem->flags & MAP_0WS)
751 i365_set_pair (s, base + I365_W_START, i);
753 i = (mem->sys_stop >> 12) & 0x0fff;
754 switch (mem->speed / CYCLE_TIME) {
764 i |= I365_MEM_WS1 | I365_MEM_WS0;
767 i365_set_pair (s, base + I365_W_STOP, i);
772 i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
774 if (mem->flags & MAP_WRPROT)
775 i |= I365_MEM_WRPROT;
776 if (mem->flags & MAP_ATTRIB)
778 i365_set_pair (s, base + I365_W_OFF, i);
781 /* set System Memory map Upper Adress */
782 i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
783 i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
786 /* Turn on the window if necessary */
787 if (mem->flags & MAP_ACTIVE)
788 i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
790 } /* i365_set_mem_map */
792 static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
797 /* comment out: comparison is always false due to limited range of data type */
798 if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
799 (io->stop < io->start))
801 /* Turn off the window before changing anything */
802 if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
803 i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
804 i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
805 i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
806 ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
808 ioctl |= I365_IOCTL_WAIT (map);
809 if (io->flags & MAP_0WS)
810 ioctl |= I365_IOCTL_0WS (map);
811 if (io->flags & MAP_16BIT)
812 ioctl |= I365_IOCTL_16BIT (map);
813 if (io->flags & MAP_AUTOSZ)
814 ioctl |= I365_IOCTL_IOCS16 (map);
815 i365_set (s, I365_IOCTL, ioctl);
816 /* Turn on the window if necessary */
817 if (io->flags & MAP_ACTIVE)
818 i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
820 } /* i365_set_io_map */
822 /*====================================================================*/
824 int i82365_init (void)
830 if (SPD67290Init () != 0)
833 if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
834 /* Controller not found */
837 debug ("i82365 Device Found!\n");
839 pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
840 socket.cb_phys &= ~0xf;
843 /* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */
844 socket.cb_phys += 0xfe000000;
847 get_bridge_state (&socket);
848 set_bridge_opts (&socket);
850 i = i365_get_status (&socket, &val);
854 puts (pcic[socket.type].name);
856 printf ("i82365: Controller not found.\n");
859 if((val & SS_DETECT) != SS_DETECT){
863 #else /* !CONFIG_CPC45 */
864 if (val & SS_DETECT) {
865 if (val & SS_3VCARD) {
866 state.Vcc = state.Vpp = 33;
867 puts (" 3.3V card found: ");
868 } else if (!(val & SS_XVCARD)) {
869 state.Vcc = state.Vpp = 50;
870 puts (" 5.0V card found: ");
872 puts ("i82365: unsupported voltage key\n");
873 state.Vcc = state.Vpp = 0;
876 /* No card inserted */
880 #endif /* CONFIG_CPC45 */
883 state.flags |= SS_OUTPUT_ENA;
885 state.flags = SS_IOCARD | SS_OUTPUT_ENA;
890 i365_set_socket (&socket, &state);
892 for (i = 500; i; i--) {
893 if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
899 /* PC Card not ready for data transfer */
900 puts ("i82365 PC Card not ready for data transfer\n");
903 debug (" PC Card ready for data transfer: ");
906 mem.flags = MAP_ATTRIB | MAP_ACTIVE;
908 mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
909 mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
911 i365_set_mem_map (&socket, &mem);
915 mem.flags = MAP_ACTIVE;
917 mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE;
918 mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1;
920 i365_set_mem_map (&socket, &mem);
922 #else /* !CONFIG_CPC45 */
925 io.flags = MAP_AUTOSZ | MAP_ACTIVE;
929 i365_set_io_map (&socket, &io);
931 #endif /* CONFIG_CPC45 */
934 i82365_dump_regions (socket.dev);
940 void i82365_exit (void)
948 i365_set_io_map (&socket, &io);
954 mem.sys_stop = 0x1000;
957 i365_set_mem_map (&socket, &mem);
964 mem.sys_stop = 0x1000;
967 i365_set_mem_map (&socket, &mem);
968 #else /* !CONFIG_CPC45 */
969 socket.state.sysctl &= 0xFFFF00FF;
971 state.Vcc = state.Vpp = 0;
973 i365_set_socket (&socket, &state);
976 /*======================================================================
980 ======================================================================*/
983 static void i82365_dump_regions (pci_dev_t dev)
986 u_int *mem = (void *) socket.cb_phys;
987 u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
988 u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
990 pci_read_config_dword (dev, 0x00, tmp + 0);
991 pci_read_config_dword (dev, 0x80, tmp + 1);
993 printf ("PCI CONF: %08X ... %08X\n",
995 printf ("PCI MEM: ... %08X ... %08X\n",
996 mem[0x8 / 4], mem[0x800 / 4]);
997 printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
998 cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
999 cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
1000 printf ("CIS CONF: %02X %02X %02X ...\n",
1001 cis[0x200], cis[0x202], cis[0x204]);
1002 printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
1003 ide[0], ide[1], ide[2], ide[3],
1004 ide[4], ide[5], ide[6], ide[7]);