git.sur5r.net Git - u-boot/blob - drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <dm.h>
  15 #include <dm/device.h>
  16 #include <generic-phy.h>
  17 #include <asm/gpio.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/cpu.h>
  21
  22 #define REG_ISCR                        0x00
  23 #define REG_PHYCTL_A10                  0x04
  24 #define REG_PHYBIST                     0x08
  25 #define REG_PHYTUNE                     0x0c
  26 #define REG_PHYCTL_A33                  0x10
  27 #define REG_PHY_OTGCTL                  0x20
  28 #define REG_PMU_UNK1                    0x10
  29
  30 /* Common Control Bits for Both PHYs */
  31 #define PHY_PLL_BW                      0x03
  32 #define PHY_RES45_CAL_EN                0x0c
  33
  34 /* Private Control Bits for Each PHY */
  35 #define PHY_TX_AMPLITUDE_TUNE           0x20
  36 #define PHY_TX_SLEWRATE_TUNE            0x22
  37 #define PHY_DISCON_TH_SEL               0x2a
  38
  39 #define PHYCTL_DATA                     BIT(7)
  40 #define OTGCTL_ROUTE_MUSB               BIT(0)
  41
  42 #define PHY_TX_RATE                     BIT(4)
  43 #define PHY_TX_MAGNITUDE                BIT(2)
  44 #define PHY_TX_AMPLITUDE_LEN            5
  45
  46 #define PHY_RES45_CAL_DATA              BIT(0)
  47 #define PHY_RES45_CAL_LEN               1
  48 #define PHY_DISCON_TH_LEN               2
  49
  50 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  51 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  52 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  53 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  54
  55 #define MAX_PHYS                        4
  56
  57 enum sun4i_usb_phy_type {
  58         sun50i_a64_phy,
  59 };
  60
  61 struct sun4i_usb_phy_cfg {
  62         int num_phys;
  63         enum sun4i_usb_phy_type type;
  64         u32 disc_thresh;
  65         u8 phyctl_offset;
  66         bool enable_pmu_unk1;
  67         bool phy0_dual_route;
  68 };
  69
  70 struct sun4i_usb_phy_info {
  71         const char *gpio_vbus;
  72         const char *gpio_vbus_det;
  73         const char *gpio_id_det;
  74         int rst_mask;
  75 } phy_info[] = {
  76         {
  77                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
  78                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
  79                 .gpio_id_det = CONFIG_USB0_ID_DET,
  80                 .rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
  81         },
  82         {
  83                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
  84                 .gpio_vbus_det = NULL,
  85                 .gpio_id_det = NULL,
  86                 .rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
  87         },
  88         {
  89                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
  90                 .gpio_vbus_det = NULL,
  91                 .gpio_id_det = NULL,
  92                 .rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
  93         },
  94         {
  95                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
  96                 .gpio_vbus_det = NULL,
  97                 .gpio_id_det = NULL,
  98                 .rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
  99         },
 100 };
 101
 102 struct sun4i_usb_phy_plat {
 103         void __iomem *pmu;
 104         int power_on_count;
 105         int gpio_vbus;
 106         int gpio_vbus_det;
 107         int gpio_id_det;
 108         int rst_mask;
 109         int id;
 110 };
 111
 112 struct sun4i_usb_phy_data {
 113         void __iomem *base;
 114         struct sunxi_ccm_reg *ccm;
 115         const struct sun4i_usb_phy_cfg *cfg;
 116         struct sun4i_usb_phy_plat *usb_phy;
 117 };
 118
 119 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 120
 121 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 122 {
 123         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 124         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 125         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 126         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 127         int i;
 128
 129         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 130                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 131                 writel(0, phyctl);
 132         }
 133
 134         for (i = 0; i < len; i++) {
 135                 temp = readl(phyctl);
 136
 137                 /* clear the address portion */
 138                 temp &= ~(0xff << 8);
 139
 140                 /* set the address */
 141                 temp |= ((addr + i) << 8);
 142                 writel(temp, phyctl);
 143
 144                 /* set the data bit and clear usbc bit*/
 145                 temp = readb(phyctl);
 146                 if (data & 0x1)
 147                         temp |= PHYCTL_DATA;
 148                 else
 149                         temp &= ~PHYCTL_DATA;
 150                 temp &= ~usbc_bit;
 151                 writeb(temp, phyctl);
 152
 153                 /* pulse usbc_bit */
 154                 temp = readb(phyctl);
 155                 temp |= usbc_bit;
 156                 writeb(temp, phyctl);
 157
 158                 temp = readb(phyctl);
 159                 temp &= ~usbc_bit;
 160                 writeb(temp, phyctl);
 161
 162                 data >>= 1;
 163         }
 164 }
 165
 166 static void sun4i_usb_phy_passby(struct sun4i_usb_phy_plat *usb_phy,
 167                                  bool enable)
 168 {
 169         u32 bits, reg_value;
 170
 171         if (!usb_phy->pmu)
 172                 return;
 173
 174         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 175                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 176         reg_value = readl(usb_phy->pmu);
 177
 178         if (enable)
 179                 reg_value |= bits;
 180         else
 181                 reg_value &= ~bits;
 182
 183         writel(reg_value, usb_phy->pmu);
 184 }
 185
 186 static int sun4i_usb_phy_power_on(struct phy *phy)
 187 {
 188         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 189         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 190
 191         if (initial_usb_scan_delay) {
 192                 mdelay(initial_usb_scan_delay);
 193                 initial_usb_scan_delay = 0;
 194         }
 195
 196         usb_phy->power_on_count++;
 197         if (usb_phy->power_on_count != 1)
 198                 return 0;
 199
 200         if (usb_phy->gpio_vbus >= 0)
 201                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
 202
 203         return 0;
 204 }
 205
 206 static int sun4i_usb_phy_power_off(struct phy *phy)
 207 {
 208         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 209         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 210
 211         usb_phy->power_on_count--;
 212         if (usb_phy->power_on_count != 0)
 213                 return 0;
 214
 215         if (usb_phy->gpio_vbus >= 0)
 216                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
 217
 218         return 0;
 219 }
 220
 221 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 222 {
 223         u32 regval;
 224
 225         regval = readl(data->base + REG_PHY_OTGCTL);
 226         if (!id_det) {
 227                 /* Host mode. Route phy0 to EHCI/OHCI */
 228                 regval &= ~OTGCTL_ROUTE_MUSB;
 229         } else {
 230                 /* Peripheral mode. Route phy0 to MUSB */
 231                 regval |= OTGCTL_ROUTE_MUSB;
 232         }
 233         writel(regval, data->base + REG_PHY_OTGCTL);
 234 }
 235
 236 static int sun4i_usb_phy_init(struct phy *phy)
 237 {
 238         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 239         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 240         u32 val;
 241
 242         setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 243
 244         if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
 245                 val = readl(usb_phy->pmu + REG_PMU_UNK1);
 246                 writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
 247         }
 248
 249         if (usb_phy->id == 0)
 250                 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, PHY_RES45_CAL_DATA,
 251                                     PHY_RES45_CAL_LEN);
 252
 253         /* Adjust PHY's magnitude and rate */
 254         sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, PHY_TX_MAGNITUDE |
 255                             PHY_TX_RATE, PHY_TX_AMPLITUDE_LEN);
 256
 257         /* Disconnect threshold adjustment */
 258         sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->cfg->disc_thresh,
 259                             PHY_DISCON_TH_LEN);
 260
 261         if (usb_phy->id != 0)
 262                 sun4i_usb_phy_passby(usb_phy, true);
 263
 264         sun4i_usb_phy0_reroute(data, true);
 265
 266         return 0;
 267 }
 268
 269 static int sun4i_usb_phy_exit(struct phy *phy)
 270 {
 271         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 272         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 273
 274         sun4i_usb_phy_passby(usb_phy, false);
 275
 276         clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 277
 278         return 0;
 279 }
 280
 281 static int sun4i_usb_phy_xlate(struct phy *phy,
 282                                struct ofnode_phandle_args *args)
 283 {
 284         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 285
 286         if (args->args_count >= data->cfg->num_phys)
 287                 return -EINVAL;
 288
 289         if (args->args_count)
 290                 phy->id = args->args[0];
 291         else
 292                 phy->id = 0;
 293
 294         debug("%s: phy_id = %ld\n", __func__, phy->id);
 295         return 0;
 296 }
 297
 298 static struct phy_ops sun4i_usb_phy_ops = {
 299         .of_xlate = sun4i_usb_phy_xlate,
 300         .init = sun4i_usb_phy_init,
 301         .power_on = sun4i_usb_phy_power_on,
 302         .power_off = sun4i_usb_phy_power_off,
 303         .exit = sun4i_usb_phy_exit,
 304 };
 305
 306 static int sun4i_usb_phy_probe(struct udevice *dev)
 307 {
 308         struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
 309         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 310         int i, ret;
 311
 312         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 313         if (!data->cfg)
 314                 return -EINVAL;
 315
 316         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 317         if (IS_ERR(data->base))
 318                 return PTR_ERR(data->base);
 319
 320         data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 321         if (IS_ERR(data->ccm))
 322                 return PTR_ERR(data->ccm);
 323
 324         data->usb_phy = plat;
 325         for (i = 0; i < data->cfg->num_phys; i++) {
 326                 struct sun4i_usb_phy_plat *phy = &plat[i];
 327                 struct sun4i_usb_phy_info *info = &phy_info[i];
 328                 char name[16];
 329
 330                 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
 331                 if (phy->gpio_vbus >= 0) {
 332                         ret = gpio_request(phy->gpio_vbus, "usb_vbus");
 333                         if (ret)
 334                                 return ret;
 335                         ret = gpio_direction_output(phy->gpio_vbus, 0);
 336                         if (ret)
 337                                 return ret;
 338                 }
 339
 340                 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
 341                 if (phy->gpio_vbus_det >= 0) {
 342                         ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
 343                         if (ret)
 344                                 return ret;
 345                         ret = gpio_direction_input(phy->gpio_vbus_det);
 346                         if (ret)
 347                                 return ret;
 348                 }
 349
 350                 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
 351                 if (phy->gpio_id_det >= 0) {
 352                         ret = gpio_request(phy->gpio_id_det, "usb_id_det");
 353                         if (ret)
 354                                 return ret;
 355                         ret = gpio_direction_input(phy->gpio_id_det);
 356                         if (ret)
 357                                 return ret;
 358                         sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 359                 }
 360
 361                 if (i || data->cfg->phy0_dual_route) {
 362                         snprintf(name, sizeof(name), "pmu%d", i);
 363                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 364                         if (IS_ERR(phy->pmu))
 365                                 return PTR_ERR(phy->pmu);
 366                 }
 367
 368                 phy->id = i;
 369                 phy->rst_mask = info->rst_mask;
 370         };
 371
 372         setbits_le32(&data->ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
 373
 374         debug("Allwinner Sun4I USB PHY driver loaded\n");
 375         return 0;
 376 }
 377
 378 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 379         .num_phys = 2,
 380         .type = sun50i_a64_phy,
 381         .disc_thresh = 3,
 382         .phyctl_offset = REG_PHYCTL_A33,
 383         .enable_pmu_unk1 = true,
 384         .phy0_dual_route = true,
 385 };
 386
 387 static const struct udevice_id sun4i_usb_phy_ids[] = {
 388         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 389         { }
 390 };
 391
 392 U_BOOT_DRIVER(sun4i_usb_phy) = {
 393         .name   = "sun4i_usb_phy",
 394         .id     = UCLASS_PHY,
 395         .of_match = sun4i_usb_phy_ids,
 396         .ops = &sun4i_usb_phy_ops,
 397         .probe = sun4i_usb_phy_probe,
 398         .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 399         .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
 400 };