git.sur5r.net Git - u-boot/blob - drivers/phy/allwinner/phy-sun4i-usb.c

   1 /*
   2  * Allwinner sun4i USB PHY driver
   3  *
   4  * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
   5  * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
   6  * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
   7  *
   8  * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <dm.h>
  15 #include <dm/device.h>
  16 #include <generic-phy.h>
  17 #include <phy-sun4i-usb.h>
  18 #include <asm/gpio.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/cpu.h>
  22
  23 #define REG_ISCR                        0x00
  24 #define REG_PHYCTL_A10                  0x04
  25 #define REG_PHYBIST                     0x08
  26 #define REG_PHYTUNE                     0x0c
  27 #define REG_PHYCTL_A33                  0x10
  28 #define REG_PHY_OTGCTL                  0x20
  29 #define REG_PMU_UNK1                    0x10
  30
  31 /* Common Control Bits for Both PHYs */
  32 #define PHY_PLL_BW                      0x03
  33 #define PHY_RES45_CAL_EN                0x0c
  34
  35 /* Private Control Bits for Each PHY */
  36 #define PHY_TX_AMPLITUDE_TUNE           0x20
  37 #define PHY_TX_SLEWRATE_TUNE            0x22
  38 #define PHY_DISCON_TH_SEL               0x2a
  39
  40 #define PHYCTL_DATA                     BIT(7)
  41 #define OTGCTL_ROUTE_MUSB               BIT(0)
  42
  43 #define PHY_TX_RATE                     BIT(4)
  44 #define PHY_TX_MAGNITUDE                BIT(2)
  45 #define PHY_TX_AMPLITUDE_LEN            5
  46
  47 #define PHY_RES45_CAL_DATA              BIT(0)
  48 #define PHY_RES45_CAL_LEN               1
  49 #define PHY_DISCON_TH_LEN               2
  50
  51 #define SUNXI_AHB_ICHR8_EN              BIT(10)
  52 #define SUNXI_AHB_INCR4_BURST_EN        BIT(9)
  53 #define SUNXI_AHB_INCRX_ALIGN_EN        BIT(8)
  54 #define SUNXI_ULPI_BYPASS_EN            BIT(0)
  55
  56 /* A83T specific control bits for PHY0 */
  57 #define PHY_CTL_VBUSVLDEXT              BIT(5)
  58 #define PHY_CTL_SIDDQ                   BIT(3)
  59
  60 /* A83T specific control bits for PHY2 HSIC */
  61 #define SUNXI_EHCI_HS_FORCE             BIT(20)
  62 #define SUNXI_HSIC_CONNECT_INT          BIT(16)
  63 #define SUNXI_HSIC                      BIT(1)
  64
  65 #define MAX_PHYS                        4
  66
  67 enum sun4i_usb_phy_type {
  68         sun4i_a10_phy,
  69         sun8i_a83t_phy,
  70         sun8i_h3_phy,
  71         sun8i_v3s_phy,
  72         sun50i_a64_phy,
  73 };
  74
  75 struct sun4i_usb_phy_cfg {
  76         int num_phys;
  77         enum sun4i_usb_phy_type type;
  78         u32 disc_thresh;
  79         u8 phyctl_offset;
  80         bool enable_pmu_unk1;
  81         bool phy0_dual_route;
  82 };
  83
  84 struct sun4i_usb_phy_info {
  85         const char *gpio_vbus;
  86         const char *gpio_vbus_det;
  87         const char *gpio_id_det;
  88         int rst_mask;
  89 } phy_info[] = {
  90         {
  91                 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
  92                 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
  93                 .gpio_id_det = CONFIG_USB0_ID_DET,
  94                 .rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
  95         },
  96         {
  97                 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
  98                 .gpio_vbus_det = NULL,
  99                 .gpio_id_det = NULL,
 100                 .rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
 101         },
 102         {
 103                 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
 104                 .gpio_vbus_det = NULL,
 105                 .gpio_id_det = NULL,
 106 #ifdef CONFIG_MACH_SUN8I_A83T
 107                 .rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
 108                              CCM_USB_CTRL_12M_CLK),
 109 #else
 110                 .rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
 111 #endif
 112         },
 113         {
 114                 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
 115                 .gpio_vbus_det = NULL,
 116                 .gpio_id_det = NULL,
 117 #ifdef CONFIG_MACH_SUN6I
 118                 .rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
 119 #endif
 120         },
 121 };
 122
 123 struct sun4i_usb_phy_plat {
 124         void __iomem *pmu;
 125         int power_on_count;
 126         int gpio_vbus;
 127         int gpio_vbus_det;
 128         int gpio_id_det;
 129         int rst_mask;
 130         int id;
 131 };
 132
 133 struct sun4i_usb_phy_data {
 134         void __iomem *base;
 135         struct sunxi_ccm_reg *ccm;
 136         const struct sun4i_usb_phy_cfg *cfg;
 137         struct sun4i_usb_phy_plat *usb_phy;
 138 };
 139
 140 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
 141
 142 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
 143 {
 144         struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
 145         struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
 146         u32 temp, usbc_bit = BIT(usb_phy->id * 2);
 147         void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
 148         int i;
 149
 150         if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
 151                 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 152                 writel(0, phyctl);
 153         }
 154
 155         for (i = 0; i < len; i++) {
 156                 temp = readl(phyctl);
 157
 158                 /* clear the address portion */
 159                 temp &= ~(0xff << 8);
 160
 161                 /* set the address */
 162                 temp |= ((addr + i) << 8);
 163                 writel(temp, phyctl);
 164
 165                 /* set the data bit and clear usbc bit*/
 166                 temp = readb(phyctl);
 167                 if (data & 0x1)
 168                         temp |= PHYCTL_DATA;
 169                 else
 170                         temp &= ~PHYCTL_DATA;
 171                 temp &= ~usbc_bit;
 172                 writeb(temp, phyctl);
 173
 174                 /* pulse usbc_bit */
 175                 temp = readb(phyctl);
 176                 temp |= usbc_bit;
 177                 writeb(temp, phyctl);
 178
 179                 temp = readb(phyctl);
 180                 temp &= ~usbc_bit;
 181                 writeb(temp, phyctl);
 182
 183                 data >>= 1;
 184         }
 185 }
 186
 187 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
 188 {
 189         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 190         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 191         u32 bits, reg_value;
 192
 193         if (!usb_phy->pmu)
 194                 return;
 195
 196         bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
 197                 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
 198
 199         /* A83T USB2 is HSIC */
 200         if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
 201                 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
 202                         SUNXI_HSIC;
 203
 204         reg_value = readl(usb_phy->pmu);
 205
 206         if (enable)
 207                 reg_value |= bits;
 208         else
 209                 reg_value &= ~bits;
 210
 211         writel(reg_value, usb_phy->pmu);
 212 }
 213
 214 static int sun4i_usb_phy_power_on(struct phy *phy)
 215 {
 216         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 217         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 218
 219         if (initial_usb_scan_delay) {
 220                 mdelay(initial_usb_scan_delay);
 221                 initial_usb_scan_delay = 0;
 222         }
 223
 224         usb_phy->power_on_count++;
 225         if (usb_phy->power_on_count != 1)
 226                 return 0;
 227
 228         if (usb_phy->gpio_vbus >= 0)
 229                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
 230
 231         return 0;
 232 }
 233
 234 static int sun4i_usb_phy_power_off(struct phy *phy)
 235 {
 236         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 237         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 238
 239         usb_phy->power_on_count--;
 240         if (usb_phy->power_on_count != 0)
 241                 return 0;
 242
 243         if (usb_phy->gpio_vbus >= 0)
 244                 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
 245
 246         return 0;
 247 }
 248
 249 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
 250 {
 251         u32 regval;
 252
 253         regval = readl(data->base + REG_PHY_OTGCTL);
 254         if (!id_det) {
 255                 /* Host mode. Route phy0 to EHCI/OHCI */
 256                 regval &= ~OTGCTL_ROUTE_MUSB;
 257         } else {
 258                 /* Peripheral mode. Route phy0 to MUSB */
 259                 regval |= OTGCTL_ROUTE_MUSB;
 260         }
 261         writel(regval, data->base + REG_PHY_OTGCTL);
 262 }
 263
 264 static int sun4i_usb_phy_init(struct phy *phy)
 265 {
 266         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 267         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 268         u32 val;
 269
 270         setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 271
 272         if (data->cfg->type == sun8i_a83t_phy) {
 273                 if (phy->id == 0) {
 274                         val = readl(data->base + data->cfg->phyctl_offset);
 275                         val |= PHY_CTL_VBUSVLDEXT;
 276                         val &= ~PHY_CTL_SIDDQ;
 277                         writel(val, data->base + data->cfg->phyctl_offset);
 278                 }
 279         } else {
 280                 if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
 281                         val = readl(usb_phy->pmu + REG_PMU_UNK1);
 282                         writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
 283                 }
 284
 285                 if (usb_phy->id == 0)
 286                         sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 287                                             PHY_RES45_CAL_DATA,
 288                                             PHY_RES45_CAL_LEN);
 289
 290                 /* Adjust PHY's magnitude and rate */
 291                 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
 292                                     PHY_TX_MAGNITUDE | PHY_TX_RATE,
 293                                     PHY_TX_AMPLITUDE_LEN);
 294
 295                 /* Disconnect threshold adjustment */
 296                 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
 297                                     data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
 298         }
 299
 300         if (usb_phy->id != 0)
 301                 sun4i_usb_phy_passby(phy, true);
 302
 303         sun4i_usb_phy0_reroute(data, true);
 304
 305         return 0;
 306 }
 307
 308 static int sun4i_usb_phy_exit(struct phy *phy)
 309 {
 310         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 311         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 312
 313         if (phy->id == 0) {
 314                 if (data->cfg->type == sun8i_a83t_phy) {
 315                         void __iomem *phyctl = data->base +
 316                                 data->cfg->phyctl_offset;
 317
 318                         writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
 319                 }
 320         }
 321
 322         sun4i_usb_phy_passby(phy, false);
 323
 324         clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
 325
 326         return 0;
 327 }
 328
 329 static int sun4i_usb_phy_xlate(struct phy *phy,
 330                                struct ofnode_phandle_args *args)
 331 {
 332         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 333
 334         if (args->args_count >= data->cfg->num_phys)
 335                 return -EINVAL;
 336
 337         if (args->args_count)
 338                 phy->id = args->args[0];
 339         else
 340                 phy->id = 0;
 341
 342         debug("%s: phy_id = %ld\n", __func__, phy->id);
 343         return 0;
 344 }
 345
 346 int sun4i_usb_phy_vbus_detect(struct phy *phy)
 347 {
 348         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 349         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 350         int err, retries = 3;
 351
 352         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 353
 354         if (usb_phy->gpio_vbus_det < 0)
 355                 return usb_phy->gpio_vbus_det;
 356
 357         err = gpio_get_value(usb_phy->gpio_vbus_det);
 358         /*
 359          * Vbus may have been provided by the board and just been turned of
 360          * some milliseconds ago on reset, what we're measuring then is a
 361          * residual charge on Vbus, sleep a bit and try again.
 362          */
 363         while (err > 0 && retries--) {
 364                 mdelay(100);
 365                 err = gpio_get_value(usb_phy->gpio_vbus_det);
 366         }
 367
 368         return err;
 369 }
 370
 371 int sun4i_usb_phy_id_detect(struct phy *phy)
 372 {
 373         struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 374         struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 375
 376         debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
 377
 378         if (usb_phy->gpio_id_det < 0)
 379                 return usb_phy->gpio_id_det;
 380
 381         return gpio_get_value(usb_phy->gpio_id_det);
 382 }
 383
 384 static struct phy_ops sun4i_usb_phy_ops = {
 385         .of_xlate = sun4i_usb_phy_xlate,
 386         .init = sun4i_usb_phy_init,
 387         .power_on = sun4i_usb_phy_power_on,
 388         .power_off = sun4i_usb_phy_power_off,
 389         .exit = sun4i_usb_phy_exit,
 390 };
 391
 392 static int sun4i_usb_phy_probe(struct udevice *dev)
 393 {
 394         struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
 395         struct sun4i_usb_phy_data *data = dev_get_priv(dev);
 396         int i, ret;
 397
 398         data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
 399         if (!data->cfg)
 400                 return -EINVAL;
 401
 402         data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
 403         if (IS_ERR(data->base))
 404                 return PTR_ERR(data->base);
 405
 406         data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 407         if (IS_ERR(data->ccm))
 408                 return PTR_ERR(data->ccm);
 409
 410         data->usb_phy = plat;
 411         for (i = 0; i < data->cfg->num_phys; i++) {
 412                 struct sun4i_usb_phy_plat *phy = &plat[i];
 413                 struct sun4i_usb_phy_info *info = &phy_info[i];
 414                 char name[16];
 415
 416                 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
 417                 if (phy->gpio_vbus >= 0) {
 418                         ret = gpio_request(phy->gpio_vbus, "usb_vbus");
 419                         if (ret)
 420                                 return ret;
 421                         ret = gpio_direction_output(phy->gpio_vbus, 0);
 422                         if (ret)
 423                                 return ret;
 424                 }
 425
 426                 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
 427                 if (phy->gpio_vbus_det >= 0) {
 428                         ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
 429                         if (ret)
 430                                 return ret;
 431                         ret = gpio_direction_input(phy->gpio_vbus_det);
 432                         if (ret)
 433                                 return ret;
 434                 }
 435
 436                 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
 437                 if (phy->gpio_id_det >= 0) {
 438                         ret = gpio_request(phy->gpio_id_det, "usb_id_det");
 439                         if (ret)
 440                                 return ret;
 441                         ret = gpio_direction_input(phy->gpio_id_det);
 442                         if (ret)
 443                                 return ret;
 444                         sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 445                 }
 446
 447                 if (i || data->cfg->phy0_dual_route) {
 448                         snprintf(name, sizeof(name), "pmu%d", i);
 449                         phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
 450                         if (IS_ERR(phy->pmu))
 451                                 return PTR_ERR(phy->pmu);
 452                 }
 453
 454                 phy->id = i;
 455                 phy->rst_mask = info->rst_mask;
 456         };
 457
 458         setbits_le32(&data->ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
 459
 460         debug("Allwinner Sun4I USB PHY driver loaded\n");
 461         return 0;
 462 }
 463
 464 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 465         .num_phys = 3,
 466         .type = sun4i_a10_phy,
 467         .disc_thresh = 3,
 468         .phyctl_offset = REG_PHYCTL_A10,
 469         .enable_pmu_unk1 = false,
 470 };
 471
 472 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 473         .num_phys = 2,
 474         .type = sun4i_a10_phy,
 475         .disc_thresh = 2,
 476         .phyctl_offset = REG_PHYCTL_A10,
 477         .enable_pmu_unk1 = false,
 478 };
 479
 480 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 481         .num_phys = 3,
 482         .type = sun4i_a10_phy,
 483         .disc_thresh = 2,
 484         .phyctl_offset = REG_PHYCTL_A10,
 485         .enable_pmu_unk1 = false,
 486 };
 487
 488 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
 489         .num_phys = 3,
 490         .type = sun8i_a83t_phy,
 491         .phyctl_offset = REG_PHYCTL_A33,
 492 };
 493
 494 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 495         .num_phys = 4,
 496         .type = sun8i_h3_phy,
 497         .disc_thresh = 3,
 498         .phyctl_offset = REG_PHYCTL_A33,
 499         .enable_pmu_unk1 = true,
 500         .phy0_dual_route = true,
 501 };
 502
 503 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 504         .num_phys = 1,
 505         .type = sun8i_v3s_phy,
 506         .disc_thresh = 3,
 507         .phyctl_offset = REG_PHYCTL_A33,
 508         .enable_pmu_unk1 = true,
 509         .phy0_dual_route = true,
 510 };
 511
 512 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 513         .num_phys = 2,
 514         .type = sun50i_a64_phy,
 515         .disc_thresh = 3,
 516         .phyctl_offset = REG_PHYCTL_A33,
 517         .enable_pmu_unk1 = true,
 518         .phy0_dual_route = true,
 519 };
 520
 521 static const struct udevice_id sun4i_usb_phy_ids[] = {
 522         { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
 523         { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
 524         { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
 525         { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
 526         { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 527         { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
 528         { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 529         { }
 530 };
 531
 532 U_BOOT_DRIVER(sun4i_usb_phy) = {
 533         .name   = "sun4i_usb_phy",
 534         .id     = UCLASS_PHY,
 535         .of_match = sun4i_usb_phy_ids,
 536         .ops = &sun4i_usb_phy_ops,
 537         .probe = sun4i_usb_phy_probe,
 538         .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
 539         .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
 540 };