git.sur5r.net Git - u-boot/blob - drivers/phy/marvell/comphy.h

   1 /*
   2  * Copyright (C) 2015-2016 Marvell International Ltd.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _COMPHY_H_
   8 #define _COMPHY_H_
   9
  10 #include <dt-bindings/comphy/comphy_data.h>
  11 #include <fdtdec.h>
  12
  13 #if defined(DEBUG)
  14 #define debug_enter()   printf("----> Enter %s\n", __func__);
  15 #define debug_exit()    printf("<---- Exit  %s\n", __func__);
  16 #else
  17 #define debug_enter()
  18 #define debug_exit()
  19 #endif
  20
  21 /* COMPHY registers */
  22 #define COMMON_PHY_CFG1_REG                     0x0
  23 #define COMMON_PHY_CFG1_PWR_UP_OFFSET           1
  24 #define COMMON_PHY_CFG1_PWR_UP_MASK             \
  25         (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
  26 #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET      2
  27 #define COMMON_PHY_CFG1_PIPE_SELECT_MASK        \
  28         (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
  29 #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET     13
  30 #define COMMON_PHY_CFG1_PWR_ON_RESET_MASK       \
  31         (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
  32 #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET        14
  33 #define COMMON_PHY_CFG1_CORE_RSTN_MASK          \
  34         (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
  35 #define COMMON_PHY_PHY_MODE_OFFSET              15
  36 #define COMMON_PHY_PHY_MODE_MASK                \
  37         (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
  38
  39 #define COMMON_PHY_CFG6_REG                     0x14
  40 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET        18
  41 #define COMMON_PHY_CFG6_IF_40_SEL_MASK          \
  42         (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
  43
  44 #define COMMON_SELECTOR_PHY_OFFSET              0x140
  45 #define COMMON_SELECTOR_PIPE_OFFSET             0x144
  46
  47 #define COMMON_PHY_SD_CTRL1                     0x148
  48 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET      0
  49 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK        0xFFFF
  50 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET   24
  51 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK     \
  52         (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
  53 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET   25
  54 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK     \
  55         (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
  56 #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET       26
  57 #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK         \
  58         (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
  59 #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET       27
  60 #define COMMON_PHY_SD_CTRL1_RXAUI0_MASK         \
  61         (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
  62
  63 /* ToDo: Get this address via DT */
  64 #define MVEBU_CP0_REGS_BASE                     0xF2000000UL
  65
  66 #define DFX_DEV_GEN_CTRL12                      (MVEBU_CP0_REGS_BASE + 0x400280)
  67 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET         7
  68 #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK           \
  69         (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
  70
  71 #define MAX_LANE_OPTIONS                        10
  72 #define MAX_UTMI_PHY_COUNT                      3
  73
  74 struct comphy_mux_options {
  75         u32 type;
  76         u32 mux_value;
  77 };
  78
  79 struct comphy_mux_data {
  80         u32 max_lane_values;
  81         struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
  82 };
  83
  84 struct comphy_map {
  85         u32 type;
  86         u32 speed;
  87         u32 invert;
  88         bool clk_src;
  89         bool end_point;
  90 };
  91
  92 struct chip_serdes_phy_config {
  93         struct comphy_mux_data *mux_data;
  94         int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
  95                                     struct comphy_map *);
  96         void __iomem *comphy_base_addr;
  97         void __iomem *hpipe3_base_addr;
  98         u32 comphy_lanes_count;
  99         u32 comphy_mux_bitcount;
 100         u32 cp_index;
 101 };
 102
 103 /* Register helper functions */
 104 void reg_set(void __iomem *addr, u32 data, u32 mask);
 105 void reg_set_silent(void __iomem *addr, u32 data, u32 mask);
 106 void reg_set16(void __iomem *addr, u16 data, u16 mask);
 107 void reg_set_silent16(void __iomem *addr, u16 data, u16 mask);
 108
 109 /* SoC specific init functions */
 110 #ifdef CONFIG_ARMADA_3700
 111 int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 112                       struct comphy_map *serdes_map);
 113 #else
 114 static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 115                                     struct comphy_map *serdes_map)
 116 {
 117         /*
 118          * This function should never be called in this configuration, so
 119          * lets return an error here.
 120          */
 121         return -1;
 122 }
 123 #endif
 124
 125 #ifdef CONFIG_ARMADA_8K
 126 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 127                       struct comphy_map *serdes_map);
 128 #else
 129 static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 130                       struct comphy_map *serdes_map)
 131 {
 132         /*
 133          * This function should never be called in this configuration, so
 134          * lets return an error here.
 135          */
 136         return -1;
 137 }
 138 #endif
 139
 140 void comphy_dedicated_phys_init(void);
 141
 142 /* MUX function */
 143 void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 144                      struct comphy_map *comphy_map_data,
 145                      void __iomem *selector_base);
 146
 147 void comphy_pcie_config_set(u32 comphy_max_count,
 148                             struct comphy_map *serdes_map);
 149 void comphy_pcie_config_detect(u32 comphy_max_count,
 150                                struct comphy_map *serdes_map);
 151 void comphy_pcie_unit_general_config(u32 pex_index);
 152
 153 #endif /* _COMPHY_H_ */
 154