2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _COMPHY_A3700_H_
8 #define _COMPHY_A3700_H_
11 #include "comphy_hpipe.h"
13 #define MVEBU_REG(offs) ((uintptr_t)MVEBU_REGISTER(offs))
15 #define DEFAULT_REFCLK_MHZ 25
16 #define PLL_SET_DELAY_US 600
17 #define PLL_LOCK_TIMEOUT 1000
18 #define POLL_16B_REG 1
19 #define POLL_32B_REG 0
22 * COMPHY SB definitions
24 #define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC)
25 #define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0))
27 #define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28)
28 #define rb_pin_pu_iveref BIT(1)
29 #define rb_pin_reset_core BIT(11)
30 #define rb_pin_reset_comphy BIT(12)
31 #define rb_pin_pu_pll BIT(16)
32 #define rb_pin_pu_rx BIT(17)
33 #define rb_pin_pu_tx BIT(18)
34 #define rb_pin_tx_idle BIT(19)
35 #define rf_gen_rx_sel_shift 22
36 #define rf_gen_rx_select (0xFF << rf_gen_rx_sel_shift)
37 #define rf_gen_tx_sel_shift 26
38 #define rf_gen_tx_select (0xFF << rf_gen_tx_sel_shift)
39 #define rb_phy_rx_init BIT(30)
41 #define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (lane) * 0x28)
42 #define rb_rx_init_done BIT(0)
43 #define rb_pll_ready_rx BIT(2)
44 #define rb_pll_ready_tx BIT(3)
47 * PCIe/USB/SGMII definitions
49 #define PCIE_BASE MVEBU_REG(0x070000)
50 #define PCIETOP_BASE MVEBU_REG(0x080000)
51 #define PCIE_RAMBASE MVEBU_REG(0x08C000)
52 #define PCIEPHY_BASE MVEBU_REG(0x01F000)
53 #define PCIEPHY_SHFT 2
55 #define USB32_BASE MVEBU_REG(0x050000) /* usb3 device */
56 #define USB32H_BASE MVEBU_REG(0x058000) /* usb3 host */
57 #define USB3PHY_BASE MVEBU_REG(0x05C000)
58 #define USB2PHY_BASE MVEBU_REG(0x05D000)
59 #define USB2PHY2_BASE MVEBU_REG(0x05F000)
60 #define USB32_CTRL_BASE MVEBU_REG(0x05D800)
61 #define USB3PHY_SHFT 2
63 #define SGMIIPHY_BASE(l) (l == 1 ? USB3PHY_BASE : PCIEPHY_BASE)
64 #define SGMIIPHY_ADDR(l, a) (((a & 0x00007FF) * 2) | SGMIIPHY_BASE(l))
66 #define phy_read16(l, a) read16((void __iomem *)SGMIIPHY_ADDR(l, a))
67 #define phy_write16(l, a, data, mask) \
68 reg_set16((void __iomem *)SGMIIPHY_ADDR(l, a), data, mask)
74 #define PHY_BASE(unit) ((unit == PCIE) ? PCIEPHY_BASE : USB3PHY_BASE)
75 #define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT)
77 /* bit definition for USB32_CTRL_BASE (USB32 Control Mode) */
78 #define usb32_ctrl_id_mode BIT(0)
79 #define usb32_ctrl_soft_id BIT(1)
80 #define usb32_ctrl_int_mode BIT(4)
83 #define PHY_PWR_PLL_CTRL_ADDR 0x01 /* for phy_read16 and phy_write16 */
84 #define PWR_PLL_CTRL_ADDR(unit) \
85 (PHY_PWR_PLL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
86 #define rf_phy_mode_shift 5
87 #define rf_phy_mode_mask (0x7 << rf_phy_mode_shift)
88 #define rf_ref_freq_sel_shift 0
89 #define rf_ref_freq_sel_mask (0x1F << rf_ref_freq_sel_shift)
90 #define PHY_MODE_SGMII 0x4
92 /* for phy_read16 and phy_write16 */
93 #define PHY_REG_KVCO_CAL_CTRL_ADDR 0x02
94 #define KVCO_CAL_CTRL_ADDR(unit) \
95 (PHY_REG_KVCO_CAL_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
96 #define rb_use_max_pll_rate BIT(12)
97 #define rb_force_calibration_done BIT(9)
99 /* for phy_read16 and phy_write16 */
100 #define PHY_DIG_LB_EN_ADDR 0x23
101 #define DIG_LB_EN_ADDR(unit) \
102 (PHY_DIG_LB_EN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
103 #define rf_data_width_shift 10
104 #define rf_data_width_mask (0x3 << rf_data_width_shift)
106 /* for phy_read16 and phy_write16 */
107 #define PHY_SYNC_PATTERN_ADDR 0x24
108 #define SYNC_PATTERN_ADDR(unit) \
109 (PHY_SYNC_PATTERN_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
110 #define phy_txd_inv BIT(10)
111 #define phy_rxd_inv BIT(11)
113 /* for phy_read16 and phy_write16 */
114 #define PHY_REG_UNIT_CTRL_ADDR 0x48
115 #define UNIT_CTRL_ADDR(unit) \
116 (PHY_REG_UNIT_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
117 #define rb_idle_sync_en BIT(12)
119 /* for phy_read16 and phy_write16 */
120 #define PHY_REG_GEN2_SETTINGS_2 0x3e
121 #define GEN2_SETTING_2_ADDR(unit) \
122 (PHY_REG_GEN2_SETTINGS_2 * PHY_SHFT(unit) + PHY_BASE(unit))
123 #define g2_tx_ssc_amp BIT(14)
125 /* for phy_read16 and phy_write16 */
126 #define PHY_REG_GEN2_SETTINGS_3 0x3f
127 #define GEN2_SETTING_3_ADDR(unit) \
128 (PHY_REG_GEN2_SETTINGS_3 * PHY_SHFT(unit) + PHY_BASE(unit))
130 /* for phy_read16 and phy_write16 */
131 #define PHY_MISC_REG0_ADDR 0x4f
132 #define MISC_REG0_ADDR(unit) \
133 (PHY_MISC_REG0_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
134 #define rb_clk100m_125m_en BIT(4)
135 #define rb_clk500m_en BIT(7)
136 #define rb_ref_clk_sel BIT(10)
138 /* for phy_read16 and phy_write16 */
139 #define PHY_REG_IFACE_REF_CLK_CTRL_ADDR 0x51
140 #define UNIT_IFACE_REF_CLK_CTRL_ADDR(unit) \
141 (PHY_REG_IFACE_REF_CLK_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
142 #define rb_ref1m_gen_div_force BIT(8)
143 #define rf_ref1m_gen_div_value_shift 0
144 #define rf_ref1m_gen_div_value_mask (0xFF << rf_ref1m_gen_div_value_shift)
146 /* for phy_read16 and phy_write16 */
147 #define PHY_REG_ERR_CNT_CONST_CTRL_ADDR 0x6A
148 #define UNIT_ERR_CNT_CONST_CTRL_ADDR(unit) \
149 (PHY_REG_ERR_CNT_CONST_CTRL_ADDR * PHY_SHFT(unit) + PHY_BASE(unit))
150 #define rb_fast_dfe_enable BIT(13)
152 #define MISC_REG1_ADDR(u) (0x73 * PHY_SHFT(u) + PHY_BASE(u))
153 #define bf_sel_bits_pcie_force BIT(15)
155 #define LANE_CFG0_ADDR(u) (0x180 * PHY_SHFT(u) + PHY_BASE(u))
156 #define bf_use_max_pll_rate BIT(9)
157 #define LANE_CFG1_ADDR(u) (0x181 * PHY_SHFT(u) + PHY_BASE(u))
158 #define bf_use_max_pll_rate BIT(9)
159 /* 0x5c310 = 0x93 (set BIT7) */
160 #define LANE_CFG4_ADDR(u) (0x188 * PHY_SHFT(u) + PHY_BASE(u))
161 #define bf_spread_spectrum_clock_en BIT(7)
163 #define LANE_STAT1_ADDR(u) (0x183 * PHY_SHFT(u) + PHY_BASE(u))
164 #define rb_txdclk_pclk_en BIT(0)
166 #define GLOB_PHY_CTRL0_ADDR(u) (0x1c1 * PHY_SHFT(u) + PHY_BASE(u))
167 #define bf_soft_rst BIT(0)
168 #define bf_mode_refdiv 0x30
169 #define rb_mode_core_clk_freq_sel BIT(9)
170 #define rb_mode_pipe_width_32 BIT(3)
172 #define TEST_MODE_CTRL_ADDR(u) (0x1c2 * PHY_SHFT(u) + PHY_BASE(u))
173 #define rb_mode_margin_override BIT(2)
175 #define GLOB_CLK_SRC_LO_ADDR(u) (0x1c3 * PHY_SHFT(u) + PHY_BASE(u))
176 #define bf_cfg_sel_20b BIT(15)
178 #define PWR_MGM_TIM1_ADDR(u) (0x1d0 * PHY_SHFT(u) + PHY_BASE(u))
180 #define PHY_REF_CLK_ADDR (0x4814 + PCIE_BASE)
182 #define USB3_CTRPUL_VAL_REG (0x20 + USB32_BASE)
183 #define USB3H_CTRPUL_VAL_REG (0x3454 + USB32H_BASE)
184 #define rb_usb3_ctr_100ns 0xff000000
186 #define USB2_OTG_PHY_CTRL_ADDR (0x820 + USB2PHY_BASE)
187 #define rb_usb2phy_suspm BIT(14)
188 #define rb_usb2phy_pu BIT(0)
190 #define USB2_PHY_OTG_CTRL_ADDR (0x34 + USB2PHY_BASE)
191 #define rb_pu_otg BIT(4)
193 #define USB2_PHY_CHRGR_DET_ADDR (0x38 + USB2PHY_BASE)
194 #define rb_cdp_en BIT(2)
195 #define rb_dcp_en BIT(3)
196 #define rb_pd_en BIT(4)
197 #define rb_pu_chrg_dtc BIT(5)
198 #define rb_cdp_dm_auto BIT(7)
199 #define rb_enswitch_dp BIT(12)
200 #define rb_enswitch_dm BIT(13)
202 #define USB2_CAL_CTRL_ADDR (0x8 + USB2PHY_BASE)
203 #define rb_usb2phy_pllcal_done BIT(31)
204 #define rb_usb2phy_impcal_done BIT(23)
206 #define USB2_PLL_CTRL0_ADDR (0x0 + USB2PHY_BASE)
207 #define rb_usb2phy_pll_ready BIT(31)
209 #define USB2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY_BASE)
210 #define rb_usb2phy_sqcal_done BIT(31)
212 #define USB2_PHY2_CTRL_ADDR (0x804 + USB2PHY2_BASE)
213 #define rb_usb2phy2_suspm BIT(7)
214 #define rb_usb2phy2_pu BIT(0)
215 #define USB2_PHY2_CAL_CTRL_ADDR (0x8 + USB2PHY2_BASE)
216 #define USB2_PHY2_PLL_CTRL0_ADDR (0x0 + USB2PHY2_BASE)
217 #define USB2_PHY2_RX_CHAN_CTRL1_ADDR (0x18 + USB2PHY2_BASE)
219 #define USB2_PHY_BASE(usb32) (usb32 == 0 ? USB2PHY2_BASE : USB2PHY_BASE)
220 #define USB2_PHY_CTRL_ADDR(usb32) \
221 (usb32 == 0 ? USB2_PHY2_CTRL_ADDR : USB2_OTG_PHY_CTRL_ADDR)
222 #define RB_USB2PHY_SUSPM(usb32) \
223 (usb32 == 0 ? rb_usb2phy2_suspm : rb_usb2phy_suspm)
224 #define RB_USB2PHY_PU(usb32) \
225 (usb32 == 0 ? rb_usb2phy2_pu : rb_usb2phy_pu)
226 #define USB2_PHY_CAL_CTRL_ADDR(usb32) \
227 (usb32 == 0 ? USB2_PHY2_CAL_CTRL_ADDR : USB2_CAL_CTRL_ADDR)
228 #define USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32) \
229 (usb32 == 0 ? USB2_PHY2_RX_CHAN_CTRL1_ADDR : USB2_RX_CHAN_CTRL1_ADDR)
230 #define USB2_PHY_PLL_CTRL0_ADDR(usb32) \
231 (usb32 == 0 ? USB2_PHY2_PLL_CTRL0_ADDR : USB2_PLL_CTRL0_ADDR)
236 #define AHCI_BASE MVEBU_REG(0xE0000)
238 #define rh_vsreg_addr (AHCI_BASE + 0x178)
239 #define rh_vsreg_data (AHCI_BASE + 0x17C)
240 #define rh_vs0_a (AHCI_BASE + 0xA0)
241 #define rh_vs0_d (AHCI_BASE + 0xA4)
243 #define vphy_sync_pattern_reg 0x224
244 #define bs_txd_inv BIT(10)
245 #define bs_rxd_inv BIT(11)
247 #define vphy_loopback_reg0 0x223
248 #define bs_phyintf_40bit 0x0C00
249 #define bs_pll_ready_tx 0x10
251 #define vphy_power_reg0 0x201
253 #define vphy_calctl_reg 0x202
254 #define bs_max_pll_rate BIT(12)
256 #define vphy_reserve_reg 0x0e
257 #define bs_phyctrl_frm_pin BIT(13)
259 #define vsata_ctrl_reg 0x00
260 #define bs_phy_pu_pll BIT(6)
263 * SDIO/eMMC definitions
265 #define SDIO_BASE MVEBU_REG(0xD8000)
267 #define SDIO_HOST_CTRL1_ADDR (SDIO_BASE + 0x28)
268 #define SDIO_SDHC_FIFO_ADDR (SDIO_BASE + 0x12C)
269 #define SDIO_CAP_12_ADDR (SDIO_BASE + 0x40)
270 #define SDIO_ENDIAN_ADDR (SDIO_BASE + 0x1A4)
271 #define SDIO_PHY_TIMING_ADDR (SDIO_BASE + 0x170)
272 #define SDIO_PHY_PAD_CTRL0_ADDR (SDIO_BASE + 0x178)
273 #define SDIO_DLL_RST_ADDR (SDIO_BASE + 0x148)
275 #endif /* _COMPHY_A3700_H_ */