git.sur5r.net Git - u-boot/blob - drivers/phy/marvell/utmi_phy.h

   1 /*
   2  * Copyright (C) 2015-2016 Marvell International Ltd.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _UTMI_PHY_H_
   8 #define _UTMI_PHY_H_
   9
  10 #define UTMI_USB_CFG_DEVICE_EN_OFFSET           0
  11 #define UTMI_USB_CFG_DEVICE_EN_MASK             \
  12         (0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET)
  13 #define UTMI_USB_CFG_DEVICE_MUX_OFFSET          1
  14 #define UTMI_USB_CFG_DEVICE_MUX_MASK            \
  15         (0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET)
  16 #define UTMI_USB_CFG_PLL_OFFSET                 25
  17 #define UTMI_USB_CFG_PLL_MASK                   \
  18         (0x1 << UTMI_USB_CFG_PLL_OFFSET)
  19
  20 #define UTMI_PHY_CFG_PU_OFFSET                  5
  21 #define UTMI_PHY_CFG_PU_MASK                    \
  22         (0x1 << UTMI_PHY_CFG_PU_OFFSET)
  23
  24 #define UTMI_PLL_CTRL_REG                       0x0
  25 #define UTMI_PLL_CTRL_REFDIV_OFFSET             0
  26 #define UTMI_PLL_CTRL_REFDIV_MASK               \
  27         (0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET)
  28 #define UTMI_PLL_CTRL_FBDIV_OFFSET              16
  29 #define UTMI_PLL_CTRL_FBDIV_MASK                \
  30         (0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET)
  31 #define UTMI_PLL_CTRL_SEL_LPFR_OFFSET           28
  32 #define UTMI_PLL_CTRL_SEL_LPFR_MASK             \
  33         (0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET)
  34 #define UTMI_PLL_CTRL_PLL_RDY_OFFSET            31
  35 #define UTMI_PLL_CTRL_PLL_RDY_MASK              \
  36         (0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET)
  37
  38 #define UTMI_CALIB_CTRL_REG                     0x8
  39 #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET       8
  40 #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK         \
  41         (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
  42 #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET      23
  43 #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK        \
  44         (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
  45 #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET      31
  46 #define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK        \
  47         (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
  48
  49 #define UTMI_TX_CH_CTRL_REG                     0xC
  50 #define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET        12
  51 #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK          \
  52         (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
  53 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET       16
  54 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK         \
  55         (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
  56
  57 #define UTMI_RX_CH_CTRL0_REG                    0x14
  58 #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET          15
  59 #define UTMI_RX_CH_CTRL0_SQ_DET_MASK            \
  60         (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
  61 #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET      28
  62 #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK        \
  63         (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
  64
  65 #define UTMI_RX_CH_CTRL1_REG                    0x18
  66 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET      0
  67 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK        \
  68         (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
  69 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET   3
  70 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK     \
  71         (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
  72
  73 #define UTMI_CTRL_STATUS0_REG                   0x24
  74 #define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET       22
  75 #define UTMI_CTRL_STATUS0_SUSPENDM_MASK         \
  76         (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
  77 #define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET       25
  78 #define UTMI_CTRL_STATUS0_TEST_SEL_MASK         \
  79         (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
  80
  81 #define UTMI_CHGDTC_CTRL_REG                    0x38
  82 #define UTMI_CHGDTC_CTRL_VDAT_OFFSET            8
  83 #define UTMI_CHGDTC_CTRL_VDAT_MASK              \
  84         (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
  85 #define UTMI_CHGDTC_CTRL_VSRC_OFFSET            10
  86 #define UTMI_CHGDTC_CTRL_VSRC_MASK              \
  87         (0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET)
  88
  89 #endif /* _UTMI_PHY_H_ */
  90