1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
10 #include <dm/pinctrl.h>
11 #include <mach/ar71xx_regs.h>
13 DECLARE_GLOBAL_DATA_PTR;
21 struct qca953x_pinctrl_priv {
25 static void pinctrl_qca953x_spi_config(struct qca953x_pinctrl_priv *priv, int cs)
29 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
30 QCA953X_GPIO(5) | QCA953X_GPIO(6) |
31 QCA953X_GPIO(7), QCA953X_GPIO(8));
33 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC1,
34 QCA953X_GPIO_MUX_MASK(8) |
35 QCA953X_GPIO_MUX_MASK(16) |
36 QCA953X_GPIO_MUX_MASK(24),
37 (QCA953X_GPIO_OUT_MUX_SPI_CS0 << 8) |
38 (QCA953X_GPIO_OUT_MUX_SPI_CLK << 16) |
39 (QCA953X_GPIO_OUT_MUX_SPI_MOSI << 24));
41 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
42 QCA953X_GPIO_MUX_MASK(0),
43 QCA953X_GPIO_IN_MUX_SPI_DATA_IN);
45 setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
51 static void pinctrl_qca953x_uart_config(struct qca953x_pinctrl_priv *priv, int uart_id)
55 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
56 QCA953X_GPIO(9), QCA953X_GPIO(10));
58 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC2,
59 QCA953X_GPIO_MUX_MASK(16),
60 QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16);
62 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
63 QCA953X_GPIO_MUX_MASK(8),
64 QCA953X_GPIO_IN_MUX_UART0_SIN << 8);
66 setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
72 static int qca953x_pinctrl_request(struct udevice *dev, int func, int flags)
74 struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
76 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
79 pinctrl_qca953x_spi_config(priv, flags);
82 pinctrl_qca953x_uart_config(priv, func);
91 static int qca953x_pinctrl_get_periph_id(struct udevice *dev,
92 struct udevice *periph)
97 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
98 "interrupts", cell, ARRAY_SIZE(cell));
104 return PERIPH_ID_UART0;
106 return PERIPH_ID_SPI0;
111 static int qca953x_pinctrl_set_state_simple(struct udevice *dev,
112 struct udevice *periph)
116 func = qca953x_pinctrl_get_periph_id(dev, periph);
119 return qca953x_pinctrl_request(dev, func, 0);
122 static struct pinctrl_ops qca953x_pinctrl_ops = {
123 .set_state_simple = qca953x_pinctrl_set_state_simple,
124 .request = qca953x_pinctrl_request,
125 .get_periph_id = qca953x_pinctrl_get_periph_id,
128 static int qca953x_pinctrl_probe(struct udevice *dev)
130 struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
133 addr = devfdt_get_addr(dev);
134 if (addr == FDT_ADDR_T_NONE)
137 priv->regs = map_physmem(addr,
143 static const struct udevice_id qca953x_pinctrl_ids[] = {
144 { .compatible = "qca,qca953x-pinctrl" },
148 U_BOOT_DRIVER(pinctrl_qca953x) = {
149 .name = "pinctrl_qca953x",
150 .id = UCLASS_PINCTRL,
151 .of_match = qca953x_pinctrl_ids,
152 .priv_auto_alloc_size = sizeof(struct qca953x_pinctrl_priv),
153 .ops = &qca953x_pinctrl_ops,
154 .probe = qca953x_pinctrl_probe,