2 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <dm/pinctrl.h>
12 #include <mach/ar71xx_regs.h>
14 DECLARE_GLOBAL_DATA_PTR;
22 struct qca953x_pinctrl_priv {
26 static void pinctrl_qca953x_spi_config(struct qca953x_pinctrl_priv *priv, int cs)
30 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
31 QCA953X_GPIO(5) | QCA953X_GPIO(6) |
32 QCA953X_GPIO(7), QCA953X_GPIO(8));
34 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC1,
35 QCA953X_GPIO_MUX_MASK(8) |
36 QCA953X_GPIO_MUX_MASK(16) |
37 QCA953X_GPIO_MUX_MASK(24),
38 (QCA953X_GPIO_OUT_MUX_SPI_CS0 << 8) |
39 (QCA953X_GPIO_OUT_MUX_SPI_CLK << 16) |
40 (QCA953X_GPIO_OUT_MUX_SPI_MOSI << 24));
42 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
43 QCA953X_GPIO_MUX_MASK(0),
44 QCA953X_GPIO_IN_MUX_SPI_DATA_IN);
46 setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
52 static void pinctrl_qca953x_uart_config(struct qca953x_pinctrl_priv *priv, int uart_id)
56 clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
57 QCA953X_GPIO(9), QCA953X_GPIO(10));
59 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_OUT_FUNC2,
60 QCA953X_GPIO_MUX_MASK(16),
61 QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16);
63 clrsetbits_be32(priv->regs + QCA953X_GPIO_REG_IN_ENABLE0,
64 QCA953X_GPIO_MUX_MASK(8),
65 QCA953X_GPIO_IN_MUX_UART0_SIN << 8);
67 setbits_be32(priv->regs + AR71XX_GPIO_REG_OUT,
73 static int qca953x_pinctrl_request(struct udevice *dev, int func, int flags)
75 struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
77 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
80 pinctrl_qca953x_spi_config(priv, flags);
83 pinctrl_qca953x_uart_config(priv, func);
92 static int qca953x_pinctrl_get_periph_id(struct udevice *dev,
93 struct udevice *periph)
98 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
99 "interrupts", cell, ARRAY_SIZE(cell));
105 return PERIPH_ID_UART0;
107 return PERIPH_ID_SPI0;
112 static int qca953x_pinctrl_set_state_simple(struct udevice *dev,
113 struct udevice *periph)
117 func = qca953x_pinctrl_get_periph_id(dev, periph);
120 return qca953x_pinctrl_request(dev, func, 0);
123 static struct pinctrl_ops qca953x_pinctrl_ops = {
124 .set_state_simple = qca953x_pinctrl_set_state_simple,
125 .request = qca953x_pinctrl_request,
126 .get_periph_id = qca953x_pinctrl_get_periph_id,
129 static int qca953x_pinctrl_probe(struct udevice *dev)
131 struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
134 addr = dev_get_addr(dev);
135 if (addr == FDT_ADDR_T_NONE)
138 priv->regs = map_physmem(addr,
144 static const struct udevice_id qca953x_pinctrl_ids[] = {
145 { .compatible = "qca,qca953x-pinctrl" },
149 U_BOOT_DRIVER(pinctrl_qca953x) = {
150 .name = "pinctrl_qca953x",
151 .id = UCLASS_PINCTRL,
152 .of_match = qca953x_pinctrl_ids,
153 .priv_auto_alloc_size = sizeof(struct qca953x_pinctrl_priv),
154 .ops = &qca953x_pinctrl_ops,
155 .probe = qca953x_pinctrl_probe,