1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
11 #include <dm/pinctrl.h>
13 #include "pinctrl-imx.h"
15 DECLARE_GLOBAL_DATA_PTR;
17 static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
19 struct imx_pinctrl_priv *priv = dev_get_priv(dev);
20 struct imx_pinctrl_soc_info *info = priv->info;
21 int node = dev_of_offset(config);
22 const struct fdt_property *prop;
24 int npins, size, pin_size;
25 int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
26 u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
29 dev_dbg(dev, "%s: %s\n", __func__, config->name);
31 if (info->flags & SHARE_MUX_CONF_REG)
32 pin_size = SHARE_FSL_PIN_SIZE;
34 pin_size = FSL_PIN_SIZE;
36 prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
38 dev_err(dev, "No fsl,pins property in node %s\n", config->name);
42 if (!size || size % pin_size) {
43 dev_err(dev, "Invalid fsl,pins property in node %s\n",
48 pin_data = devm_kzalloc(dev, size, 0);
52 if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
53 pin_data, size >> 2)) {
54 dev_err(dev, "Error reading pin data.\n");
55 devm_kfree(dev, pin_data);
59 npins = size / pin_size;
62 * Refer to linux documentation for details:
63 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
65 for (i = 0; i < npins; i++) {
66 mux_reg = pin_data[j++];
68 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
71 if (info->flags & SHARE_MUX_CONF_REG) {
74 conf_reg = pin_data[j++];
75 if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
79 if ((mux_reg == -1) || (conf_reg == -1)) {
80 dev_err(dev, "Error mux_reg or conf_reg\n");
81 devm_kfree(dev, pin_data);
85 input_reg = pin_data[j++];
86 mux_mode = pin_data[j++];
87 input_val = pin_data[j++];
88 config_val = pin_data[j++];
90 dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
91 "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
92 mux_reg, conf_reg, input_reg, mux_mode, input_val,
95 if (config_val & IMX_PAD_SION)
96 mux_mode |= IOMUXC_CONFIG_SION;
98 config_val &= ~IMX_PAD_SION;
101 if (info->flags & SHARE_MUX_CONF_REG) {
102 clrsetbits_le32(info->base + mux_reg, info->mux_mask,
103 mux_mode << mux_shift);
105 writel(mux_mode, info->base + mux_reg);
108 dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
114 * If the select input value begins with 0xff, it's a quirky
115 * select input and the value should be interpreted as below.
117 * | 0xff | shift | width | select |
118 * It's used to work around the problem that the select
119 * input for some pin is not implemented in the select
120 * input register but in some general purpose register.
121 * We encode the select input value, width and shift of
122 * the bit field into input_val cell of pin function ID
123 * in device tree, and then decode them here for setting
124 * up the select input bits in general purpose register.
127 if (input_val >> 24 == 0xff) {
129 u8 select = val & 0xff;
130 u8 width = (val >> 8) & 0xff;
131 u8 shift = (val >> 16) & 0xff;
132 u32 mask = ((1 << width) - 1) << shift;
134 * The input_reg[i] here is actually some IOMUXC general
135 * purpose register, not regular select input register.
137 val = readl(info->base + input_reg);
139 val |= select << shift;
140 writel(val, info->base + input_reg);
141 } else if (input_reg) {
143 * Regular select input register can never be at offset
144 * 0, and we only print register value for regular case.
146 if (info->input_sel_base)
147 writel(input_val, info->input_sel_base +
150 writel(input_val, info->base + input_reg);
152 dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
153 input_reg, input_val);
157 if (!(config_val & IMX_NO_PAD_CTL)) {
158 if (info->flags & SHARE_MUX_CONF_REG) {
159 clrsetbits_le32(info->base + conf_reg,
160 ~info->mux_mask, config_val);
162 writel(config_val, info->base + conf_reg);
165 dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
166 conf_reg, config_val);
170 devm_kfree(dev, pin_data);
175 const struct pinctrl_ops imx_pinctrl_ops = {
176 .set_state = imx_pinctrl_set_state,
179 int imx_pinctrl_probe(struct udevice *dev,
180 struct imx_pinctrl_soc_info *info)
182 struct imx_pinctrl_priv *priv = dev_get_priv(dev);
183 int node = dev_of_offset(dev), ret;
184 struct fdtdec_phandle_args arg;
189 dev_err(dev, "wrong pinctrl info\n");
196 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
199 if (addr == FDT_ADDR_T_NONE)
202 info->base = map_sysmem(addr, size);
207 info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
209 * Refer to linux documentation for details:
210 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
212 if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
213 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
214 node, "fsl,input-sel",
217 dev_err(dev, "iomuxc fsl,input-sel property not found\n");
221 addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
223 if (addr == FDT_ADDR_T_NONE)
226 info->input_sel_base = map_sysmem(addr, size);
227 if (!info->input_sel_base)
231 dev_dbg(dev, "initialized IMX pinctrl driver\n");
236 int imx_pinctrl_remove(struct udevice *dev)
238 struct imx_pinctrl_priv *priv = dev_get_priv(dev);
239 struct imx_pinctrl_soc_info *info = priv->info;
241 if (info->input_sel_base)
242 unmap_sysmem(info->input_sel_base);
244 unmap_sysmem(info->base);