git.sur5r.net Git - u-boot/blob - drivers/pinctrl/nxp/pinctrl-imx.c

   1 /*
   2  * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <mapmem.h>
   9 #include <linux/io.h>
  10 #include <linux/err.h>
  11 #include <dm/device.h>
  12 #include <dm/pinctrl.h>
  13
  14 #include "pinctrl-imx.h"
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  19 {
  20         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  21         struct imx_pinctrl_soc_info *info = priv->info;
  22         int node = config->of_offset;
  23         const struct fdt_property *prop;
  24         u32 *pin_data;
  25         int npins, size, pin_size;
  26         int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
  27         int i, j = 0;
  28
  29         dev_dbg(dev, "%s: %s\n", __func__, config->name);
  30
  31         if (info->flags & SHARE_MUX_CONF_REG)
  32                 pin_size = SHARE_FSL_PIN_SIZE;
  33         else
  34                 pin_size = FSL_PIN_SIZE;
  35
  36         prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
  37         if (!prop) {
  38                 dev_err(dev, "No fsl,pins property in node %s\n", config->name);
  39                 return -EINVAL;
  40         }
  41
  42         if (!size || size % pin_size) {
  43                 dev_err(dev, "Invalid fsl,pins property in node %s\n",
  44                         config->name);
  45                 return -EINVAL;
  46         }
  47
  48         pin_data = devm_kzalloc(dev, size, 0);
  49         if (!pin_data)
  50                 return -ENOMEM;
  51
  52         if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
  53                                  pin_data, size >> 2)) {
  54                 dev_err(dev, "Error reading pin data.\n");
  55                 return -EINVAL;
  56         }
  57
  58         npins = size / pin_size;
  59
  60         /*
  61          * Refer to linux documentation for details:
  62          * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
  63          */
  64         for (i = 0; i < npins; i++) {
  65                 mux_reg = pin_data[j++];
  66
  67                 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
  68                         mux_reg = -1;
  69
  70                 if (info->flags & SHARE_MUX_CONF_REG) {
  71                         conf_reg = mux_reg;
  72                 } else {
  73                         conf_reg = pin_data[j++];
  74                         if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
  75                                 conf_reg = -1;
  76                 }
  77
  78                 if ((mux_reg == -1) || (conf_reg == -1)) {
  79                         dev_err(dev, "Error mux_reg or conf_reg\n");
  80                         return -EINVAL;
  81                 }
  82
  83                 input_reg = pin_data[j++];
  84                 mux_mode = pin_data[j++];
  85                 input_val = pin_data[j++];
  86                 config_val = pin_data[j++];
  87
  88                 dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
  89                         "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
  90                         mux_reg, conf_reg, input_reg, mux_mode, input_val,
  91                         config_val);
  92
  93                 if (config_val & IMX_PAD_SION)
  94                         mux_mode |= IOMUXC_CONFIG_SION;
  95
  96                 config_val &= ~IMX_PAD_SION;
  97
  98                 /* Set Mux */
  99                 if (info->flags & SHARE_MUX_CONF_REG) {
 100                         clrsetbits_le32(info->base + mux_reg, 0x7 << 20,
 101                                         mux_mode << 20);
 102                 } else {
 103                         writel(mux_mode, info->base + mux_reg);
 104                 }
 105
 106                 dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
 107                         mux_mode);
 108
 109                 /*
 110                  * Set select input
 111                  *
 112                  * If the select input value begins with 0xff, it's a quirky
 113                  * select input and the value should be interpreted as below.
 114                  *     31     23      15      7        0
 115                  *     | 0xff | shift | width | select |
 116                  * It's used to work around the problem that the select
 117                  * input for some pin is not implemented in the select
 118                  * input register but in some general purpose register.
 119                  * We encode the select input value, width and shift of
 120                  * the bit field into input_val cell of pin function ID
 121                  * in device tree, and then decode them here for setting
 122                  * up the select input bits in general purpose register.
 123                  */
 124
 125                 if (input_val >> 24 == 0xff) {
 126                         u32 val = input_val;
 127                         u8 select = val & 0xff;
 128                         u8 width = (val >> 8) & 0xff;
 129                         u8 shift = (val >> 16) & 0xff;
 130                         u32 mask = ((1 << width) - 1) << shift;
 131                         /*
 132                          * The input_reg[i] here is actually some IOMUXC general
 133                          * purpose register, not regular select input register.
 134                          */
 135                         val = readl(info->base + input_reg);
 136                         val &= ~mask;
 137                         val |= select << shift;
 138                         writel(val, info->base + input_reg);
 139                 } else if (input_reg) {
 140                         /*
 141                          * Regular select input register can never be at offset
 142                          * 0, and we only print register value for regular case.
 143                          */
 144                         if (info->input_sel_base)
 145                                 writel(input_val, info->input_sel_base +
 146                                        input_reg);
 147                         else
 148                                 writel(input_val, info->base + input_reg);
 149
 150                         dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
 151                                 input_reg, input_val);
 152                 }
 153
 154                 /* Set config */
 155                 if (!(config_val & IMX_NO_PAD_CTL)) {
 156                         if (info->flags & SHARE_MUX_CONF_REG) {
 157                                 clrsetbits_le32(info->base + conf_reg, 0xffff,
 158                                                 config_val);
 159                         } else {
 160                                 writel(config_val, info->base + conf_reg);
 161                         }
 162
 163                         dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
 164                                 conf_reg, config_val);
 165                 }
 166         }
 167
 168         return 0;
 169 }
 170
 171 const struct pinctrl_ops imx_pinctrl_ops  = {
 172         .set_state = imx_pinctrl_set_state,
 173 };
 174
 175 int imx_pinctrl_probe(struct udevice *dev,
 176                       struct imx_pinctrl_soc_info *info)
 177 {
 178         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 179         int node = dev->of_offset, ret;
 180         struct fdtdec_phandle_args arg;
 181         fdt_addr_t addr;
 182         fdt_size_t size;
 183
 184         if (!info) {
 185                 dev_err(dev, "wrong pinctrl info\n");
 186                 return -EINVAL;
 187         }
 188
 189         priv->dev = dev;
 190         priv->info = info;
 191
 192         addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
 193
 194         if (addr == FDT_ADDR_T_NONE)
 195                 return -EINVAL;
 196
 197         info->base = map_sysmem(addr, size);
 198         if (!info->base)
 199                 return -ENOMEM;
 200         priv->info = info;
 201
 202         /*
 203          * Refer to linux documentation for details:
 204          * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
 205          */
 206         if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
 207                 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
 208                                                      node, "fsl,input-sel",
 209                                                      NULL, 0, 0, &arg);
 210                 if (ret) {
 211                         dev_err(dev, "iomuxc fsl,input-sel property not found\n");
 212                         return -EINVAL;
 213                 }
 214
 215                 addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
 216                                             &size);
 217                 if (addr == FDT_ADDR_T_NONE)
 218                         return -EINVAL;
 219
 220                 info->input_sel_base = map_sysmem(addr, size);
 221                 if (!info->input_sel_base)
 222                         return -ENOMEM;
 223         }
 224
 225         dev_info(dev, "initialized IMX pinctrl driver\n");
 226
 227         return 0;
 228 }
 229
 230 int imx_pinctrl_remove(struct udevice *dev)
 231 {
 232         struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 233         struct imx_pinctrl_soc_info *info = priv->info;
 234
 235         if (info->input_sel_base)
 236                 unmap_sysmem(info->input_sel_base);
 237         if (info->base)
 238                 unmap_sysmem(info->base);
 239
 240         return 0;
 241 }