1 // SPDX-License-Identifier: GPL-2.0
3 * R8A7790 processor support
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 * Copyright (C) 2012 Renesas Solutions Corp.
8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 #include <dm/pinctrl.h>
15 #include <linux/kernel.h>
20 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
21 * which case they support both 3.3V and 1.8V signalling.
23 #define CPU_ALL_PORT(fn, sfx) \
24 PORT_GP_32(0, fn, sfx), \
25 PORT_GP_30(1, fn, sfx), \
26 PORT_GP_30(2, fn, sfx), \
27 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_32(4, fn, sfx), \
29 PORT_GP_32(5, fn, sfx)
38 PINMUX_FUNCTION_BEGIN,
42 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
43 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
44 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
45 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
46 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
47 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
48 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
49 FN_IP3_14_12, FN_IP3_17_15,
52 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
53 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
54 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
55 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
56 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
57 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
58 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
61 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
62 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
63 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
64 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
65 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
66 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
67 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
70 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
71 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
72 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
73 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
74 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
75 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
76 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
79 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
80 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
81 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
82 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
83 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
84 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
85 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
86 FN_IP14_15_12, FN_IP14_18_16,
89 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
90 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
91 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
92 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
93 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
94 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
95 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
98 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
99 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
100 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
101 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
102 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
103 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
104 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
105 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
106 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
107 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
108 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
109 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
110 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
111 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
114 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
115 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
116 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
117 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
118 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
119 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
120 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
121 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
122 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
123 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
124 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
125 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
126 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
127 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
128 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
131 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
132 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
133 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
134 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
135 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
136 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
137 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
138 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
139 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
140 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
141 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
144 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
145 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
146 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
147 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
148 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
149 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
150 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
151 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
152 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
153 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
154 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
155 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
156 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
159 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
160 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
161 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
162 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
163 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
164 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
165 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
166 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
167 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
168 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
169 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
170 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
171 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
172 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
173 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
176 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
177 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
178 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
179 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
180 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
181 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
182 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
183 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
184 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
185 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
186 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
187 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
188 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
189 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
190 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
191 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
192 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
193 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
197 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
198 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
199 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
200 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
201 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
202 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
203 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
204 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
205 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
206 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
207 FN_I2C2_SCL_E, FN_ETH_RX_ER,
208 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
209 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
210 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
211 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
212 FN_HRX0_E, FN_STP_ISSYNC_0_B,
213 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
214 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
215 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
216 FN_ETH_REF_CLK, FN_HCTS0_N_E,
217 FN_STP_IVCXO27_1_B, FN_HRX0_F,
220 FN_ETH_MDIO, FN_HRTS0_N_E,
221 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
222 FN_HTX0_F, FN_BPFCLK_G,
223 FN_ETH_TX_EN, FN_SIM0_CLK_C,
224 FN_HRTS0_N_F, FN_ETH_MAGIC,
225 FN_SIM0_RST_C, FN_ETH_TXD0,
226 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
227 FN_ETH_MDC, FN_STP_ISD_1_B,
228 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
229 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
230 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
231 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
232 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
233 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
234 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
235 FN_ATACS00_N, FN_AVB_RXD1,
236 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
239 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
240 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
241 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
242 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
243 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
244 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
245 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
246 FN_VI1_CLK, FN_AVB_RX_DV,
247 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
248 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
249 FN_SCIFA1_RXD_D, FN_AVB_MDC,
250 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
251 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
252 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
253 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
254 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
255 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
256 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
259 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
260 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
261 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
262 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
263 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
264 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
265 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
266 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
267 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
268 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
269 FN_AVB_TX_EN, FN_SD1_CMD,
270 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
271 FN_SD1_DAT0, FN_AVB_TX_CLK,
272 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
273 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
274 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
275 FN_SD1_DAT3, FN_AVB_RXD0,
276 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
277 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
278 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
282 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
283 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
284 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
285 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
286 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
287 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
288 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
289 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
290 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
291 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
292 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
293 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
294 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
295 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
296 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
297 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
298 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
299 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
300 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
301 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
302 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
303 FN_GLO_I0_B, FN_VI3_DATA6_B,
306 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
307 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
308 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
309 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
310 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
311 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
312 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
313 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
314 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
315 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
316 FN_FMIN_E, FN_FMIN_F,
317 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
318 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
319 FN_I2C2_SDA_B, FN_MLB_DAT,
320 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
321 FN_SSI_SCK0129, FN_CAN_CLK_B,
325 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
326 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
327 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
328 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
329 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
330 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
331 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
332 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
333 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
334 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
335 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
336 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
337 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
338 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
339 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
340 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
341 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
342 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
346 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
347 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
348 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
349 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
350 FN_BPFCLK_F, FN_SSI_WS6,
351 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
352 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
353 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
354 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
355 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
356 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
357 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
358 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
359 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
360 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
361 FN_BPFCLK_E, FN_SSI_SDATA7_B,
362 FN_FMIN_G, FN_SSI_SDATA8,
363 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
364 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
365 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
366 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
367 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
370 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
371 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
372 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
373 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
374 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
375 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
376 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
377 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
378 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
379 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
380 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
381 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
382 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
383 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
384 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
385 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
386 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
387 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
391 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
392 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
393 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
394 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
395 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
396 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
397 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
398 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
399 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
400 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
401 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
402 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
403 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
404 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
405 FN_DU2_DG6, FN_LCDOUT14,
408 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
409 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
410 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
411 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
412 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
415 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
417 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
418 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
419 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
421 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
422 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
423 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
424 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
425 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
426 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
427 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
428 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
429 FN_SEL_VI3_0, FN_SEL_VI3_1,
430 FN_SEL_VI2_0, FN_SEL_VI2_1,
431 FN_SEL_VI1_0, FN_SEL_VI1_1,
432 FN_SEL_VI0_0, FN_SEL_VI0_1,
433 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
434 FN_SEL_LBS_0, FN_SEL_LBS_1,
435 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
436 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
437 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
439 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
440 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
441 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
442 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
443 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
444 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
445 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
446 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
447 FN_SEL_ADI_0, FN_SEL_ADI_1,
448 FN_SEL_SSP_0, FN_SEL_SSP_1,
449 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
450 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
451 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
452 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
453 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
454 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
455 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
457 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
458 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
459 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
460 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
462 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
463 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
465 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
470 VI1_DATA7_VI1_B7_MARK,
472 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
473 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
474 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
476 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
477 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
478 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
479 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
480 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
481 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
482 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
483 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
484 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
485 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
486 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
487 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
488 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
489 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
491 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
492 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
493 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
494 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
495 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
496 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
497 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
498 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
499 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
500 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
501 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
502 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
503 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
504 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
505 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
507 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
508 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
509 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
510 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
511 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
512 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
513 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
514 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
515 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
516 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
517 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
519 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
520 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
521 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
522 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
523 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
524 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
525 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
526 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
527 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
528 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
529 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
530 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
531 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
533 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
534 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
535 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
536 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
537 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
538 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
539 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
540 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
541 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
542 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
543 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
544 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
545 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
546 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
547 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
549 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
550 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
551 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
552 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
553 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
554 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
555 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
556 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
557 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
558 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
559 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
560 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
561 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
562 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
563 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
564 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
565 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
566 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
567 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
570 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
571 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
572 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
573 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
574 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
575 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
576 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
577 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
578 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
579 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
580 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
581 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
582 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
583 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
584 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
585 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
586 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
587 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
588 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
589 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
590 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
592 ETH_MDIO_MARK, HRTS0_N_E_MARK,
593 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
594 HTX0_F_MARK, BPFCLK_G_MARK,
595 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
596 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
597 SIM0_RST_C_MARK, ETH_TXD0_MARK,
598 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
599 ETH_MDC_MARK, STP_ISD_1_B_MARK,
600 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
601 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
602 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
603 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
604 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
605 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
606 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
607 ATACS00_N_MARK, AVB_RXD1_MARK,
608 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
610 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
611 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
612 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
613 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
614 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
615 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
616 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
617 VI1_CLK_MARK, AVB_RX_DV_MARK,
618 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
619 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
620 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
621 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
622 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
623 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
624 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
625 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
626 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
627 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
629 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
630 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
631 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
632 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
633 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
634 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
635 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
636 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
637 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
638 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
639 AVB_TX_EN_MARK, SD1_CMD_MARK,
640 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
641 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
642 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
643 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
644 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
645 SD1_DAT3_MARK, AVB_RXD0_MARK,
646 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
647 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
648 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
651 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
652 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
653 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
654 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
655 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
656 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
657 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
658 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
659 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
660 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
661 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
662 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
663 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
664 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
665 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
666 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
667 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
668 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
669 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
670 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
671 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
672 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
674 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
675 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
676 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
677 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
678 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
679 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
680 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
681 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
682 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
683 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
684 FMIN_E_MARK, FMIN_F_MARK,
685 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
686 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
687 I2C2_SDA_B_MARK, MLB_DAT_MARK,
688 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
689 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
692 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
693 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
694 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
695 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
696 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
697 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
698 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
699 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
700 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
701 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
702 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
703 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
704 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
705 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
706 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
707 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
708 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
709 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
712 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
713 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
714 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
715 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
716 BPFCLK_F_MARK, SSI_WS6_MARK,
717 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
718 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
719 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
720 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
721 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
722 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
723 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
724 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
725 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
726 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
727 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
728 FMIN_G_MARK, SSI_SDATA8_MARK,
729 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
730 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
731 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
732 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
733 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
735 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
736 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
737 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
738 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
739 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
740 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
741 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
742 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
743 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
744 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
745 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
746 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
747 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
748 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
749 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
750 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
751 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
752 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
755 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
756 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
757 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
758 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
759 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
760 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
761 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
762 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
763 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
764 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
765 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
766 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
767 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
768 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
769 DU2_DG6_MARK, LCDOUT14_MARK,
771 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
772 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
773 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
774 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
775 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
778 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
779 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
783 static const u16 pinmux_data[] = {
784 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
786 PINMUX_SINGLE(VI1_DATA7_VI1_B7),
787 PINMUX_SINGLE(USB0_PWEN),
788 PINMUX_SINGLE(USB0_OVC_VBUS),
789 PINMUX_SINGLE(USB2_PWEN),
790 PINMUX_SINGLE(USB2_OVC),
793 PINMUX_SINGLE(DU_DOTCLKIN0),
794 PINMUX_SINGLE(DU_DOTCLKIN2),
796 PINMUX_IPSR_GPSR(IP0_2_0, D0),
797 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
798 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
799 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
800 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
801 PINMUX_IPSR_GPSR(IP0_5_3, D1),
802 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
803 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
804 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
805 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
806 PINMUX_IPSR_GPSR(IP0_8_6, D2),
807 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
808 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
809 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
810 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
811 PINMUX_IPSR_GPSR(IP0_11_9, D3),
812 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
813 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
814 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
815 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
816 PINMUX_IPSR_GPSR(IP0_15_12, D4),
817 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
818 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
819 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
820 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
821 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
822 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
823 PINMUX_IPSR_GPSR(IP0_19_16, D5),
824 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
825 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
826 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
827 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
828 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
829 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
830 PINMUX_IPSR_GPSR(IP0_22_20, D6),
831 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
832 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
833 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
834 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
835 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
836 PINMUX_IPSR_GPSR(IP0_26_23, D7),
837 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
838 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
839 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
840 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
841 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
842 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
843 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
844 PINMUX_IPSR_GPSR(IP0_30_27, D8),
845 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
846 PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
847 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
848 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
849 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
851 PINMUX_IPSR_GPSR(IP1_3_0, D9),
852 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
853 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
854 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
855 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
856 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
857 PINMUX_IPSR_GPSR(IP1_7_4, D10),
858 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
859 PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
860 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
861 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
862 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
863 PINMUX_IPSR_GPSR(IP1_11_8, D11),
864 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
865 PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
866 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
867 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
868 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
869 PINMUX_IPSR_GPSR(IP1_14_12, D12),
870 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
871 PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
872 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
873 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
874 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
875 PINMUX_IPSR_GPSR(IP1_17_15, D13),
876 PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
877 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
878 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
879 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
880 PINMUX_IPSR_GPSR(IP1_21_18, D14),
881 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
882 PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
883 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
884 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
885 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
886 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
887 PINMUX_IPSR_GPSR(IP1_25_22, D15),
888 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
889 PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
890 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
891 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
892 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
893 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
894 PINMUX_IPSR_GPSR(IP1_27_26, A0),
895 PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
896 PINMUX_IPSR_GPSR(IP1_29_28, A1),
897 PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
899 PINMUX_IPSR_GPSR(IP2_2_0, A2),
900 PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
901 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
902 PINMUX_IPSR_GPSR(IP2_5_3, A3),
903 PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
904 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
905 PINMUX_IPSR_GPSR(IP2_8_6, A4),
906 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
907 PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
908 PINMUX_IPSR_GPSR(IP2_11_9, A5),
909 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
910 PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
911 PINMUX_IPSR_GPSR(IP2_14_12, A6),
912 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
913 PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
914 PINMUX_IPSR_GPSR(IP2_17_15, A7),
915 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
916 PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
917 PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
918 PINMUX_IPSR_GPSR(IP2_21_18, A8),
919 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
920 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
921 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
922 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
923 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
924 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
925 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
926 PINMUX_IPSR_GPSR(IP2_25_22, A9),
927 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
928 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
929 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
930 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
931 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
932 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
933 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
934 PINMUX_IPSR_GPSR(IP2_28_26, A10),
935 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
936 PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
937 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
938 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
939 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
941 PINMUX_IPSR_GPSR(IP3_3_0, A11),
942 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
943 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
944 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
945 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
946 PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
947 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
948 PINMUX_IPSR_GPSR(IP3_7_4, A12),
949 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
950 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
951 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
952 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
953 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
954 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
955 PINMUX_IPSR_GPSR(IP3_11_8, A13),
956 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
957 PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
958 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
959 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
960 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
961 PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
962 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
963 PINMUX_IPSR_GPSR(IP3_14_12, A14),
964 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
965 PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
966 PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
967 PINMUX_IPSR_GPSR(IP3_17_15, A15),
968 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
969 PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
970 PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
971 PINMUX_IPSR_GPSR(IP3_19_18, A16),
972 PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
973 PINMUX_IPSR_GPSR(IP3_22_20, A17),
974 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
975 PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
976 PINMUX_IPSR_GPSR(IP3_25_23, A18),
977 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
978 PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
979 PINMUX_IPSR_GPSR(IP3_28_26, A19),
980 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
981 PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
982 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
983 PINMUX_IPSR_GPSR(IP3_31_29, A20),
984 PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
985 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
986 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
987 PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
989 PINMUX_IPSR_GPSR(IP4_2_0, A21),
990 PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
991 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
992 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
993 PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
994 PINMUX_IPSR_GPSR(IP4_5_3, A22),
995 PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
996 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
997 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
998 PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
999 PINMUX_IPSR_GPSR(IP4_8_6, A23),
1000 PINMUX_IPSR_GPSR(IP4_8_6, IO2),
1001 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1002 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1003 PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
1004 PINMUX_IPSR_GPSR(IP4_11_9, A24),
1005 PINMUX_IPSR_GPSR(IP4_11_9, IO3),
1006 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1007 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1008 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1009 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1010 PINMUX_IPSR_GPSR(IP4_14_12, A25),
1011 PINMUX_IPSR_GPSR(IP4_14_12, SSL),
1012 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1013 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1014 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1015 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1016 PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
1017 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1018 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1019 PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
1020 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1021 PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
1022 PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
1023 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1024 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1025 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1026 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1027 PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
1028 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1029 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1030 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1031 PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
1032 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1033 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1034 PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
1035 PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
1036 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1037 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1038 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1039 PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
1040 PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
1041 PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
1042 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1043 PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
1044 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1045 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1046 PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
1048 PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
1049 PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
1050 PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
1051 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1052 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1053 PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
1054 PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
1055 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1056 PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
1057 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1058 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1059 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1060 PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
1061 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1062 PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
1063 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1064 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1065 PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
1066 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1067 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1068 PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
1069 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1070 PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
1071 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1072 PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
1073 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1074 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1075 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1076 PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
1077 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1078 PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
1079 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1080 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1081 PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
1082 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1083 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1084 PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
1085 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1086 PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
1087 PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
1088 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1089 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1090 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1091 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1092 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1093 PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
1094 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1095 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1096 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1097 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1098 PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
1099 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1100 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1101 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1102 PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1103 PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
1104 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1105 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1106 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1107 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1108 PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
1109 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1110 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1111 PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
1112 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1113 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1115 PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
1116 PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1117 PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
1118 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1119 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1120 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1121 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1122 PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
1123 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1124 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1125 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1126 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1127 PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
1128 PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1129 PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
1130 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1131 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1132 PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
1133 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1134 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1135 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1136 PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
1137 PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1138 PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
1139 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1140 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1141 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1142 PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
1143 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1144 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1145 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1146 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1147 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1148 PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
1149 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1150 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1151 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1152 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1153 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1154 PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
1155 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1156 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1157 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1158 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1159 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1160 PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
1161 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1162 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1163 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1164 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1165 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1166 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1167 PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
1168 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1169 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1170 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1171 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1172 PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
1173 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1174 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1175 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1177 PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
1178 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1179 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1180 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1181 PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
1182 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1183 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1184 PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
1185 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1186 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1187 PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
1188 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1189 PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
1190 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1191 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1192 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1193 PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
1194 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1195 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1196 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1197 PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
1198 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1199 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1200 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1201 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1202 PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
1203 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1204 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1205 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1206 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1207 PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
1208 PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
1209 PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
1210 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1211 PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
1212 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1213 PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
1214 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
1215 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
1216 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1217 PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
1218 PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
1219 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1220 PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
1221 PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
1223 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1224 PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
1225 PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
1226 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1227 PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
1228 PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
1229 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1230 PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
1231 PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
1232 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1233 PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
1234 PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
1235 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1236 PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
1237 PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
1238 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1239 PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
1240 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1241 PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
1242 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1243 PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
1244 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1245 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1246 PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
1247 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1248 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1249 PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
1250 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1251 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1252 PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
1253 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1254 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1255 PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
1256 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1257 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1258 PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
1259 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1260 PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
1261 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1262 PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
1263 PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
1264 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1265 PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
1266 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1267 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1269 PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
1270 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1271 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1272 PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
1273 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1274 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1275 PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
1276 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1277 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1278 PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
1279 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1280 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1281 PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
1282 PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
1283 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1284 PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
1285 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1286 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1287 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1288 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1289 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1290 PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
1291 PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
1292 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1293 PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
1294 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1295 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1296 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1297 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1298 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1299 PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
1300 PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
1301 PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
1302 PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
1303 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1304 PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
1305 PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
1306 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1307 PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
1308 PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
1309 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1310 PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
1311 PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
1312 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1313 PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
1314 PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
1315 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1316 PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
1317 PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
1318 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1319 PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
1320 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1321 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1322 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1323 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1324 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1325 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1327 PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
1328 PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
1329 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1330 PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
1331 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1332 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1333 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1334 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1335 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1336 PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
1337 PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
1338 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1339 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1340 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1341 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1342 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1343 PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
1344 PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
1345 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1346 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1347 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1348 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1349 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1350 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1351 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1352 PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
1353 PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
1354 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1355 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1356 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1357 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1358 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1359 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1360 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1361 PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
1362 PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
1363 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1364 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1365 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1366 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1367 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1368 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1369 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1370 PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
1371 PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
1372 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1373 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1374 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1375 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1376 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1377 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1378 PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
1379 PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
1380 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1381 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1382 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1383 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1384 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1385 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1386 PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
1387 PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
1388 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1389 PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
1390 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1391 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1392 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1393 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1394 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1395 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1397 PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
1398 PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
1399 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1400 PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
1401 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1402 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1403 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1404 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1405 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1406 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1407 PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
1408 PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
1409 PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
1410 PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
1411 PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
1412 PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
1413 PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
1414 PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
1415 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
1416 PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
1417 PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
1418 PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
1419 PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
1420 PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
1421 PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
1422 PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
1423 PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
1424 PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
1425 PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
1426 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1427 PINMUX_IPSR_GPSR(IP11_17_15, VSP),
1428 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1429 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1430 PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
1431 PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
1432 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1433 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1434 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1435 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1436 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1437 PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
1438 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1439 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1440 PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
1441 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1442 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1443 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1444 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1445 PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
1446 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1447 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1448 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1449 PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
1450 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1451 PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
1453 PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
1454 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1455 PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
1456 PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
1457 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1458 PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
1459 PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
1460 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1461 PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
1462 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
1463 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1464 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
1465 PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
1466 PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
1467 PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
1468 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1469 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1470 PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1471 PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
1472 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1473 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1474 PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
1475 PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
1476 PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
1477 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1478 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1479 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1480 PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
1481 PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
1482 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1483 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1484 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1485 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1486 PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
1487 PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
1488 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1489 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1490 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1491 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1492 PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
1493 PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
1494 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1495 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1496 PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
1497 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1498 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1499 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1500 PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1501 PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
1502 PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
1503 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1504 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1505 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1506 PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1507 PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
1508 PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
1510 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1511 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1512 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1513 PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
1514 PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
1515 PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
1516 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1517 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1518 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1519 PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
1520 PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
1521 PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
1522 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1523 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1524 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1525 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1526 PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
1527 PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
1528 PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
1529 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1530 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1531 PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
1532 PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
1533 PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
1534 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1535 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1536 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1537 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1538 PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
1539 PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
1540 PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
1541 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1542 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1543 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1544 PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
1545 PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
1546 PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
1547 PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
1548 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1549 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1550 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1551 PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
1552 PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
1553 PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
1554 PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
1555 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1556 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1557 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1558 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1559 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1560 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1561 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1562 PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
1563 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1564 PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
1565 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1566 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1567 PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
1568 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1569 PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
1570 PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
1571 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1572 PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
1574 PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
1575 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1576 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1577 PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
1578 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1579 PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
1580 PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
1581 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1582 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1583 PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
1584 PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
1585 PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
1586 PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
1587 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1588 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1589 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1590 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1591 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1592 PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
1593 PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
1594 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1595 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1596 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1597 PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
1598 PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
1599 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1600 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1601 PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
1602 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1603 PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
1604 PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
1605 PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
1606 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1607 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1608 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1609 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1610 PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
1611 PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
1612 PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
1613 PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
1614 PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
1615 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1616 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1617 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1618 PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1619 PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
1620 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1621 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1622 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1623 PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
1624 PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
1625 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1626 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1627 PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
1628 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1629 PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
1630 PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
1631 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1632 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1633 PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
1634 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1635 PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
1636 PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
1637 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1639 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1640 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1641 PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
1642 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1643 PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
1644 PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
1645 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1646 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1647 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1648 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1649 PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
1650 PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
1651 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1652 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1653 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1654 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1655 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1656 PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
1657 PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
1658 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1659 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1660 PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
1661 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1662 PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
1663 PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
1664 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1665 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1666 PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
1667 PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
1668 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1669 PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
1670 PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
1671 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1672 PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
1673 PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
1674 PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
1675 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1676 PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
1677 PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
1678 PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
1679 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1680 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1681 PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
1682 PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
1683 PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
1684 PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
1685 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1686 PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
1687 PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
1688 PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
1689 PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
1690 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1691 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1692 PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
1693 PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
1694 PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
1695 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1696 PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
1697 PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
1698 PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
1700 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1701 PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
1702 PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
1703 PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
1704 PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
1705 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1706 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1707 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1708 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1709 PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
1710 PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
1711 PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
1712 PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
1713 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1714 PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
1715 PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
1716 PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
1717 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1719 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1720 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1721 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1722 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1724 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1725 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1726 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1727 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1730 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1731 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1732 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1733 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1735 static const struct sh_pfc_pin pinmux_pins[] = {
1736 PINMUX_GPIO_GP_ALL(),
1738 /* Pins not associated with a GPIO port */
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
1740 SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
1741 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1742 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1745 /* - AUDIO CLOCK ------------------------------------------------------------ */
1746 static const unsigned int audio_clk_a_pins[] = {
1750 static const unsigned int audio_clk_a_mux[] = {
1753 static const unsigned int audio_clk_b_pins[] = {
1757 static const unsigned int audio_clk_b_mux[] = {
1760 static const unsigned int audio_clk_c_pins[] = {
1764 static const unsigned int audio_clk_c_mux[] = {
1767 static const unsigned int audio_clkout_pins[] = {
1771 static const unsigned int audio_clkout_mux[] = {
1774 static const unsigned int audio_clkout_b_pins[] = {
1778 static const unsigned int audio_clkout_b_mux[] = {
1779 AUDIO_CLKOUT_B_MARK,
1781 static const unsigned int audio_clkout_c_pins[] = {
1785 static const unsigned int audio_clkout_c_mux[] = {
1786 AUDIO_CLKOUT_C_MARK,
1788 static const unsigned int audio_clkout_d_pins[] = {
1792 static const unsigned int audio_clkout_d_mux[] = {
1793 AUDIO_CLKOUT_D_MARK,
1795 /* - AVB -------------------------------------------------------------------- */
1796 static const unsigned int avb_link_pins[] = {
1799 static const unsigned int avb_link_mux[] = {
1802 static const unsigned int avb_magic_pins[] = {
1805 static const unsigned int avb_magic_mux[] = {
1808 static const unsigned int avb_phy_int_pins[] = {
1811 static const unsigned int avb_phy_int_mux[] = {
1814 static const unsigned int avb_mdio_pins[] = {
1815 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1817 static const unsigned int avb_mdio_mux[] = {
1818 AVB_MDC_MARK, AVB_MDIO_MARK,
1820 static const unsigned int avb_mii_pins[] = {
1821 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1824 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1827 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1828 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1829 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
1831 static const unsigned int avb_mii_mux[] = {
1832 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1835 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1838 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1839 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1840 AVB_TX_CLK_MARK, AVB_COL_MARK,
1842 static const unsigned int avb_gmii_pins[] = {
1843 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1844 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1845 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1847 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1848 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1849 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1851 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1852 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1853 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1856 static const unsigned int avb_gmii_mux[] = {
1857 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1858 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1859 AVB_TXD6_MARK, AVB_TXD7_MARK,
1861 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1862 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1863 AVB_RXD6_MARK, AVB_RXD7_MARK,
1865 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1866 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1867 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1870 /* - DU RGB ----------------------------------------------------------------- */
1871 static const unsigned int du_rgb666_pins[] = {
1872 /* R[7:2], G[7:2], B[7:2] */
1873 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1874 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1875 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1876 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1877 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1878 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1880 static const unsigned int du_rgb666_mux[] = {
1881 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1882 DU2_DR3_MARK, DU2_DR2_MARK,
1883 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1884 DU2_DG3_MARK, DU2_DG2_MARK,
1885 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1886 DU2_DB3_MARK, DU2_DB2_MARK,
1888 static const unsigned int du_rgb888_pins[] = {
1889 /* R[7:0], G[7:0], B[7:0] */
1890 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1891 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1892 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1893 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1894 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1895 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1896 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1897 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1899 static const unsigned int du_rgb888_mux[] = {
1900 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1901 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1902 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1903 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1904 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1905 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1907 static const unsigned int du_clk_out_0_pins[] = {
1911 static const unsigned int du_clk_out_0_mux[] = {
1914 static const unsigned int du_clk_out_1_pins[] = {
1918 static const unsigned int du_clk_out_1_mux[] = {
1921 static const unsigned int du_sync_0_pins[] = {
1922 /* VSYNC, HSYNC, DISP */
1923 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1925 static const unsigned int du_sync_0_mux[] = {
1926 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1927 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1929 static const unsigned int du_sync_1_pins[] = {
1930 /* VSYNC, HSYNC, DISP */
1931 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1933 static const unsigned int du_sync_1_mux[] = {
1934 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1937 static const unsigned int du_cde_pins[] = {
1941 static const unsigned int du_cde_mux[] = {
1944 /* - DU0 -------------------------------------------------------------------- */
1945 static const unsigned int du0_clk_in_pins[] = {
1949 static const unsigned int du0_clk_in_mux[] = {
1952 /* - DU1 -------------------------------------------------------------------- */
1953 static const unsigned int du1_clk_in_pins[] = {
1957 static const unsigned int du1_clk_in_mux[] = {
1960 /* - DU2 -------------------------------------------------------------------- */
1961 static const unsigned int du2_clk_in_pins[] = {
1965 static const unsigned int du2_clk_in_mux[] = {
1968 /* - ETH -------------------------------------------------------------------- */
1969 static const unsigned int eth_link_pins[] = {
1973 static const unsigned int eth_link_mux[] = {
1976 static const unsigned int eth_magic_pins[] = {
1980 static const unsigned int eth_magic_mux[] = {
1983 static const unsigned int eth_mdio_pins[] = {
1985 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1987 static const unsigned int eth_mdio_mux[] = {
1988 ETH_MDC_MARK, ETH_MDIO_MARK,
1990 static const unsigned int eth_rmii_pins[] = {
1991 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1992 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1993 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1994 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1996 static const unsigned int eth_rmii_mux[] = {
1997 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1998 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2000 /* - HSCIF0 ----------------------------------------------------------------- */
2001 static const unsigned int hscif0_data_pins[] = {
2003 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2005 static const unsigned int hscif0_data_mux[] = {
2006 HRX0_MARK, HTX0_MARK,
2008 static const unsigned int hscif0_clk_pins[] = {
2012 static const unsigned int hscif0_clk_mux[] = {
2015 static const unsigned int hscif0_ctrl_pins[] = {
2017 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2019 static const unsigned int hscif0_ctrl_mux[] = {
2020 HRTS0_N_MARK, HCTS0_N_MARK,
2022 static const unsigned int hscif0_data_b_pins[] = {
2024 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2026 static const unsigned int hscif0_data_b_mux[] = {
2027 HRX0_B_MARK, HTX0_B_MARK,
2029 static const unsigned int hscif0_ctrl_b_pins[] = {
2031 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2033 static const unsigned int hscif0_ctrl_b_mux[] = {
2034 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2036 static const unsigned int hscif0_data_c_pins[] = {
2038 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2040 static const unsigned int hscif0_data_c_mux[] = {
2041 HRX0_C_MARK, HTX0_C_MARK,
2043 static const unsigned int hscif0_ctrl_c_pins[] = {
2045 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2047 static const unsigned int hscif0_ctrl_c_mux[] = {
2048 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2050 static const unsigned int hscif0_data_d_pins[] = {
2052 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2054 static const unsigned int hscif0_data_d_mux[] = {
2055 HRX0_D_MARK, HTX0_D_MARK,
2057 static const unsigned int hscif0_ctrl_d_pins[] = {
2059 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2061 static const unsigned int hscif0_ctrl_d_mux[] = {
2062 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2064 static const unsigned int hscif0_data_e_pins[] = {
2066 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2068 static const unsigned int hscif0_data_e_mux[] = {
2069 HRX0_E_MARK, HTX0_E_MARK,
2071 static const unsigned int hscif0_ctrl_e_pins[] = {
2073 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2075 static const unsigned int hscif0_ctrl_e_mux[] = {
2076 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2078 static const unsigned int hscif0_data_f_pins[] = {
2080 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2082 static const unsigned int hscif0_data_f_mux[] = {
2083 HRX0_F_MARK, HTX0_F_MARK,
2085 static const unsigned int hscif0_ctrl_f_pins[] = {
2087 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2089 static const unsigned int hscif0_ctrl_f_mux[] = {
2090 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2092 /* - HSCIF1 ----------------------------------------------------------------- */
2093 static const unsigned int hscif1_data_pins[] = {
2095 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2097 static const unsigned int hscif1_data_mux[] = {
2098 HRX1_MARK, HTX1_MARK,
2100 static const unsigned int hscif1_clk_pins[] = {
2104 static const unsigned int hscif1_clk_mux[] = {
2107 static const unsigned int hscif1_ctrl_pins[] = {
2109 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2111 static const unsigned int hscif1_ctrl_mux[] = {
2112 HRTS1_N_MARK, HCTS1_N_MARK,
2114 static const unsigned int hscif1_data_b_pins[] = {
2116 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2118 static const unsigned int hscif1_data_b_mux[] = {
2119 HRX1_B_MARK, HTX1_B_MARK,
2121 static const unsigned int hscif1_clk_b_pins[] = {
2125 static const unsigned int hscif1_clk_b_mux[] = {
2128 static const unsigned int hscif1_ctrl_b_pins[] = {
2130 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2132 static const unsigned int hscif1_ctrl_b_mux[] = {
2133 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2135 /* - I2C0 ------------------------------------------------------------------- */
2136 static const unsigned int i2c0_pins[] = {
2138 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2140 static const unsigned int i2c0_mux[] = {
2141 I2C0_SCL_MARK, I2C0_SDA_MARK,
2143 /* - I2C1 ------------------------------------------------------------------- */
2144 static const unsigned int i2c1_pins[] = {
2146 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2148 static const unsigned int i2c1_mux[] = {
2149 I2C1_SCL_MARK, I2C1_SDA_MARK,
2151 static const unsigned int i2c1_b_pins[] = {
2153 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2155 static const unsigned int i2c1_b_mux[] = {
2156 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2158 static const unsigned int i2c1_c_pins[] = {
2160 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2162 static const unsigned int i2c1_c_mux[] = {
2163 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2165 /* - I2C2 ------------------------------------------------------------------- */
2166 static const unsigned int i2c2_pins[] = {
2168 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2170 static const unsigned int i2c2_mux[] = {
2171 I2C2_SCL_MARK, I2C2_SDA_MARK,
2173 static const unsigned int i2c2_b_pins[] = {
2175 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2177 static const unsigned int i2c2_b_mux[] = {
2178 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2180 static const unsigned int i2c2_c_pins[] = {
2182 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2184 static const unsigned int i2c2_c_mux[] = {
2185 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2187 static const unsigned int i2c2_d_pins[] = {
2189 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2191 static const unsigned int i2c2_d_mux[] = {
2192 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2194 static const unsigned int i2c2_e_pins[] = {
2196 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2198 static const unsigned int i2c2_e_mux[] = {
2199 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2201 /* - I2C3 ------------------------------------------------------------------- */
2202 static const unsigned int i2c3_pins[] = {
2204 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2206 static const unsigned int i2c3_mux[] = {
2207 I2C3_SCL_MARK, I2C3_SDA_MARK,
2209 /* - IIC0 (I2C4) ------------------------------------------------------------ */
2210 static const unsigned int iic0_pins[] = {
2212 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2214 static const unsigned int iic0_mux[] = {
2215 IIC0_SCL_MARK, IIC0_SDA_MARK,
2217 /* - IIC1 (I2C5) ------------------------------------------------------------ */
2218 static const unsigned int iic1_pins[] = {
2220 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2222 static const unsigned int iic1_mux[] = {
2223 IIC1_SCL_MARK, IIC1_SDA_MARK,
2225 static const unsigned int iic1_b_pins[] = {
2227 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2229 static const unsigned int iic1_b_mux[] = {
2230 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2232 static const unsigned int iic1_c_pins[] = {
2234 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2236 static const unsigned int iic1_c_mux[] = {
2237 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2239 /* - IIC2 (I2C6) ------------------------------------------------------------ */
2240 static const unsigned int iic2_pins[] = {
2242 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2244 static const unsigned int iic2_mux[] = {
2245 IIC2_SCL_MARK, IIC2_SDA_MARK,
2247 static const unsigned int iic2_b_pins[] = {
2249 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2251 static const unsigned int iic2_b_mux[] = {
2252 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2254 static const unsigned int iic2_c_pins[] = {
2256 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2258 static const unsigned int iic2_c_mux[] = {
2259 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2261 static const unsigned int iic2_d_pins[] = {
2263 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2265 static const unsigned int iic2_d_mux[] = {
2266 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2268 static const unsigned int iic2_e_pins[] = {
2270 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2272 static const unsigned int iic2_e_mux[] = {
2273 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2275 /* - IIC3 (I2C7) ------------------------------------------------------------ */
2276 static const unsigned int iic3_pins[] = {
2278 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2280 static const unsigned int iic3_mux[] = {
2281 IIC3_SCL_MARK, IIC3_SDA_MARK,
2283 /* - INTC ------------------------------------------------------------------- */
2284 static const unsigned int intc_irq0_pins[] = {
2288 static const unsigned int intc_irq0_mux[] = {
2291 static const unsigned int intc_irq1_pins[] = {
2295 static const unsigned int intc_irq1_mux[] = {
2298 static const unsigned int intc_irq2_pins[] = {
2302 static const unsigned int intc_irq2_mux[] = {
2305 static const unsigned int intc_irq3_pins[] = {
2309 static const unsigned int intc_irq3_mux[] = {
2312 /* - MLB+ ------------------------------------------------------------------- */
2313 static const unsigned int mlb_3pin_pins[] = {
2314 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2316 static const unsigned int mlb_3pin_mux[] = {
2317 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2319 /* - MMCIF0 ----------------------------------------------------------------- */
2320 static const unsigned int mmc0_data1_pins[] = {
2324 static const unsigned int mmc0_data1_mux[] = {
2327 static const unsigned int mmc0_data4_pins[] = {
2329 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2330 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2332 static const unsigned int mmc0_data4_mux[] = {
2333 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2335 static const unsigned int mmc0_data8_pins[] = {
2337 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2338 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2339 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2340 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2342 static const unsigned int mmc0_data8_mux[] = {
2343 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2344 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2346 static const unsigned int mmc0_ctrl_pins[] = {
2348 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2350 static const unsigned int mmc0_ctrl_mux[] = {
2351 MMC0_CLK_MARK, MMC0_CMD_MARK,
2353 /* - MMCIF1 ----------------------------------------------------------------- */
2354 static const unsigned int mmc1_data1_pins[] = {
2358 static const unsigned int mmc1_data1_mux[] = {
2361 static const unsigned int mmc1_data4_pins[] = {
2363 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2364 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2366 static const unsigned int mmc1_data4_mux[] = {
2367 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2369 static const unsigned int mmc1_data8_pins[] = {
2371 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2372 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2373 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2374 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2376 static const unsigned int mmc1_data8_mux[] = {
2377 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2378 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2380 static const unsigned int mmc1_ctrl_pins[] = {
2382 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2384 static const unsigned int mmc1_ctrl_mux[] = {
2385 MMC1_CLK_MARK, MMC1_CMD_MARK,
2387 /* - MSIOF0 ----------------------------------------------------------------- */
2388 static const unsigned int msiof0_clk_pins[] = {
2392 static const unsigned int msiof0_clk_mux[] = {
2395 static const unsigned int msiof0_sync_pins[] = {
2399 static const unsigned int msiof0_sync_mux[] = {
2402 static const unsigned int msiof0_ss1_pins[] = {
2406 static const unsigned int msiof0_ss1_mux[] = {
2409 static const unsigned int msiof0_ss2_pins[] = {
2413 static const unsigned int msiof0_ss2_mux[] = {
2416 static const unsigned int msiof0_rx_pins[] = {
2420 static const unsigned int msiof0_rx_mux[] = {
2423 static const unsigned int msiof0_tx_pins[] = {
2427 static const unsigned int msiof0_tx_mux[] = {
2431 static const unsigned int msiof0_clk_b_pins[] = {
2435 static const unsigned int msiof0_clk_b_mux[] = {
2438 static const unsigned int msiof0_ss1_b_pins[] = {
2442 static const unsigned int msiof0_ss1_b_mux[] = {
2445 static const unsigned int msiof0_ss2_b_pins[] = {
2449 static const unsigned int msiof0_ss2_b_mux[] = {
2452 static const unsigned int msiof0_rx_b_pins[] = {
2456 static const unsigned int msiof0_rx_b_mux[] = {
2459 static const unsigned int msiof0_tx_b_pins[] = {
2463 static const unsigned int msiof0_tx_b_mux[] = {
2466 /* - MSIOF1 ----------------------------------------------------------------- */
2467 static const unsigned int msiof1_clk_pins[] = {
2471 static const unsigned int msiof1_clk_mux[] = {
2474 static const unsigned int msiof1_sync_pins[] = {
2478 static const unsigned int msiof1_sync_mux[] = {
2481 static const unsigned int msiof1_ss1_pins[] = {
2485 static const unsigned int msiof1_ss1_mux[] = {
2488 static const unsigned int msiof1_ss2_pins[] = {
2492 static const unsigned int msiof1_ss2_mux[] = {
2495 static const unsigned int msiof1_rx_pins[] = {
2499 static const unsigned int msiof1_rx_mux[] = {
2502 static const unsigned int msiof1_tx_pins[] = {
2506 static const unsigned int msiof1_tx_mux[] = {
2510 static const unsigned int msiof1_clk_b_pins[] = {
2514 static const unsigned int msiof1_clk_b_mux[] = {
2517 static const unsigned int msiof1_ss1_b_pins[] = {
2521 static const unsigned int msiof1_ss1_b_mux[] = {
2524 static const unsigned int msiof1_ss2_b_pins[] = {
2528 static const unsigned int msiof1_ss2_b_mux[] = {
2531 static const unsigned int msiof1_rx_b_pins[] = {
2535 static const unsigned int msiof1_rx_b_mux[] = {
2538 static const unsigned int msiof1_tx_b_pins[] = {
2542 static const unsigned int msiof1_tx_b_mux[] = {
2545 /* - MSIOF2 ----------------------------------------------------------------- */
2546 static const unsigned int msiof2_clk_pins[] = {
2550 static const unsigned int msiof2_clk_mux[] = {
2553 static const unsigned int msiof2_sync_pins[] = {
2557 static const unsigned int msiof2_sync_mux[] = {
2560 static const unsigned int msiof2_ss1_pins[] = {
2564 static const unsigned int msiof2_ss1_mux[] = {
2567 static const unsigned int msiof2_ss2_pins[] = {
2571 static const unsigned int msiof2_ss2_mux[] = {
2574 static const unsigned int msiof2_rx_pins[] = {
2578 static const unsigned int msiof2_rx_mux[] = {
2581 static const unsigned int msiof2_tx_pins[] = {
2585 static const unsigned int msiof2_tx_mux[] = {
2588 /* - MSIOF3 ----------------------------------------------------------------- */
2589 static const unsigned int msiof3_clk_pins[] = {
2593 static const unsigned int msiof3_clk_mux[] = {
2596 static const unsigned int msiof3_sync_pins[] = {
2600 static const unsigned int msiof3_sync_mux[] = {
2603 static const unsigned int msiof3_ss1_pins[] = {
2607 static const unsigned int msiof3_ss1_mux[] = {
2610 static const unsigned int msiof3_ss2_pins[] = {
2614 static const unsigned int msiof3_ss2_mux[] = {
2617 static const unsigned int msiof3_rx_pins[] = {
2621 static const unsigned int msiof3_rx_mux[] = {
2624 static const unsigned int msiof3_tx_pins[] = {
2628 static const unsigned int msiof3_tx_mux[] = {
2632 static const unsigned int msiof3_clk_b_pins[] = {
2636 static const unsigned int msiof3_clk_b_mux[] = {
2639 static const unsigned int msiof3_sync_b_pins[] = {
2643 static const unsigned int msiof3_sync_b_mux[] = {
2646 static const unsigned int msiof3_rx_b_pins[] = {
2650 static const unsigned int msiof3_rx_b_mux[] = {
2653 static const unsigned int msiof3_tx_b_pins[] = {
2657 static const unsigned int msiof3_tx_b_mux[] = {
2660 /* - PWM -------------------------------------------------------------------- */
2661 static const unsigned int pwm0_pins[] = {
2664 static const unsigned int pwm0_mux[] = {
2667 static const unsigned int pwm0_b_pins[] = {
2670 static const unsigned int pwm0_b_mux[] = {
2673 static const unsigned int pwm1_pins[] = {
2676 static const unsigned int pwm1_mux[] = {
2679 static const unsigned int pwm1_b_pins[] = {
2682 static const unsigned int pwm1_b_mux[] = {
2685 static const unsigned int pwm2_pins[] = {
2688 static const unsigned int pwm2_mux[] = {
2691 static const unsigned int pwm3_pins[] = {
2694 static const unsigned int pwm3_mux[] = {
2697 static const unsigned int pwm4_pins[] = {
2700 static const unsigned int pwm4_mux[] = {
2703 static const unsigned int pwm5_pins[] = {
2706 static const unsigned int pwm5_mux[] = {
2709 static const unsigned int pwm6_pins[] = {
2712 static const unsigned int pwm6_mux[] = {
2715 /* - QSPI ------------------------------------------------------------------- */
2716 static const unsigned int qspi_ctrl_pins[] = {
2718 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2720 static const unsigned int qspi_ctrl_mux[] = {
2721 SPCLK_MARK, SSL_MARK,
2723 static const unsigned int qspi_data2_pins[] = {
2724 /* MOSI_IO0, MISO_IO1 */
2725 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2727 static const unsigned int qspi_data2_mux[] = {
2728 MOSI_IO0_MARK, MISO_IO1_MARK,
2730 static const unsigned int qspi_data4_pins[] = {
2731 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2732 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2735 static const unsigned int qspi_data4_mux[] = {
2736 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2738 /* - SCIF0 ------------------------------------------------------------------ */
2739 static const unsigned int scif0_data_pins[] = {
2741 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2743 static const unsigned int scif0_data_mux[] = {
2746 static const unsigned int scif0_clk_pins[] = {
2750 static const unsigned int scif0_clk_mux[] = {
2753 static const unsigned int scif0_ctrl_pins[] = {
2755 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2757 static const unsigned int scif0_ctrl_mux[] = {
2758 RTS0_N_MARK, CTS0_N_MARK,
2760 static const unsigned int scif0_data_b_pins[] = {
2762 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2764 static const unsigned int scif0_data_b_mux[] = {
2765 RX0_B_MARK, TX0_B_MARK,
2767 /* - SCIF1 ------------------------------------------------------------------ */
2768 static const unsigned int scif1_data_pins[] = {
2770 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2772 static const unsigned int scif1_data_mux[] = {
2775 static const unsigned int scif1_clk_pins[] = {
2779 static const unsigned int scif1_clk_mux[] = {
2782 static const unsigned int scif1_ctrl_pins[] = {
2784 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2786 static const unsigned int scif1_ctrl_mux[] = {
2787 RTS1_N_MARK, CTS1_N_MARK,
2789 static const unsigned int scif1_data_b_pins[] = {
2791 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2793 static const unsigned int scif1_data_b_mux[] = {
2794 RX1_B_MARK, TX1_B_MARK,
2796 static const unsigned int scif1_data_c_pins[] = {
2798 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2800 static const unsigned int scif1_data_c_mux[] = {
2801 RX1_C_MARK, TX1_C_MARK,
2803 static const unsigned int scif1_data_d_pins[] = {
2805 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2807 static const unsigned int scif1_data_d_mux[] = {
2808 RX1_D_MARK, TX1_D_MARK,
2810 static const unsigned int scif1_clk_d_pins[] = {
2814 static const unsigned int scif1_clk_d_mux[] = {
2817 static const unsigned int scif1_data_e_pins[] = {
2819 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2821 static const unsigned int scif1_data_e_mux[] = {
2822 RX1_E_MARK, TX1_E_MARK,
2824 static const unsigned int scif1_clk_e_pins[] = {
2828 static const unsigned int scif1_clk_e_mux[] = {
2831 /* - SCIF2 ------------------------------------------------------------------ */
2832 static const unsigned int scif2_data_pins[] = {
2834 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2836 static const unsigned int scif2_data_mux[] = {
2839 static const unsigned int scif2_clk_pins[] = {
2843 static const unsigned int scif2_clk_mux[] = {
2846 static const unsigned int scif2_data_b_pins[] = {
2848 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2850 static const unsigned int scif2_data_b_mux[] = {
2851 RX2_B_MARK, TX2_B_MARK,
2853 /* - SCIFA0 ----------------------------------------------------------------- */
2854 static const unsigned int scifa0_data_pins[] = {
2856 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2858 static const unsigned int scifa0_data_mux[] = {
2859 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2861 static const unsigned int scifa0_clk_pins[] = {
2865 static const unsigned int scifa0_clk_mux[] = {
2868 static const unsigned int scifa0_ctrl_pins[] = {
2870 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2872 static const unsigned int scifa0_ctrl_mux[] = {
2873 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2875 static const unsigned int scifa0_data_b_pins[] = {
2877 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2879 static const unsigned int scifa0_data_b_mux[] = {
2880 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2882 static const unsigned int scifa0_clk_b_pins[] = {
2886 static const unsigned int scifa0_clk_b_mux[] = {
2889 static const unsigned int scifa0_ctrl_b_pins[] = {
2891 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2893 static const unsigned int scifa0_ctrl_b_mux[] = {
2894 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2896 /* - SCIFA1 ----------------------------------------------------------------- */
2897 static const unsigned int scifa1_data_pins[] = {
2899 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2901 static const unsigned int scifa1_data_mux[] = {
2902 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2904 static const unsigned int scifa1_clk_pins[] = {
2908 static const unsigned int scifa1_clk_mux[] = {
2911 static const unsigned int scifa1_ctrl_pins[] = {
2913 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2915 static const unsigned int scifa1_ctrl_mux[] = {
2916 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2918 static const unsigned int scifa1_data_b_pins[] = {
2920 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2922 static const unsigned int scifa1_data_b_mux[] = {
2923 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2925 static const unsigned int scifa1_clk_b_pins[] = {
2929 static const unsigned int scifa1_clk_b_mux[] = {
2932 static const unsigned int scifa1_ctrl_b_pins[] = {
2934 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2936 static const unsigned int scifa1_ctrl_b_mux[] = {
2937 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2939 static const unsigned int scifa1_data_c_pins[] = {
2941 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2943 static const unsigned int scifa1_data_c_mux[] = {
2944 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2946 static const unsigned int scifa1_clk_c_pins[] = {
2950 static const unsigned int scifa1_clk_c_mux[] = {
2953 static const unsigned int scifa1_ctrl_c_pins[] = {
2955 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2957 static const unsigned int scifa1_ctrl_c_mux[] = {
2958 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2960 static const unsigned int scifa1_data_d_pins[] = {
2962 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2964 static const unsigned int scifa1_data_d_mux[] = {
2965 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2967 static const unsigned int scifa1_clk_d_pins[] = {
2971 static const unsigned int scifa1_clk_d_mux[] = {
2974 static const unsigned int scifa1_ctrl_d_pins[] = {
2976 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2978 static const unsigned int scifa1_ctrl_d_mux[] = {
2979 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2981 /* - SCIFA2 ----------------------------------------------------------------- */
2982 static const unsigned int scifa2_data_pins[] = {
2984 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2986 static const unsigned int scifa2_data_mux[] = {
2987 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2989 static const unsigned int scifa2_clk_pins[] = {
2993 static const unsigned int scifa2_clk_mux[] = {
2996 static const unsigned int scifa2_ctrl_pins[] = {
2998 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3000 static const unsigned int scifa2_ctrl_mux[] = {
3001 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3003 static const unsigned int scifa2_data_b_pins[] = {
3005 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3007 static const unsigned int scifa2_data_b_mux[] = {
3008 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3010 static const unsigned int scifa2_data_c_pins[] = {
3012 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3014 static const unsigned int scifa2_data_c_mux[] = {
3015 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3017 static const unsigned int scifa2_clk_c_pins[] = {
3021 static const unsigned int scifa2_clk_c_mux[] = {
3024 /* - SCIFB0 ----------------------------------------------------------------- */
3025 static const unsigned int scifb0_data_pins[] = {
3027 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3029 static const unsigned int scifb0_data_mux[] = {
3030 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3032 static const unsigned int scifb0_clk_pins[] = {
3036 static const unsigned int scifb0_clk_mux[] = {
3039 static const unsigned int scifb0_ctrl_pins[] = {
3041 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3043 static const unsigned int scifb0_ctrl_mux[] = {
3044 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3046 static const unsigned int scifb0_data_b_pins[] = {
3048 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3050 static const unsigned int scifb0_data_b_mux[] = {
3051 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3053 static const unsigned int scifb0_clk_b_pins[] = {
3057 static const unsigned int scifb0_clk_b_mux[] = {
3060 static const unsigned int scifb0_ctrl_b_pins[] = {
3062 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3064 static const unsigned int scifb0_ctrl_b_mux[] = {
3065 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3067 static const unsigned int scifb0_data_c_pins[] = {
3069 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3071 static const unsigned int scifb0_data_c_mux[] = {
3072 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3074 /* - SCIFB1 ----------------------------------------------------------------- */
3075 static const unsigned int scifb1_data_pins[] = {
3077 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3079 static const unsigned int scifb1_data_mux[] = {
3080 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3082 static const unsigned int scifb1_clk_pins[] = {
3086 static const unsigned int scifb1_clk_mux[] = {
3089 static const unsigned int scifb1_ctrl_pins[] = {
3091 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3093 static const unsigned int scifb1_ctrl_mux[] = {
3094 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3096 static const unsigned int scifb1_data_b_pins[] = {
3098 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3100 static const unsigned int scifb1_data_b_mux[] = {
3101 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3103 static const unsigned int scifb1_clk_b_pins[] = {
3107 static const unsigned int scifb1_clk_b_mux[] = {
3110 static const unsigned int scifb1_ctrl_b_pins[] = {
3112 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3114 static const unsigned int scifb1_ctrl_b_mux[] = {
3115 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3117 static const unsigned int scifb1_data_c_pins[] = {
3119 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3121 static const unsigned int scifb1_data_c_mux[] = {
3122 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3124 static const unsigned int scifb1_data_d_pins[] = {
3126 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3128 static const unsigned int scifb1_data_d_mux[] = {
3129 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3131 static const unsigned int scifb1_data_e_pins[] = {
3133 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3135 static const unsigned int scifb1_data_e_mux[] = {
3136 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3138 static const unsigned int scifb1_clk_e_pins[] = {
3142 static const unsigned int scifb1_clk_e_mux[] = {
3145 static const unsigned int scifb1_data_f_pins[] = {
3147 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3149 static const unsigned int scifb1_data_f_mux[] = {
3150 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3152 static const unsigned int scifb1_data_g_pins[] = {
3154 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3156 static const unsigned int scifb1_data_g_mux[] = {
3157 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3159 static const unsigned int scifb1_clk_g_pins[] = {
3163 static const unsigned int scifb1_clk_g_mux[] = {
3166 /* - SCIFB2 ----------------------------------------------------------------- */
3167 static const unsigned int scifb2_data_pins[] = {
3169 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3171 static const unsigned int scifb2_data_mux[] = {
3172 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3174 static const unsigned int scifb2_clk_pins[] = {
3178 static const unsigned int scifb2_clk_mux[] = {
3181 static const unsigned int scifb2_ctrl_pins[] = {
3183 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3185 static const unsigned int scifb2_ctrl_mux[] = {
3186 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3188 static const unsigned int scifb2_data_b_pins[] = {
3190 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3192 static const unsigned int scifb2_data_b_mux[] = {
3193 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3195 static const unsigned int scifb2_clk_b_pins[] = {
3199 static const unsigned int scifb2_clk_b_mux[] = {
3202 static const unsigned int scifb2_ctrl_b_pins[] = {
3204 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3206 static const unsigned int scifb2_ctrl_b_mux[] = {
3207 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3209 static const unsigned int scifb2_data_c_pins[] = {
3211 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3213 static const unsigned int scifb2_data_c_mux[] = {
3214 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3216 /* - SCIF Clock ------------------------------------------------------------- */
3217 static const unsigned int scif_clk_pins[] = {
3221 static const unsigned int scif_clk_mux[] = {
3224 static const unsigned int scif_clk_b_pins[] = {
3228 static const unsigned int scif_clk_b_mux[] = {
3231 /* - SDHI0 ------------------------------------------------------------------ */
3232 static const unsigned int sdhi0_data1_pins[] = {
3236 static const unsigned int sdhi0_data1_mux[] = {
3239 static const unsigned int sdhi0_data4_pins[] = {
3241 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3243 static const unsigned int sdhi0_data4_mux[] = {
3244 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3246 static const unsigned int sdhi0_ctrl_pins[] = {
3248 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3250 static const unsigned int sdhi0_ctrl_mux[] = {
3251 SD0_CLK_MARK, SD0_CMD_MARK,
3253 static const unsigned int sdhi0_cd_pins[] = {
3257 static const unsigned int sdhi0_cd_mux[] = {
3260 static const unsigned int sdhi0_wp_pins[] = {
3264 static const unsigned int sdhi0_wp_mux[] = {
3267 /* - SDHI1 ------------------------------------------------------------------ */
3268 static const unsigned int sdhi1_data1_pins[] = {
3272 static const unsigned int sdhi1_data1_mux[] = {
3275 static const unsigned int sdhi1_data4_pins[] = {
3277 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3279 static const unsigned int sdhi1_data4_mux[] = {
3280 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3282 static const unsigned int sdhi1_ctrl_pins[] = {
3284 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3286 static const unsigned int sdhi1_ctrl_mux[] = {
3287 SD1_CLK_MARK, SD1_CMD_MARK,
3289 static const unsigned int sdhi1_cd_pins[] = {
3293 static const unsigned int sdhi1_cd_mux[] = {
3296 static const unsigned int sdhi1_wp_pins[] = {
3300 static const unsigned int sdhi1_wp_mux[] = {
3303 /* - SDHI2 ------------------------------------------------------------------ */
3304 static const unsigned int sdhi2_data1_pins[] = {
3308 static const unsigned int sdhi2_data1_mux[] = {
3311 static const unsigned int sdhi2_data4_pins[] = {
3313 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3315 static const unsigned int sdhi2_data4_mux[] = {
3316 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3318 static const unsigned int sdhi2_ctrl_pins[] = {
3320 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3322 static const unsigned int sdhi2_ctrl_mux[] = {
3323 SD2_CLK_MARK, SD2_CMD_MARK,
3325 static const unsigned int sdhi2_cd_pins[] = {
3329 static const unsigned int sdhi2_cd_mux[] = {
3332 static const unsigned int sdhi2_wp_pins[] = {
3336 static const unsigned int sdhi2_wp_mux[] = {
3339 /* - SDHI3 ------------------------------------------------------------------ */
3340 static const unsigned int sdhi3_data1_pins[] = {
3344 static const unsigned int sdhi3_data1_mux[] = {
3347 static const unsigned int sdhi3_data4_pins[] = {
3349 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3351 static const unsigned int sdhi3_data4_mux[] = {
3352 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3354 static const unsigned int sdhi3_ctrl_pins[] = {
3356 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3358 static const unsigned int sdhi3_ctrl_mux[] = {
3359 SD3_CLK_MARK, SD3_CMD_MARK,
3361 static const unsigned int sdhi3_cd_pins[] = {
3365 static const unsigned int sdhi3_cd_mux[] = {
3368 static const unsigned int sdhi3_wp_pins[] = {
3372 static const unsigned int sdhi3_wp_mux[] = {
3375 /* - SSI -------------------------------------------------------------------- */
3376 static const unsigned int ssi0_data_pins[] = {
3380 static const unsigned int ssi0_data_mux[] = {
3383 static const unsigned int ssi0129_ctrl_pins[] = {
3385 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3387 static const unsigned int ssi0129_ctrl_mux[] = {
3388 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3390 static const unsigned int ssi1_data_pins[] = {
3394 static const unsigned int ssi1_data_mux[] = {
3397 static const unsigned int ssi1_ctrl_pins[] = {
3399 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3401 static const unsigned int ssi1_ctrl_mux[] = {
3402 SSI_SCK1_MARK, SSI_WS1_MARK,
3404 static const unsigned int ssi2_data_pins[] = {
3408 static const unsigned int ssi2_data_mux[] = {
3411 static const unsigned int ssi2_ctrl_pins[] = {
3413 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3415 static const unsigned int ssi2_ctrl_mux[] = {
3416 SSI_SCK2_MARK, SSI_WS2_MARK,
3418 static const unsigned int ssi3_data_pins[] = {
3422 static const unsigned int ssi3_data_mux[] = {
3425 static const unsigned int ssi34_ctrl_pins[] = {
3427 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3429 static const unsigned int ssi34_ctrl_mux[] = {
3430 SSI_SCK34_MARK, SSI_WS34_MARK,
3432 static const unsigned int ssi4_data_pins[] = {
3436 static const unsigned int ssi4_data_mux[] = {
3439 static const unsigned int ssi4_ctrl_pins[] = {
3441 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3443 static const unsigned int ssi4_ctrl_mux[] = {
3444 SSI_SCK4_MARK, SSI_WS4_MARK,
3446 static const unsigned int ssi5_pins[] = {
3447 /* SDATA5, SCK, WS */
3448 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3450 static const unsigned int ssi5_mux[] = {
3451 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3453 static const unsigned int ssi5_b_pins[] = {
3454 /* SDATA5, SCK, WS */
3455 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3457 static const unsigned int ssi5_b_mux[] = {
3458 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3460 static const unsigned int ssi5_c_pins[] = {
3461 /* SDATA5, SCK, WS */
3462 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3464 static const unsigned int ssi5_c_mux[] = {
3465 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3467 static const unsigned int ssi6_pins[] = {
3468 /* SDATA6, SCK, WS */
3469 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3471 static const unsigned int ssi6_mux[] = {
3472 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3474 static const unsigned int ssi6_b_pins[] = {
3475 /* SDATA6, SCK, WS */
3476 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3478 static const unsigned int ssi6_b_mux[] = {
3479 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3481 static const unsigned int ssi7_data_pins[] = {
3485 static const unsigned int ssi7_data_mux[] = {
3488 static const unsigned int ssi7_b_data_pins[] = {
3492 static const unsigned int ssi7_b_data_mux[] = {
3495 static const unsigned int ssi7_c_data_pins[] = {
3499 static const unsigned int ssi7_c_data_mux[] = {
3502 static const unsigned int ssi78_ctrl_pins[] = {
3504 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3506 static const unsigned int ssi78_ctrl_mux[] = {
3507 SSI_SCK78_MARK, SSI_WS78_MARK,
3509 static const unsigned int ssi78_b_ctrl_pins[] = {
3511 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3513 static const unsigned int ssi78_b_ctrl_mux[] = {
3514 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3516 static const unsigned int ssi78_c_ctrl_pins[] = {
3518 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3520 static const unsigned int ssi78_c_ctrl_mux[] = {
3521 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3523 static const unsigned int ssi8_data_pins[] = {
3527 static const unsigned int ssi8_data_mux[] = {
3530 static const unsigned int ssi8_b_data_pins[] = {
3534 static const unsigned int ssi8_b_data_mux[] = {
3537 static const unsigned int ssi8_c_data_pins[] = {
3541 static const unsigned int ssi8_c_data_mux[] = {
3544 static const unsigned int ssi9_data_pins[] = {
3548 static const unsigned int ssi9_data_mux[] = {
3551 static const unsigned int ssi9_ctrl_pins[] = {
3553 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3555 static const unsigned int ssi9_ctrl_mux[] = {
3556 SSI_SCK9_MARK, SSI_WS9_MARK,
3558 /* - TPU0 ------------------------------------------------------------------- */
3559 static const unsigned int tpu0_to0_pins[] = {
3563 static const unsigned int tpu0_to0_mux[] = {
3566 static const unsigned int tpu0_to1_pins[] = {
3570 static const unsigned int tpu0_to1_mux[] = {
3573 static const unsigned int tpu0_to2_pins[] = {
3577 static const unsigned int tpu0_to2_mux[] = {
3580 static const unsigned int tpu0_to3_pins[] = {
3584 static const unsigned int tpu0_to3_mux[] = {
3587 /* - USB0 ------------------------------------------------------------------- */
3588 static const unsigned int usb0_pins[] = {
3589 /* PWEN, OVC/VBUS */
3590 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3592 static const unsigned int usb0_mux[] = {
3593 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3595 static const unsigned int usb0_ovc_vbus_pins[] = {
3599 static const unsigned int usb0_ovc_vbus_mux[] = {
3602 /* - USB1 ------------------------------------------------------------------- */
3603 static const unsigned int usb1_pins[] = {
3605 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3607 static const unsigned int usb1_mux[] = {
3608 USB1_PWEN_MARK, USB1_OVC_MARK,
3610 /* - USB2 ------------------------------------------------------------------- */
3611 static const unsigned int usb2_pins[] = {
3613 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3615 static const unsigned int usb2_mux[] = {
3616 USB2_PWEN_MARK, USB2_OVC_MARK,
3618 /* - VIN0 ------------------------------------------------------------------- */
3619 static const union vin_data vin0_data_pins = {
3622 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3623 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3624 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3625 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3627 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3628 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3629 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3630 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3632 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3633 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3634 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3635 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3638 static const union vin_data vin0_data_mux = {
3641 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3642 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3643 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3644 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3646 VI0_G0_MARK, VI0_G1_MARK,
3647 VI0_G2_MARK, VI0_G3_MARK,
3648 VI0_G4_MARK, VI0_G5_MARK,
3649 VI0_G6_MARK, VI0_G7_MARK,
3651 VI0_R0_MARK, VI0_R1_MARK,
3652 VI0_R2_MARK, VI0_R3_MARK,
3653 VI0_R4_MARK, VI0_R5_MARK,
3654 VI0_R6_MARK, VI0_R7_MARK,
3657 static const unsigned int vin0_data18_pins[] = {
3659 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3660 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3661 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3663 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3664 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3665 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3667 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3668 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3669 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3671 static const unsigned int vin0_data18_mux[] = {
3673 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3674 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3675 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3677 VI0_G2_MARK, VI0_G3_MARK,
3678 VI0_G4_MARK, VI0_G5_MARK,
3679 VI0_G6_MARK, VI0_G7_MARK,
3681 VI0_R2_MARK, VI0_R3_MARK,
3682 VI0_R4_MARK, VI0_R5_MARK,
3683 VI0_R6_MARK, VI0_R7_MARK,
3685 static const unsigned int vin0_sync_pins[] = {
3686 RCAR_GP_PIN(0, 12), /* HSYNC */
3687 RCAR_GP_PIN(0, 13), /* VSYNC */
3689 static const unsigned int vin0_sync_mux[] = {
3693 static const unsigned int vin0_field_pins[] = {
3696 static const unsigned int vin0_field_mux[] = {
3699 static const unsigned int vin0_clkenb_pins[] = {
3702 static const unsigned int vin0_clkenb_mux[] = {
3705 static const unsigned int vin0_clk_pins[] = {
3708 static const unsigned int vin0_clk_mux[] = {
3711 /* - VIN1 ------------------------------------------------------------------- */
3712 static const union vin_data vin1_data_pins = {
3715 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3716 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3717 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3718 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3720 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3721 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3722 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3723 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3725 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3726 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3727 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3728 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3731 static const union vin_data vin1_data_mux = {
3734 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3735 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3736 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3737 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3739 VI1_G0_MARK, VI1_G1_MARK,
3740 VI1_G2_MARK, VI1_G3_MARK,
3741 VI1_G4_MARK, VI1_G5_MARK,
3742 VI1_G6_MARK, VI1_G7_MARK,
3744 VI1_R0_MARK, VI1_R1_MARK,
3745 VI1_R2_MARK, VI1_R3_MARK,
3746 VI1_R4_MARK, VI1_R5_MARK,
3747 VI1_R6_MARK, VI1_R7_MARK,
3750 static const unsigned int vin1_data18_pins[] = {
3752 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3753 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3754 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3756 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3757 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3758 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3760 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3761 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3762 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3764 static const unsigned int vin1_data18_mux[] = {
3766 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3767 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3768 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3770 VI1_G2_MARK, VI1_G3_MARK,
3771 VI1_G4_MARK, VI1_G5_MARK,
3772 VI1_G6_MARK, VI1_G7_MARK,
3774 VI1_R2_MARK, VI1_R3_MARK,
3775 VI1_R4_MARK, VI1_R5_MARK,
3776 VI1_R6_MARK, VI1_R7_MARK,
3778 static const unsigned int vin1_sync_pins[] = {
3779 RCAR_GP_PIN(1, 24), /* HSYNC */
3780 RCAR_GP_PIN(1, 25), /* VSYNC */
3782 static const unsigned int vin1_sync_mux[] = {
3786 static const unsigned int vin1_field_pins[] = {
3789 static const unsigned int vin1_field_mux[] = {
3792 static const unsigned int vin1_clkenb_pins[] = {
3795 static const unsigned int vin1_clkenb_mux[] = {
3798 static const unsigned int vin1_clk_pins[] = {
3801 static const unsigned int vin1_clk_mux[] = {
3804 /* - VIN2 ----------------------------------------------------------------- */
3805 static const union vin_data vin2_data_pins = {
3808 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3809 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3810 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3811 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3813 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3814 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3815 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3816 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3818 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3819 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3820 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3821 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3824 static const union vin_data vin2_data_mux = {
3827 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3828 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3829 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3830 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3832 VI2_G0_MARK, VI2_G1_MARK,
3833 VI2_G2_MARK, VI2_G3_MARK,
3834 VI2_G4_MARK, VI2_G5_MARK,
3835 VI2_G6_MARK, VI2_G7_MARK,
3837 VI2_R0_MARK, VI2_R1_MARK,
3838 VI2_R2_MARK, VI2_R3_MARK,
3839 VI2_R4_MARK, VI2_R5_MARK,
3840 VI2_R6_MARK, VI2_R7_MARK,
3843 static const unsigned int vin2_data18_pins[] = {
3845 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3846 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3847 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3849 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3850 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3851 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3853 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3854 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3855 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3857 static const unsigned int vin2_data18_mux[] = {
3859 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3860 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3861 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3863 VI2_G2_MARK, VI2_G3_MARK,
3864 VI2_G4_MARK, VI2_G5_MARK,
3865 VI2_G6_MARK, VI2_G7_MARK,
3867 VI2_R2_MARK, VI2_R3_MARK,
3868 VI2_R4_MARK, VI2_R5_MARK,
3869 VI2_R6_MARK, VI2_R7_MARK,
3871 static const unsigned int vin2_sync_pins[] = {
3872 RCAR_GP_PIN(1, 16), /* HSYNC */
3873 RCAR_GP_PIN(1, 21), /* VSYNC */
3875 static const unsigned int vin2_sync_mux[] = {
3879 static const unsigned int vin2_field_pins[] = {
3882 static const unsigned int vin2_field_mux[] = {
3885 static const unsigned int vin2_clkenb_pins[] = {
3888 static const unsigned int vin2_clkenb_mux[] = {
3891 static const unsigned int vin2_clk_pins[] = {
3894 static const unsigned int vin2_clk_mux[] = {
3897 /* - VIN3 ----------------------------------------------------------------- */
3898 static const unsigned int vin3_data8_pins[] = {
3899 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3900 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3901 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3902 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3904 static const unsigned int vin3_data8_mux[] = {
3905 VI3_DATA0_MARK, VI3_DATA1_MARK,
3906 VI3_DATA2_MARK, VI3_DATA3_MARK,
3907 VI3_DATA4_MARK, VI3_DATA5_MARK,
3908 VI3_DATA6_MARK, VI3_DATA7_MARK,
3910 static const unsigned int vin3_sync_pins[] = {
3911 RCAR_GP_PIN(1, 16), /* HSYNC */
3912 RCAR_GP_PIN(1, 17), /* VSYNC */
3914 static const unsigned int vin3_sync_mux[] = {
3918 static const unsigned int vin3_field_pins[] = {
3921 static const unsigned int vin3_field_mux[] = {
3924 static const unsigned int vin3_clkenb_pins[] = {
3927 static const unsigned int vin3_clkenb_mux[] = {
3930 static const unsigned int vin3_clk_pins[] = {
3933 static const unsigned int vin3_clk_mux[] = {
3937 static const struct sh_pfc_pin_group pinmux_groups[] = {
3938 SH_PFC_PIN_GROUP(audio_clk_a),
3939 SH_PFC_PIN_GROUP(audio_clk_b),
3940 SH_PFC_PIN_GROUP(audio_clk_c),
3941 SH_PFC_PIN_GROUP(audio_clkout),
3942 SH_PFC_PIN_GROUP(audio_clkout_b),
3943 SH_PFC_PIN_GROUP(audio_clkout_c),
3944 SH_PFC_PIN_GROUP(audio_clkout_d),
3945 SH_PFC_PIN_GROUP(avb_link),
3946 SH_PFC_PIN_GROUP(avb_magic),
3947 SH_PFC_PIN_GROUP(avb_phy_int),
3948 SH_PFC_PIN_GROUP(avb_mdio),
3949 SH_PFC_PIN_GROUP(avb_mii),
3950 SH_PFC_PIN_GROUP(avb_gmii),
3951 SH_PFC_PIN_GROUP(du_rgb666),
3952 SH_PFC_PIN_GROUP(du_rgb888),
3953 SH_PFC_PIN_GROUP(du_clk_out_0),
3954 SH_PFC_PIN_GROUP(du_clk_out_1),
3955 SH_PFC_PIN_GROUP(du_sync_0),
3956 SH_PFC_PIN_GROUP(du_sync_1),
3957 SH_PFC_PIN_GROUP(du_cde),
3958 SH_PFC_PIN_GROUP(du0_clk_in),
3959 SH_PFC_PIN_GROUP(du1_clk_in),
3960 SH_PFC_PIN_GROUP(du2_clk_in),
3961 SH_PFC_PIN_GROUP(eth_link),
3962 SH_PFC_PIN_GROUP(eth_magic),
3963 SH_PFC_PIN_GROUP(eth_mdio),
3964 SH_PFC_PIN_GROUP(eth_rmii),
3965 SH_PFC_PIN_GROUP(hscif0_data),
3966 SH_PFC_PIN_GROUP(hscif0_clk),
3967 SH_PFC_PIN_GROUP(hscif0_ctrl),
3968 SH_PFC_PIN_GROUP(hscif0_data_b),
3969 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3970 SH_PFC_PIN_GROUP(hscif0_data_c),
3971 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3972 SH_PFC_PIN_GROUP(hscif0_data_d),
3973 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3974 SH_PFC_PIN_GROUP(hscif0_data_e),
3975 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3976 SH_PFC_PIN_GROUP(hscif0_data_f),
3977 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3978 SH_PFC_PIN_GROUP(hscif1_data),
3979 SH_PFC_PIN_GROUP(hscif1_clk),
3980 SH_PFC_PIN_GROUP(hscif1_ctrl),
3981 SH_PFC_PIN_GROUP(hscif1_data_b),
3982 SH_PFC_PIN_GROUP(hscif1_clk_b),
3983 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3984 SH_PFC_PIN_GROUP(i2c0),
3985 SH_PFC_PIN_GROUP(i2c1),
3986 SH_PFC_PIN_GROUP(i2c1_b),
3987 SH_PFC_PIN_GROUP(i2c1_c),
3988 SH_PFC_PIN_GROUP(i2c2),
3989 SH_PFC_PIN_GROUP(i2c2_b),
3990 SH_PFC_PIN_GROUP(i2c2_c),
3991 SH_PFC_PIN_GROUP(i2c2_d),
3992 SH_PFC_PIN_GROUP(i2c2_e),
3993 SH_PFC_PIN_GROUP(i2c3),
3994 SH_PFC_PIN_GROUP(iic0),
3995 SH_PFC_PIN_GROUP(iic1),
3996 SH_PFC_PIN_GROUP(iic1_b),
3997 SH_PFC_PIN_GROUP(iic1_c),
3998 SH_PFC_PIN_GROUP(iic2),
3999 SH_PFC_PIN_GROUP(iic2_b),
4000 SH_PFC_PIN_GROUP(iic2_c),
4001 SH_PFC_PIN_GROUP(iic2_d),
4002 SH_PFC_PIN_GROUP(iic2_e),
4003 SH_PFC_PIN_GROUP(iic3),
4004 SH_PFC_PIN_GROUP(intc_irq0),
4005 SH_PFC_PIN_GROUP(intc_irq1),
4006 SH_PFC_PIN_GROUP(intc_irq2),
4007 SH_PFC_PIN_GROUP(intc_irq3),
4008 SH_PFC_PIN_GROUP(mlb_3pin),
4009 SH_PFC_PIN_GROUP(mmc0_data1),
4010 SH_PFC_PIN_GROUP(mmc0_data4),
4011 SH_PFC_PIN_GROUP(mmc0_data8),
4012 SH_PFC_PIN_GROUP(mmc0_ctrl),
4013 SH_PFC_PIN_GROUP(mmc1_data1),
4014 SH_PFC_PIN_GROUP(mmc1_data4),
4015 SH_PFC_PIN_GROUP(mmc1_data8),
4016 SH_PFC_PIN_GROUP(mmc1_ctrl),
4017 SH_PFC_PIN_GROUP(msiof0_clk),
4018 SH_PFC_PIN_GROUP(msiof0_sync),
4019 SH_PFC_PIN_GROUP(msiof0_ss1),
4020 SH_PFC_PIN_GROUP(msiof0_ss2),
4021 SH_PFC_PIN_GROUP(msiof0_rx),
4022 SH_PFC_PIN_GROUP(msiof0_tx),
4023 SH_PFC_PIN_GROUP(msiof0_clk_b),
4024 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4025 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4026 SH_PFC_PIN_GROUP(msiof0_rx_b),
4027 SH_PFC_PIN_GROUP(msiof0_tx_b),
4028 SH_PFC_PIN_GROUP(msiof1_clk),
4029 SH_PFC_PIN_GROUP(msiof1_sync),
4030 SH_PFC_PIN_GROUP(msiof1_ss1),
4031 SH_PFC_PIN_GROUP(msiof1_ss2),
4032 SH_PFC_PIN_GROUP(msiof1_rx),
4033 SH_PFC_PIN_GROUP(msiof1_tx),
4034 SH_PFC_PIN_GROUP(msiof1_clk_b),
4035 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4036 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4037 SH_PFC_PIN_GROUP(msiof1_rx_b),
4038 SH_PFC_PIN_GROUP(msiof1_tx_b),
4039 SH_PFC_PIN_GROUP(msiof2_clk),
4040 SH_PFC_PIN_GROUP(msiof2_sync),
4041 SH_PFC_PIN_GROUP(msiof2_ss1),
4042 SH_PFC_PIN_GROUP(msiof2_ss2),
4043 SH_PFC_PIN_GROUP(msiof2_rx),
4044 SH_PFC_PIN_GROUP(msiof2_tx),
4045 SH_PFC_PIN_GROUP(msiof3_clk),
4046 SH_PFC_PIN_GROUP(msiof3_sync),
4047 SH_PFC_PIN_GROUP(msiof3_ss1),
4048 SH_PFC_PIN_GROUP(msiof3_ss2),
4049 SH_PFC_PIN_GROUP(msiof3_rx),
4050 SH_PFC_PIN_GROUP(msiof3_tx),
4051 SH_PFC_PIN_GROUP(msiof3_clk_b),
4052 SH_PFC_PIN_GROUP(msiof3_sync_b),
4053 SH_PFC_PIN_GROUP(msiof3_rx_b),
4054 SH_PFC_PIN_GROUP(msiof3_tx_b),
4055 SH_PFC_PIN_GROUP(pwm0),
4056 SH_PFC_PIN_GROUP(pwm0_b),
4057 SH_PFC_PIN_GROUP(pwm1),
4058 SH_PFC_PIN_GROUP(pwm1_b),
4059 SH_PFC_PIN_GROUP(pwm2),
4060 SH_PFC_PIN_GROUP(pwm3),
4061 SH_PFC_PIN_GROUP(pwm4),
4062 SH_PFC_PIN_GROUP(pwm5),
4063 SH_PFC_PIN_GROUP(pwm6),
4064 SH_PFC_PIN_GROUP(qspi_ctrl),
4065 SH_PFC_PIN_GROUP(qspi_data2),
4066 SH_PFC_PIN_GROUP(qspi_data4),
4067 SH_PFC_PIN_GROUP(scif0_data),
4068 SH_PFC_PIN_GROUP(scif0_clk),
4069 SH_PFC_PIN_GROUP(scif0_ctrl),
4070 SH_PFC_PIN_GROUP(scif0_data_b),
4071 SH_PFC_PIN_GROUP(scif1_data),
4072 SH_PFC_PIN_GROUP(scif1_clk),
4073 SH_PFC_PIN_GROUP(scif1_ctrl),
4074 SH_PFC_PIN_GROUP(scif1_data_b),
4075 SH_PFC_PIN_GROUP(scif1_data_c),
4076 SH_PFC_PIN_GROUP(scif1_data_d),
4077 SH_PFC_PIN_GROUP(scif1_clk_d),
4078 SH_PFC_PIN_GROUP(scif1_data_e),
4079 SH_PFC_PIN_GROUP(scif1_clk_e),
4080 SH_PFC_PIN_GROUP(scif2_data),
4081 SH_PFC_PIN_GROUP(scif2_clk),
4082 SH_PFC_PIN_GROUP(scif2_data_b),
4083 SH_PFC_PIN_GROUP(scifa0_data),
4084 SH_PFC_PIN_GROUP(scifa0_clk),
4085 SH_PFC_PIN_GROUP(scifa0_ctrl),
4086 SH_PFC_PIN_GROUP(scifa0_data_b),
4087 SH_PFC_PIN_GROUP(scifa0_clk_b),
4088 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4089 SH_PFC_PIN_GROUP(scifa1_data),
4090 SH_PFC_PIN_GROUP(scifa1_clk),
4091 SH_PFC_PIN_GROUP(scifa1_ctrl),
4092 SH_PFC_PIN_GROUP(scifa1_data_b),
4093 SH_PFC_PIN_GROUP(scifa1_clk_b),
4094 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4095 SH_PFC_PIN_GROUP(scifa1_data_c),
4096 SH_PFC_PIN_GROUP(scifa1_clk_c),
4097 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4098 SH_PFC_PIN_GROUP(scifa1_data_d),
4099 SH_PFC_PIN_GROUP(scifa1_clk_d),
4100 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4101 SH_PFC_PIN_GROUP(scifa2_data),
4102 SH_PFC_PIN_GROUP(scifa2_clk),
4103 SH_PFC_PIN_GROUP(scifa2_ctrl),
4104 SH_PFC_PIN_GROUP(scifa2_data_b),
4105 SH_PFC_PIN_GROUP(scifa2_data_c),
4106 SH_PFC_PIN_GROUP(scifa2_clk_c),
4107 SH_PFC_PIN_GROUP(scifb0_data),
4108 SH_PFC_PIN_GROUP(scifb0_clk),
4109 SH_PFC_PIN_GROUP(scifb0_ctrl),
4110 SH_PFC_PIN_GROUP(scifb0_data_b),
4111 SH_PFC_PIN_GROUP(scifb0_clk_b),
4112 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4113 SH_PFC_PIN_GROUP(scifb0_data_c),
4114 SH_PFC_PIN_GROUP(scifb1_data),
4115 SH_PFC_PIN_GROUP(scifb1_clk),
4116 SH_PFC_PIN_GROUP(scifb1_ctrl),
4117 SH_PFC_PIN_GROUP(scifb1_data_b),
4118 SH_PFC_PIN_GROUP(scifb1_clk_b),
4119 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4120 SH_PFC_PIN_GROUP(scifb1_data_c),
4121 SH_PFC_PIN_GROUP(scifb1_data_d),
4122 SH_PFC_PIN_GROUP(scifb1_data_e),
4123 SH_PFC_PIN_GROUP(scifb1_clk_e),
4124 SH_PFC_PIN_GROUP(scifb1_data_f),
4125 SH_PFC_PIN_GROUP(scifb1_data_g),
4126 SH_PFC_PIN_GROUP(scifb1_clk_g),
4127 SH_PFC_PIN_GROUP(scifb2_data),
4128 SH_PFC_PIN_GROUP(scifb2_clk),
4129 SH_PFC_PIN_GROUP(scifb2_ctrl),
4130 SH_PFC_PIN_GROUP(scifb2_data_b),
4131 SH_PFC_PIN_GROUP(scifb2_clk_b),
4132 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4133 SH_PFC_PIN_GROUP(scifb2_data_c),
4134 SH_PFC_PIN_GROUP(scif_clk),
4135 SH_PFC_PIN_GROUP(scif_clk_b),
4136 SH_PFC_PIN_GROUP(sdhi0_data1),
4137 SH_PFC_PIN_GROUP(sdhi0_data4),
4138 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4139 SH_PFC_PIN_GROUP(sdhi0_cd),
4140 SH_PFC_PIN_GROUP(sdhi0_wp),
4141 SH_PFC_PIN_GROUP(sdhi1_data1),
4142 SH_PFC_PIN_GROUP(sdhi1_data4),
4143 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4144 SH_PFC_PIN_GROUP(sdhi1_cd),
4145 SH_PFC_PIN_GROUP(sdhi1_wp),
4146 SH_PFC_PIN_GROUP(sdhi2_data1),
4147 SH_PFC_PIN_GROUP(sdhi2_data4),
4148 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4149 SH_PFC_PIN_GROUP(sdhi2_cd),
4150 SH_PFC_PIN_GROUP(sdhi2_wp),
4151 SH_PFC_PIN_GROUP(sdhi3_data1),
4152 SH_PFC_PIN_GROUP(sdhi3_data4),
4153 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4154 SH_PFC_PIN_GROUP(sdhi3_cd),
4155 SH_PFC_PIN_GROUP(sdhi3_wp),
4156 SH_PFC_PIN_GROUP(ssi0_data),
4157 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4158 SH_PFC_PIN_GROUP(ssi1_data),
4159 SH_PFC_PIN_GROUP(ssi1_ctrl),
4160 SH_PFC_PIN_GROUP(ssi2_data),
4161 SH_PFC_PIN_GROUP(ssi2_ctrl),
4162 SH_PFC_PIN_GROUP(ssi3_data),
4163 SH_PFC_PIN_GROUP(ssi34_ctrl),
4164 SH_PFC_PIN_GROUP(ssi4_data),
4165 SH_PFC_PIN_GROUP(ssi4_ctrl),
4166 SH_PFC_PIN_GROUP(ssi5),
4167 SH_PFC_PIN_GROUP(ssi5_b),
4168 SH_PFC_PIN_GROUP(ssi5_c),
4169 SH_PFC_PIN_GROUP(ssi6),
4170 SH_PFC_PIN_GROUP(ssi6_b),
4171 SH_PFC_PIN_GROUP(ssi7_data),
4172 SH_PFC_PIN_GROUP(ssi7_b_data),
4173 SH_PFC_PIN_GROUP(ssi7_c_data),
4174 SH_PFC_PIN_GROUP(ssi78_ctrl),
4175 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4176 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4177 SH_PFC_PIN_GROUP(ssi8_data),
4178 SH_PFC_PIN_GROUP(ssi8_b_data),
4179 SH_PFC_PIN_GROUP(ssi8_c_data),
4180 SH_PFC_PIN_GROUP(ssi9_data),
4181 SH_PFC_PIN_GROUP(ssi9_ctrl),
4182 SH_PFC_PIN_GROUP(tpu0_to0),
4183 SH_PFC_PIN_GROUP(tpu0_to1),
4184 SH_PFC_PIN_GROUP(tpu0_to2),
4185 SH_PFC_PIN_GROUP(tpu0_to3),
4186 SH_PFC_PIN_GROUP(usb0),
4187 SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4188 SH_PFC_PIN_GROUP(usb1),
4189 SH_PFC_PIN_GROUP(usb2),
4190 VIN_DATA_PIN_GROUP(vin0_data, 24),
4191 VIN_DATA_PIN_GROUP(vin0_data, 20),
4192 SH_PFC_PIN_GROUP(vin0_data18),
4193 VIN_DATA_PIN_GROUP(vin0_data, 16),
4194 VIN_DATA_PIN_GROUP(vin0_data, 12),
4195 VIN_DATA_PIN_GROUP(vin0_data, 10),
4196 VIN_DATA_PIN_GROUP(vin0_data, 8),
4197 VIN_DATA_PIN_GROUP(vin0_data, 4),
4198 SH_PFC_PIN_GROUP(vin0_sync),
4199 SH_PFC_PIN_GROUP(vin0_field),
4200 SH_PFC_PIN_GROUP(vin0_clkenb),
4201 SH_PFC_PIN_GROUP(vin0_clk),
4202 VIN_DATA_PIN_GROUP(vin1_data, 24),
4203 VIN_DATA_PIN_GROUP(vin1_data, 20),
4204 SH_PFC_PIN_GROUP(vin1_data18),
4205 VIN_DATA_PIN_GROUP(vin1_data, 16),
4206 VIN_DATA_PIN_GROUP(vin1_data, 12),
4207 VIN_DATA_PIN_GROUP(vin1_data, 10),
4208 VIN_DATA_PIN_GROUP(vin1_data, 8),
4209 VIN_DATA_PIN_GROUP(vin1_data, 4),
4210 SH_PFC_PIN_GROUP(vin1_sync),
4211 SH_PFC_PIN_GROUP(vin1_field),
4212 SH_PFC_PIN_GROUP(vin1_clkenb),
4213 SH_PFC_PIN_GROUP(vin1_clk),
4214 VIN_DATA_PIN_GROUP(vin2_data, 24),
4215 SH_PFC_PIN_GROUP(vin2_data18),
4216 VIN_DATA_PIN_GROUP(vin2_data, 16),
4217 VIN_DATA_PIN_GROUP(vin2_data, 8),
4218 VIN_DATA_PIN_GROUP(vin2_data, 4),
4219 SH_PFC_PIN_GROUP(vin2_sync),
4220 SH_PFC_PIN_GROUP(vin2_field),
4221 SH_PFC_PIN_GROUP(vin2_clkenb),
4222 SH_PFC_PIN_GROUP(vin2_clk),
4223 SH_PFC_PIN_GROUP(vin3_data8),
4224 SH_PFC_PIN_GROUP(vin3_sync),
4225 SH_PFC_PIN_GROUP(vin3_field),
4226 SH_PFC_PIN_GROUP(vin3_clkenb),
4227 SH_PFC_PIN_GROUP(vin3_clk),
4230 static const char * const audio_clk_groups[] = {
4240 static const char * const avb_groups[] = {
4249 static const char * const du_groups[] = {
4259 static const char * const du0_groups[] = {
4263 static const char * const du1_groups[] = {
4267 static const char * const du2_groups[] = {
4271 static const char * const eth_groups[] = {
4278 static const char * const hscif0_groups[] = {
4294 static const char * const hscif1_groups[] = {
4303 static const char * const i2c0_groups[] = {
4307 static const char * const i2c1_groups[] = {
4313 static const char * const i2c2_groups[] = {
4321 static const char * const i2c3_groups[] = {
4325 static const char * const iic0_groups[] = {
4329 static const char * const iic1_groups[] = {
4335 static const char * const iic2_groups[] = {
4343 static const char * const iic3_groups[] = {
4347 static const char * const intc_groups[] = {
4354 static const char * const mlb_groups[] = {
4358 static const char * const mmc0_groups[] = {
4365 static const char * const mmc1_groups[] = {
4372 static const char * const msiof0_groups[] = {
4386 static const char * const msiof1_groups[] = {
4400 static const char * const msiof2_groups[] = {
4409 static const char * const msiof3_groups[] = {
4422 static const char * const pwm0_groups[] = {
4427 static const char * const pwm1_groups[] = {
4432 static const char * const pwm2_groups[] = {
4436 static const char * const pwm3_groups[] = {
4440 static const char * const pwm4_groups[] = {
4444 static const char * const pwm5_groups[] = {
4448 static const char * const pwm6_groups[] = {
4452 static const char * const qspi_groups[] = {
4458 static const char * const scif0_groups[] = {
4465 static const char * const scif1_groups[] = {
4477 static const char * const scif2_groups[] = {
4483 static const char * const scifa0_groups[] = {
4492 static const char * const scifa1_groups[] = {
4507 static const char * const scifa2_groups[] = {
4516 static const char * const scifb0_groups[] = {
4526 static const char * const scifb1_groups[] = {
4542 static const char * const scifb2_groups[] = {
4552 static const char * const scif_clk_groups[] = {
4557 static const char * const sdhi0_groups[] = {
4565 static const char * const sdhi1_groups[] = {
4573 static const char * const sdhi2_groups[] = {
4581 static const char * const sdhi3_groups[] = {
4589 static const char * const ssi_groups[] = {
4618 static const char * const tpu0_groups[] = {
4625 static const char * const usb0_groups[] = {
4630 static const char * const usb1_groups[] = {
4634 static const char * const usb2_groups[] = {
4638 static const char * const vin0_groups[] = {
4653 static const char * const vin1_groups[] = {
4668 static const char * const vin2_groups[] = {
4680 static const char * const vin3_groups[] = {
4688 static const struct sh_pfc_function pinmux_functions[] = {
4689 SH_PFC_FUNCTION(audio_clk),
4690 SH_PFC_FUNCTION(avb),
4691 SH_PFC_FUNCTION(du),
4692 SH_PFC_FUNCTION(du0),
4693 SH_PFC_FUNCTION(du1),
4694 SH_PFC_FUNCTION(du2),
4695 SH_PFC_FUNCTION(eth),
4696 SH_PFC_FUNCTION(hscif0),
4697 SH_PFC_FUNCTION(hscif1),
4698 SH_PFC_FUNCTION(i2c0),
4699 SH_PFC_FUNCTION(i2c1),
4700 SH_PFC_FUNCTION(i2c2),
4701 SH_PFC_FUNCTION(i2c3),
4702 SH_PFC_FUNCTION(iic0),
4703 SH_PFC_FUNCTION(iic1),
4704 SH_PFC_FUNCTION(iic2),
4705 SH_PFC_FUNCTION(iic3),
4706 SH_PFC_FUNCTION(intc),
4707 SH_PFC_FUNCTION(mlb),
4708 SH_PFC_FUNCTION(mmc0),
4709 SH_PFC_FUNCTION(mmc1),
4710 SH_PFC_FUNCTION(msiof0),
4711 SH_PFC_FUNCTION(msiof1),
4712 SH_PFC_FUNCTION(msiof2),
4713 SH_PFC_FUNCTION(msiof3),
4714 SH_PFC_FUNCTION(pwm0),
4715 SH_PFC_FUNCTION(pwm1),
4716 SH_PFC_FUNCTION(pwm2),
4717 SH_PFC_FUNCTION(pwm3),
4718 SH_PFC_FUNCTION(pwm4),
4719 SH_PFC_FUNCTION(pwm5),
4720 SH_PFC_FUNCTION(pwm6),
4721 SH_PFC_FUNCTION(qspi),
4722 SH_PFC_FUNCTION(scif0),
4723 SH_PFC_FUNCTION(scif1),
4724 SH_PFC_FUNCTION(scif2),
4725 SH_PFC_FUNCTION(scifa0),
4726 SH_PFC_FUNCTION(scifa1),
4727 SH_PFC_FUNCTION(scifa2),
4728 SH_PFC_FUNCTION(scifb0),
4729 SH_PFC_FUNCTION(scifb1),
4730 SH_PFC_FUNCTION(scifb2),
4731 SH_PFC_FUNCTION(scif_clk),
4732 SH_PFC_FUNCTION(sdhi0),
4733 SH_PFC_FUNCTION(sdhi1),
4734 SH_PFC_FUNCTION(sdhi2),
4735 SH_PFC_FUNCTION(sdhi3),
4736 SH_PFC_FUNCTION(ssi),
4737 SH_PFC_FUNCTION(tpu0),
4738 SH_PFC_FUNCTION(usb0),
4739 SH_PFC_FUNCTION(usb1),
4740 SH_PFC_FUNCTION(usb2),
4741 SH_PFC_FUNCTION(vin0),
4742 SH_PFC_FUNCTION(vin1),
4743 SH_PFC_FUNCTION(vin2),
4744 SH_PFC_FUNCTION(vin3),
4747 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4748 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4749 GP_0_31_FN, FN_IP3_17_15,
4750 GP_0_30_FN, FN_IP3_14_12,
4751 GP_0_29_FN, FN_IP3_11_8,
4752 GP_0_28_FN, FN_IP3_7_4,
4753 GP_0_27_FN, FN_IP3_3_0,
4754 GP_0_26_FN, FN_IP2_28_26,
4755 GP_0_25_FN, FN_IP2_25_22,
4756 GP_0_24_FN, FN_IP2_21_18,
4757 GP_0_23_FN, FN_IP2_17_15,
4758 GP_0_22_FN, FN_IP2_14_12,
4759 GP_0_21_FN, FN_IP2_11_9,
4760 GP_0_20_FN, FN_IP2_8_6,
4761 GP_0_19_FN, FN_IP2_5_3,
4762 GP_0_18_FN, FN_IP2_2_0,
4763 GP_0_17_FN, FN_IP1_29_28,
4764 GP_0_16_FN, FN_IP1_27_26,
4765 GP_0_15_FN, FN_IP1_25_22,
4766 GP_0_14_FN, FN_IP1_21_18,
4767 GP_0_13_FN, FN_IP1_17_15,
4768 GP_0_12_FN, FN_IP1_14_12,
4769 GP_0_11_FN, FN_IP1_11_8,
4770 GP_0_10_FN, FN_IP1_7_4,
4771 GP_0_9_FN, FN_IP1_3_0,
4772 GP_0_8_FN, FN_IP0_30_27,
4773 GP_0_7_FN, FN_IP0_26_23,
4774 GP_0_6_FN, FN_IP0_22_20,
4775 GP_0_5_FN, FN_IP0_19_16,
4776 GP_0_4_FN, FN_IP0_15_12,
4777 GP_0_3_FN, FN_IP0_11_9,
4778 GP_0_2_FN, FN_IP0_8_6,
4779 GP_0_1_FN, FN_IP0_5_3,
4780 GP_0_0_FN, FN_IP0_2_0 }
4782 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4785 GP_1_29_FN, FN_IP6_13_11,
4786 GP_1_28_FN, FN_IP6_10_9,
4787 GP_1_27_FN, FN_IP6_8_6,
4788 GP_1_26_FN, FN_IP6_5_3,
4789 GP_1_25_FN, FN_IP6_2_0,
4790 GP_1_24_FN, FN_IP5_29_27,
4791 GP_1_23_FN, FN_IP5_26_24,
4792 GP_1_22_FN, FN_IP5_23_21,
4793 GP_1_21_FN, FN_IP5_20_18,
4794 GP_1_20_FN, FN_IP5_17_15,
4795 GP_1_19_FN, FN_IP5_14_13,
4796 GP_1_18_FN, FN_IP5_12_10,
4797 GP_1_17_FN, FN_IP5_9_6,
4798 GP_1_16_FN, FN_IP5_5_3,
4799 GP_1_15_FN, FN_IP5_2_0,
4800 GP_1_14_FN, FN_IP4_29_27,
4801 GP_1_13_FN, FN_IP4_26_24,
4802 GP_1_12_FN, FN_IP4_23_21,
4803 GP_1_11_FN, FN_IP4_20_18,
4804 GP_1_10_FN, FN_IP4_17_15,
4805 GP_1_9_FN, FN_IP4_14_12,
4806 GP_1_8_FN, FN_IP4_11_9,
4807 GP_1_7_FN, FN_IP4_8_6,
4808 GP_1_6_FN, FN_IP4_5_3,
4809 GP_1_5_FN, FN_IP4_2_0,
4810 GP_1_4_FN, FN_IP3_31_29,
4811 GP_1_3_FN, FN_IP3_28_26,
4812 GP_1_2_FN, FN_IP3_25_23,
4813 GP_1_1_FN, FN_IP3_22_20,
4814 GP_1_0_FN, FN_IP3_19_18, }
4816 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4819 GP_2_29_FN, FN_IP7_15_13,
4820 GP_2_28_FN, FN_IP7_12_10,
4821 GP_2_27_FN, FN_IP7_9_8,
4822 GP_2_26_FN, FN_IP7_7_6,
4823 GP_2_25_FN, FN_IP7_5_3,
4824 GP_2_24_FN, FN_IP7_2_0,
4825 GP_2_23_FN, FN_IP6_31_29,
4826 GP_2_22_FN, FN_IP6_28_26,
4827 GP_2_21_FN, FN_IP6_25_23,
4828 GP_2_20_FN, FN_IP6_22_20,
4829 GP_2_19_FN, FN_IP6_19_17,
4830 GP_2_18_FN, FN_IP6_16_14,
4831 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4832 GP_2_16_FN, FN_IP8_27,
4833 GP_2_15_FN, FN_IP8_26,
4834 GP_2_14_FN, FN_IP8_25_24,
4835 GP_2_13_FN, FN_IP8_23_22,
4836 GP_2_12_FN, FN_IP8_21_20,
4837 GP_2_11_FN, FN_IP8_19_18,
4838 GP_2_10_FN, FN_IP8_17_16,
4839 GP_2_9_FN, FN_IP8_15_14,
4840 GP_2_8_FN, FN_IP8_13_12,
4841 GP_2_7_FN, FN_IP8_11_10,
4842 GP_2_6_FN, FN_IP8_9_8,
4843 GP_2_5_FN, FN_IP8_7_6,
4844 GP_2_4_FN, FN_IP8_5_4,
4845 GP_2_3_FN, FN_IP8_3_2,
4846 GP_2_2_FN, FN_IP8_1_0,
4847 GP_2_1_FN, FN_IP7_30_29,
4848 GP_2_0_FN, FN_IP7_28_27 }
4850 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4851 GP_3_31_FN, FN_IP11_21_18,
4852 GP_3_30_FN, FN_IP11_17_15,
4853 GP_3_29_FN, FN_IP11_14_13,
4854 GP_3_28_FN, FN_IP11_12_11,
4855 GP_3_27_FN, FN_IP11_10_9,
4856 GP_3_26_FN, FN_IP11_8_7,
4857 GP_3_25_FN, FN_IP11_6_5,
4858 GP_3_24_FN, FN_IP11_4,
4859 GP_3_23_FN, FN_IP11_3_0,
4860 GP_3_22_FN, FN_IP10_29_26,
4861 GP_3_21_FN, FN_IP10_25_23,
4862 GP_3_20_FN, FN_IP10_22_19,
4863 GP_3_19_FN, FN_IP10_18_15,
4864 GP_3_18_FN, FN_IP10_14_11,
4865 GP_3_17_FN, FN_IP10_10_7,
4866 GP_3_16_FN, FN_IP10_6_4,
4867 GP_3_15_FN, FN_IP10_3_0,
4868 GP_3_14_FN, FN_IP9_31_28,
4869 GP_3_13_FN, FN_IP9_27_26,
4870 GP_3_12_FN, FN_IP9_25_24,
4871 GP_3_11_FN, FN_IP9_23_22,
4872 GP_3_10_FN, FN_IP9_21_20,
4873 GP_3_9_FN, FN_IP9_19_18,
4874 GP_3_8_FN, FN_IP9_17_16,
4875 GP_3_7_FN, FN_IP9_15_12,
4876 GP_3_6_FN, FN_IP9_11_8,
4877 GP_3_5_FN, FN_IP9_7_6,
4878 GP_3_4_FN, FN_IP9_5_4,
4879 GP_3_3_FN, FN_IP9_3_2,
4880 GP_3_2_FN, FN_IP9_1_0,
4881 GP_3_1_FN, FN_IP8_30_29,
4882 GP_3_0_FN, FN_IP8_28 }
4884 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4885 GP_4_31_FN, FN_IP14_18_16,
4886 GP_4_30_FN, FN_IP14_15_12,
4887 GP_4_29_FN, FN_IP14_11_9,
4888 GP_4_28_FN, FN_IP14_8_6,
4889 GP_4_27_FN, FN_IP14_5_3,
4890 GP_4_26_FN, FN_IP14_2_0,
4891 GP_4_25_FN, FN_IP13_30_29,
4892 GP_4_24_FN, FN_IP13_28_26,
4893 GP_4_23_FN, FN_IP13_25_23,
4894 GP_4_22_FN, FN_IP13_22_19,
4895 GP_4_21_FN, FN_IP13_18_16,
4896 GP_4_20_FN, FN_IP13_15_13,
4897 GP_4_19_FN, FN_IP13_12_10,
4898 GP_4_18_FN, FN_IP13_9_7,
4899 GP_4_17_FN, FN_IP13_6_3,
4900 GP_4_16_FN, FN_IP13_2_0,
4901 GP_4_15_FN, FN_IP12_30_28,
4902 GP_4_14_FN, FN_IP12_27_25,
4903 GP_4_13_FN, FN_IP12_24_23,
4904 GP_4_12_FN, FN_IP12_22_20,
4905 GP_4_11_FN, FN_IP12_19_17,
4906 GP_4_10_FN, FN_IP12_16_14,
4907 GP_4_9_FN, FN_IP12_13_11,
4908 GP_4_8_FN, FN_IP12_10_8,
4909 GP_4_7_FN, FN_IP12_7_6,
4910 GP_4_6_FN, FN_IP12_5_4,
4911 GP_4_5_FN, FN_IP12_3_2,
4912 GP_4_4_FN, FN_IP12_1_0,
4913 GP_4_3_FN, FN_IP11_31_30,
4914 GP_4_2_FN, FN_IP11_29_27,
4915 GP_4_1_FN, FN_IP11_26_24,
4916 GP_4_0_FN, FN_IP11_23_22 }
4918 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4919 GP_5_31_FN, FN_IP7_24_22,
4920 GP_5_30_FN, FN_IP7_21_19,
4921 GP_5_29_FN, FN_IP7_18_16,
4922 GP_5_28_FN, FN_DU_DOTCLKIN2,
4923 GP_5_27_FN, FN_IP7_26_25,
4924 GP_5_26_FN, FN_DU_DOTCLKIN0,
4925 GP_5_25_FN, FN_AVS2,
4926 GP_5_24_FN, FN_AVS1,
4927 GP_5_23_FN, FN_USB2_OVC,
4928 GP_5_22_FN, FN_USB2_PWEN,
4929 GP_5_21_FN, FN_IP16_7,
4930 GP_5_20_FN, FN_IP16_6,
4931 GP_5_19_FN, FN_USB0_OVC_VBUS,
4932 GP_5_18_FN, FN_USB0_PWEN,
4933 GP_5_17_FN, FN_IP16_5_3,
4934 GP_5_16_FN, FN_IP16_2_0,
4935 GP_5_15_FN, FN_IP15_29_28,
4936 GP_5_14_FN, FN_IP15_27_26,
4937 GP_5_13_FN, FN_IP15_25_23,
4938 GP_5_12_FN, FN_IP15_22_20,
4939 GP_5_11_FN, FN_IP15_19_18,
4940 GP_5_10_FN, FN_IP15_17_16,
4941 GP_5_9_FN, FN_IP15_15_14,
4942 GP_5_8_FN, FN_IP15_13_12,
4943 GP_5_7_FN, FN_IP15_11_9,
4944 GP_5_6_FN, FN_IP15_8_6,
4945 GP_5_5_FN, FN_IP15_5_3,
4946 GP_5_4_FN, FN_IP15_2_0,
4947 GP_5_3_FN, FN_IP14_30_28,
4948 GP_5_2_FN, FN_IP14_27_25,
4949 GP_5_1_FN, FN_IP14_24_22,
4950 GP_5_0_FN, FN_IP14_21_19 }
4952 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4953 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4957 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
4958 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4959 0, 0, 0, 0, 0, 0, 0, 0, 0,
4961 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4962 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
4963 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
4965 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4966 FN_I2C2_SCL_C, 0, 0,
4968 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4969 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4970 0, 0, 0, 0, 0, 0, 0, 0, 0,
4972 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4973 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4974 0, 0, 0, 0, 0, 0, 0, 0, 0,
4976 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4979 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
4982 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
4985 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
4988 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4989 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
4993 FN_A1, FN_PWM4, 0, 0,
4995 FN_A0, FN_PWM3, 0, 0,
4997 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
4998 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
4999 0, 0, 0, 0, 0, 0, 0, 0, 0,
5001 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5002 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5003 0, 0, 0, 0, 0, 0, 0, 0, 0,
5005 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5006 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5009 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5010 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5013 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5014 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5015 0, 0, 0, 0, 0, 0, 0, 0, 0,
5017 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5018 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5019 0, 0, 0, 0, 0, 0, 0, 0, 0,
5021 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5022 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5023 0, 0, 0, 0, 0, 0, 0, 0, 0, }
5025 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5026 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
5028 0, 0, 0, 0, 0, 0, 0, 0,
5030 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5031 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5033 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5034 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5035 0, 0, 0, 0, 0, 0, 0, 0,
5037 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5038 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5039 0, 0, 0, 0, 0, 0, 0, 0,
5041 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5044 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5046 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5048 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
5050 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5052 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
5054 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5055 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
5057 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5060 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5063 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5065 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5067 FN_A16, FN_ATAWR1_N, 0, 0,
5069 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5072 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5075 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5076 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5077 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5079 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5080 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5081 0, 0, 0, 0, 0, 0, 0, 0, 0,
5083 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5084 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5085 0, 0, 0, 0, 0, 0, 0, 0, }
5087 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5088 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5092 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5093 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5095 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5096 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5098 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5099 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5101 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5102 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5104 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5107 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5108 FN_VI2_FIELD_B, 0, 0,
5110 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5111 FN_VI2_CLKENB_B, 0, 0,
5113 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5115 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5117 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5120 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5121 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
5125 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5126 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5128 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
5129 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
5132 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5133 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5135 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5136 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5138 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5139 FN_INTC_IRQ4_N, 0, 0,
5141 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5143 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5146 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5147 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5148 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5150 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5151 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5152 FN_INTC_EN0_N, FN_I2C1_SCL,
5154 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5157 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5158 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
5160 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5161 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5163 FN_ETH_LINK, 0, FN_HTX0_E,
5164 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5166 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5167 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5169 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5170 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5172 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5173 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5175 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5176 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5179 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
5180 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
5182 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5184 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
5185 FN_SSI_SDATA8_C, 0, 0, 0,
5187 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5188 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5190 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5191 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
5193 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5194 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
5198 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5200 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5202 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5204 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5207 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5208 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5210 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5211 FN_GLO_SS_C, 0, 0, 0,
5213 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5214 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5216 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5217 FN_GLO_SCLK_C, 0, 0, 0,
5219 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5221 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5223 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5225 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5226 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
5228 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5229 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
5230 2, 2, 2, 2, 2, 2, 2) {
5234 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5236 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5238 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5240 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5242 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5245 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5247 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5249 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5251 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5253 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5255 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5257 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5259 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5261 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5263 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5265 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5267 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
5269 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5270 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
5272 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5273 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5274 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5276 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5278 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5280 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5282 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5284 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5286 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5288 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5289 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5290 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5292 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5293 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5294 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5296 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5298 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5300 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5302 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
5304 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5305 2, 4, 3, 4, 4, 4, 4, 3, 4) {
5306 /* IP10_31_30 [2] */
5308 /* IP10_29_26 [4] */
5309 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5310 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5311 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5312 /* IP10_25_23 [3] */
5313 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5314 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5315 /* IP10_22_19 [4] */
5316 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5317 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5318 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5319 /* IP10_18_15 [4] */
5320 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5321 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5322 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5324 /* IP10_14_11 [4] */
5325 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5326 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5327 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5328 0, 0, 0, 0, 0, 0, 0,
5330 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5331 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5332 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5333 0, 0, 0, 0, 0, 0, 0,
5335 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5336 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5339 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5340 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5341 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
5343 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5344 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
5345 /* IP11_31_30 [2] */
5346 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5347 /* IP11_29_27 [3] */
5348 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5350 /* IP11_26_24 [3] */
5351 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5353 /* IP11_23_22 [2] */
5354 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5355 /* IP11_21_18 [4] */
5356 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5357 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5358 /* IP11_17_15 [3] */
5359 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5360 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5361 /* IP11_14_13 [2] */
5362 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5363 /* IP11_12_11 [2] */
5364 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5366 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5368 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5370 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5372 FN_SD3_CLK, FN_MMC1_CLK,
5374 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5375 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5376 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
5378 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5379 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5382 /* IP12_30_28 [3] */
5383 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5384 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5385 FN_CAN_DEBUGOUT4, 0, 0,
5386 /* IP12_27_25 [3] */
5387 FN_SSI_SCK5, FN_SCIFB1_SCK,
5388 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5389 FN_CAN_DEBUGOUT3, 0, 0,
5390 /* IP12_24_23 [2] */
5391 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5393 /* IP12_22_20 [3] */
5394 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5395 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5396 /* IP12_19_17 [3] */
5397 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5398 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5399 /* IP12_16_14 [3] */
5400 FN_SSI_SDATA3, FN_STP_ISCLK_0,
5401 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5402 /* IP12_13_11 [3] */
5403 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5404 FN_CAN_STEP0, 0, 0, 0,
5406 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5407 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5409 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5411 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5413 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5415 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
5417 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5418 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5421 /* IP13_30_29 [2] */
5422 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5423 /* IP13_28_26 [3] */
5424 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5425 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5426 /* IP13_25_23 [3] */
5427 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5428 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5429 /* IP13_22_19 [4] */
5430 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5431 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5432 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5433 /* IP13_18_16 [3] */
5434 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5435 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5436 /* IP13_15_13 [3] */
5437 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5438 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5439 /* IP13_12_10 [3] */
5440 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5441 FN_CAN_DEBUGOUT8, 0, 0,
5443 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5444 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5446 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5447 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5448 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5450 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5451 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
5453 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5454 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5457 /* IP14_30_28 [3] */
5458 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5459 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5461 /* IP14_27_25 [3] */
5462 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5463 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5464 /* IP14_24_22 [3] */
5465 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5466 FN_LCDOUT9, 0, 0, 0,
5467 /* IP14_21_19 [3] */
5468 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5469 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5470 /* IP14_18_16 [3] */
5471 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5472 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5473 /* IP14_15_12 [4] */
5474 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5475 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5476 0, 0, 0, 0, 0, 0, 0,
5478 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5481 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5484 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5485 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5487 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5488 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5491 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5492 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5493 /* IP15_31_30 [2] */
5495 /* IP15_29_28 [2] */
5496 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5497 /* IP15_27_26 [2] */
5498 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5499 /* IP15_25_23 [3] */
5500 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5501 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5502 /* IP15_22_20 [3] */
5503 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5504 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5505 /* IP15_19_18 [2] */
5506 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5507 /* IP15_17_16 [2] */
5508 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5509 /* IP15_15_14 [2] */
5510 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5511 /* IP15_13_12 [2] */
5512 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5514 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5517 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5518 FN_IIC2_SDA, FN_I2C2_SDA, 0,
5520 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5521 FN_IIC2_SCL, FN_I2C2_SCL, 0,
5523 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5524 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
5526 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5527 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5528 /* IP16_31_28 [4] */
5529 0, 0, 0, 0, 0, 0, 0, 0,
5530 0, 0, 0, 0, 0, 0, 0, 0,
5531 /* IP16_27_24 [4] */
5532 0, 0, 0, 0, 0, 0, 0, 0,
5533 0, 0, 0, 0, 0, 0, 0, 0,
5534 /* IP16_23_20 [4] */
5535 0, 0, 0, 0, 0, 0, 0, 0,
5536 0, 0, 0, 0, 0, 0, 0, 0,
5537 /* IP16_19_16 [4] */
5538 0, 0, 0, 0, 0, 0, 0, 0,
5539 0, 0, 0, 0, 0, 0, 0, 0,
5540 /* IP16_15_12 [4] */
5541 0, 0, 0, 0, 0, 0, 0, 0,
5542 0, 0, 0, 0, 0, 0, 0, 0,
5544 0, 0, 0, 0, 0, 0, 0, 0,
5545 0, 0, 0, 0, 0, 0, 0, 0,
5547 FN_USB1_OVC, FN_TCLK1_B,
5549 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5551 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5552 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5554 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5555 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
5557 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5558 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5559 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5561 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5562 FN_SEL_SCIF1_4, 0, 0, 0,
5564 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5565 /* SEL_SCIFB2 [2] */
5566 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5567 /* SEL_SCIFB1 [3] */
5568 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5569 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5571 /* SEL_SCIFA1 [2] */
5572 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5575 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5577 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5579 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5581 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5583 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5585 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5587 FN_SEL_VI3_0, FN_SEL_VI3_1,
5589 FN_SEL_VI2_0, FN_SEL_VI2_1,
5591 FN_SEL_VI1_0, FN_SEL_VI1_1,
5593 FN_SEL_VI0_0, FN_SEL_VI0_1,
5595 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5599 FN_SEL_LBS_0, FN_SEL_LBS_1,
5601 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5603 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5605 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
5607 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5608 3, 1, 1, 1, 2, 1, 2, 1, 2,
5609 1, 1, 1, 3, 3, 2, 3, 2, 2) {
5611 0, 0, 0, 0, 0, 0, 0, 0,
5613 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5614 /* SEL_HSCIF1 [1] */
5615 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5616 /* SEL_SCIFCLK [1] */
5617 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5619 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5620 /* SEL_CANCLK [1] */
5621 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5622 /* SEL_SCIFA2 [2] */
5623 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5625 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5629 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5631 FN_SEL_ADI_0, FN_SEL_ADI_1,
5633 FN_SEL_SSP_0, FN_SEL_SSP_1,
5635 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5636 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5637 /* SEL_HSCIF0 [3] */
5638 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5639 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5641 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5643 0, 0, 0, 0, 0, 0, 0, 0,
5645 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5647 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
5649 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5650 1, 1, 2, 4, 4, 2, 2,
5652 /* SEL_IICDVFS [1] */
5653 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5655 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5659 0, 0, 0, 0, 0, 0, 0, 0,
5660 0, 0, 0, 0, 0, 0, 0, 0,
5662 0, 0, 0, 0, 0, 0, 0, 0,
5663 0, 0, 0, 0, 0, 0, 0, 0,
5667 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5669 0, 0, 0, 0, 0, 0, 0, 0,
5670 0, 0, 0, 0, 0, 0, 0, 0,
5674 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5675 FN_SEL_IIC2_4, 0, 0, 0,
5677 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5679 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5680 FN_SEL_I2C2_4, 0, 0, 0,
5682 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
5687 static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5689 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
5692 *pocctrl = 0xe606008c;
5694 return 31 - (pin & 0x1f);
5697 static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
5698 .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
5701 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5702 .name = "r8a77900_pfc",
5703 .ops = &r8a7790_pinmux_ops,
5704 .unlock_reg = 0xe6060000, /* PMMR */
5706 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5708 .pins = pinmux_pins,
5709 .nr_pins = ARRAY_SIZE(pinmux_pins),
5710 .groups = pinmux_groups,
5711 .nr_groups = ARRAY_SIZE(pinmux_groups),
5712 .functions = pinmux_functions,
5713 .nr_functions = ARRAY_SIZE(pinmux_functions),
5715 .cfg_regs = pinmux_config_regs,
5717 .pinmux_data = pinmux_data,
5718 .pinmux_data_size = ARRAY_SIZE(pinmux_data),