2 * R8A7796 processor support - PFC hardware block.
4 * Copyright (C) 2016 Renesas Electronics Corp.
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 * R-Car Gen3 processor support - PFC hardware block.
10 * Copyright (C) 2015 Renesas Electronics Corporation
12 * SPDX-License-Identifier: GPL-2.0
18 #include <dm/pinctrl.h>
19 #include <linux/kernel.h>
23 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
24 SH_PFC_PIN_CFG_PULL_UP | \
25 SH_PFC_PIN_CFG_PULL_DOWN)
27 #define CPU_ALL_PORT(fn, sfx) \
28 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
37 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
41 * F_() : just information
42 * FM() : macro for FN_xxx / xxx_MARK
46 #define GPSR0_15 F_(D15, IP7_11_8)
47 #define GPSR0_14 F_(D14, IP7_7_4)
48 #define GPSR0_13 F_(D13, IP7_3_0)
49 #define GPSR0_12 F_(D12, IP6_31_28)
50 #define GPSR0_11 F_(D11, IP6_27_24)
51 #define GPSR0_10 F_(D10, IP6_23_20)
52 #define GPSR0_9 F_(D9, IP6_19_16)
53 #define GPSR0_8 F_(D8, IP6_15_12)
54 #define GPSR0_7 F_(D7, IP6_11_8)
55 #define GPSR0_6 F_(D6, IP6_7_4)
56 #define GPSR0_5 F_(D5, IP6_3_0)
57 #define GPSR0_4 F_(D4, IP5_31_28)
58 #define GPSR0_3 F_(D3, IP5_27_24)
59 #define GPSR0_2 F_(D2, IP5_23_20)
60 #define GPSR0_1 F_(D1, IP5_19_16)
61 #define GPSR0_0 F_(D0, IP5_15_12)
64 #define GPSR1_28 FM(CLKOUT)
65 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
66 #define GPSR1_26 F_(WE1_N, IP5_7_4)
67 #define GPSR1_25 F_(WE0_N, IP5_3_0)
68 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
69 #define GPSR1_23 F_(RD_N, IP4_27_24)
70 #define GPSR1_22 F_(BS_N, IP4_23_20)
71 #define GPSR1_21 F_(CS1_N, IP4_19_16)
72 #define GPSR1_20 F_(CS0_N, IP4_15_12)
73 #define GPSR1_19 F_(A19, IP4_11_8)
74 #define GPSR1_18 F_(A18, IP4_7_4)
75 #define GPSR1_17 F_(A17, IP4_3_0)
76 #define GPSR1_16 F_(A16, IP3_31_28)
77 #define GPSR1_15 F_(A15, IP3_27_24)
78 #define GPSR1_14 F_(A14, IP3_23_20)
79 #define GPSR1_13 F_(A13, IP3_19_16)
80 #define GPSR1_12 F_(A12, IP3_15_12)
81 #define GPSR1_11 F_(A11, IP3_11_8)
82 #define GPSR1_10 F_(A10, IP3_7_4)
83 #define GPSR1_9 F_(A9, IP3_3_0)
84 #define GPSR1_8 F_(A8, IP2_31_28)
85 #define GPSR1_7 F_(A7, IP2_27_24)
86 #define GPSR1_6 F_(A6, IP2_23_20)
87 #define GPSR1_5 F_(A5, IP2_19_16)
88 #define GPSR1_4 F_(A4, IP2_15_12)
89 #define GPSR1_3 F_(A3, IP2_11_8)
90 #define GPSR1_2 F_(A2, IP2_7_4)
91 #define GPSR1_1 F_(A1, IP2_3_0)
92 #define GPSR1_0 F_(A0, IP1_31_28)
95 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
96 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
97 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
98 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
99 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
100 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
101 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
102 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
103 #define GPSR2_6 F_(PWM0, IP1_19_16)
104 #define GPSR2_5 F_(IRQ5, IP1_15_12)
105 #define GPSR2_4 F_(IRQ4, IP1_11_8)
106 #define GPSR2_3 F_(IRQ3, IP1_7_4)
107 #define GPSR2_2 F_(IRQ2, IP1_3_0)
108 #define GPSR2_1 F_(IRQ1, IP0_31_28)
109 #define GPSR2_0 F_(IRQ0, IP0_27_24)
112 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
113 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
114 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
115 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
116 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
117 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
118 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
119 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
120 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
121 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
122 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
123 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
124 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
125 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
126 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
127 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
130 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
131 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
132 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
133 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
134 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
135 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
136 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
137 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
138 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
139 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
140 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
141 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
142 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
143 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
144 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
145 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
146 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
147 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
150 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
151 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
152 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
153 #define GPSR5_22 FM(MSIOF0_RXD)
154 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
155 #define GPSR5_20 FM(MSIOF0_TXD)
156 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
157 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
158 #define GPSR5_17 FM(MSIOF0_SCK)
159 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
160 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
161 #define GPSR5_14 F_(HTX0, IP13_19_16)
162 #define GPSR5_13 F_(HRX0, IP13_15_12)
163 #define GPSR5_12 F_(HSCK0, IP13_11_8)
164 #define GPSR5_11 F_(RX2_A, IP13_7_4)
165 #define GPSR5_10 F_(TX2_A, IP13_3_0)
166 #define GPSR5_9 F_(SCK2, IP12_31_28)
167 #define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
168 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
169 #define GPSR5_6 F_(TX1_A, IP12_19_16)
170 #define GPSR5_5 F_(RX1_A, IP12_15_12)
171 #define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
172 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
173 #define GPSR5_2 F_(TX0, IP12_3_0)
174 #define GPSR5_1 F_(RX0, IP11_31_28)
175 #define GPSR5_0 F_(SCK0, IP11_27_24)
178 #define GPSR6_31 F_(GP6_31, IP18_7_4)
179 #define GPSR6_30 F_(GP6_30, IP18_3_0)
180 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
181 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
182 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
183 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
184 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
185 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
186 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
187 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
188 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
189 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
190 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
191 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
192 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
193 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
194 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
195 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
196 #define GPSR6_13 FM(SSI_SDATA5)
197 #define GPSR6_12 FM(SSI_WS5)
198 #define GPSR6_11 FM(SSI_SCK5)
199 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
200 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
201 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
202 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
203 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
204 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
205 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
206 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
207 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
208 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
209 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
212 #define GPSR7_3 FM(GP7_03)
213 #define GPSR7_2 FM(HDMI0_CEC)
214 #define GPSR7_1 FM(AVS2)
215 #define GPSR7_0 FM(AVS1)
218 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
219 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
248 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
279 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
315 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
336 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
345 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
365 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
366 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
367 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
368 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
369 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
371 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
373 #define PINMUX_GPSR \
381 GPSR1_25 GPSR5_25 GPSR6_25 \
382 GPSR1_24 GPSR5_24 GPSR6_24 \
383 GPSR1_23 GPSR5_23 GPSR6_23 \
384 GPSR1_22 GPSR5_22 GPSR6_22 \
385 GPSR1_21 GPSR5_21 GPSR6_21 \
386 GPSR1_20 GPSR5_20 GPSR6_20 \
387 GPSR1_19 GPSR5_19 GPSR6_19 \
388 GPSR1_18 GPSR5_18 GPSR6_18 \
389 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
390 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
391 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
392 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
393 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
394 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
395 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
396 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
397 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
398 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
399 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
400 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
401 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
402 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
403 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
404 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
405 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
406 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
408 #define PINMUX_IPSR \
410 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
411 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
412 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
413 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
414 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
415 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
416 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
417 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
419 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
420 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
421 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
422 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
423 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
424 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
425 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
426 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
428 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
429 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
430 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
431 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
432 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
433 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
434 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
435 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
437 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
438 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
439 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
440 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
441 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
442 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
443 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
444 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
446 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
447 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
448 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
449 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
450 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
451 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
452 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
453 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
455 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
456 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
458 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
459 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
460 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
461 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
462 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
463 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
464 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
465 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
466 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
467 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
468 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
469 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
470 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
471 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
472 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
473 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
475 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
476 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
477 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
479 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
480 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
482 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
483 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
484 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
485 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
486 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
487 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
488 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
489 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
490 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
491 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
492 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
493 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
494 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
495 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
496 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
497 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
499 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
500 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
501 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
502 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
503 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
504 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
505 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
506 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
507 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
508 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
509 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
510 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
511 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
512 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
514 #define PINMUX_MOD_SELS \
516 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
518 MOD_SEL1_29_28_27 MOD_SEL2_29 \
519 MOD_SEL0_28_27 MOD_SEL2_28_27 \
520 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
521 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
522 MOD_SEL0_23 MOD_SEL1_23_22_21 \
523 MOD_SEL0_22 MOD_SEL2_22 \
524 MOD_SEL0_21 MOD_SEL2_21 \
525 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
526 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
527 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
529 MOD_SEL0_16 MOD_SEL1_16 \
533 MOD_SEL0_12 MOD_SEL1_12 \
534 MOD_SEL0_11 MOD_SEL1_11 \
535 MOD_SEL0_10 MOD_SEL1_10 \
536 MOD_SEL0_9_8 MOD_SEL1_9 \
539 MOD_SEL0_5 MOD_SEL1_5 \
540 MOD_SEL0_4_3 MOD_SEL1_4 \
544 MOD_SEL1_0 MOD_SEL2_0
547 * These pins are not able to be muxed but have other properties
548 * that can be set, such as drive-strength or pull-up/pull-down enable.
550 #define PINMUX_STATIC \
551 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
552 FM(QSPI0_IO2) FM(QSPI0_IO3) \
553 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
554 FM(QSPI1_IO2) FM(QSPI1_IO3) \
555 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
556 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
557 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
558 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
560 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
561 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
571 #define FM(x) FN_##x,
572 PINMUX_FUNCTION_BEGIN,
582 #define FM(x) x##_MARK,
593 static const u16 pinmux_data[] = {
594 PINMUX_DATA_GP_ALL(),
598 PINMUX_SINGLE(CLKOUT),
599 PINMUX_SINGLE(GP7_03),
600 PINMUX_SINGLE(HDMI0_CEC),
601 PINMUX_SINGLE(MSIOF0_RXD),
602 PINMUX_SINGLE(MSIOF0_SCK),
603 PINMUX_SINGLE(MSIOF0_TXD),
604 PINMUX_SINGLE(SSI_SCK5),
605 PINMUX_SINGLE(SSI_SDATA5),
606 PINMUX_SINGLE(SSI_WS5),
609 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
610 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
613 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
616 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
617 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
620 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
621 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
624 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
625 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
626 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
628 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
629 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
630 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
632 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
633 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
634 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
635 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
637 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
638 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
640 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
641 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
642 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
643 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
645 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
646 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
649 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
650 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
651 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
652 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
653 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
654 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
656 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
657 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
658 PINMUX_IPSR_GPSR(IP1_7_4, A25),
659 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
660 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
661 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
662 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
664 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
665 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
666 PINMUX_IPSR_GPSR(IP1_11_8, A24),
667 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
668 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
669 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
670 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
672 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
673 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
674 PINMUX_IPSR_GPSR(IP1_15_12, A23),
675 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
676 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
677 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
678 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
680 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
681 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
682 PINMUX_IPSR_GPSR(IP1_19_16, A22),
683 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
686 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
687 PINMUX_IPSR_GPSR(IP1_23_20, A21),
688 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
689 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
690 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
692 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
693 PINMUX_IPSR_GPSR(IP1_27_24, A20),
694 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
695 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
697 PINMUX_IPSR_GPSR(IP1_31_28, A0),
698 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
699 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
700 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
701 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
702 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
705 PINMUX_IPSR_GPSR(IP2_3_0, A1),
706 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
707 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
708 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
709 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
710 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
712 PINMUX_IPSR_GPSR(IP2_7_4, A2),
713 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
714 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
715 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
716 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
717 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
719 PINMUX_IPSR_GPSR(IP2_11_8, A3),
720 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
721 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
722 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
723 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
724 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
726 PINMUX_IPSR_GPSR(IP2_15_12, A4),
727 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
728 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
729 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
730 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
731 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
733 PINMUX_IPSR_GPSR(IP2_19_16, A5),
734 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
735 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
736 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
737 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
738 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
739 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
741 PINMUX_IPSR_GPSR(IP2_23_20, A6),
742 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
743 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
744 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
745 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
746 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
747 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
749 PINMUX_IPSR_GPSR(IP2_27_24, A7),
750 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
751 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
752 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
753 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
754 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
755 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
757 PINMUX_IPSR_GPSR(IP2_31_28, A8),
758 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
760 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
761 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
762 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
763 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
766 PINMUX_IPSR_GPSR(IP3_3_0, A9),
767 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
768 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
769 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
771 PINMUX_IPSR_GPSR(IP3_7_4, A10),
772 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
773 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
774 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
776 PINMUX_IPSR_GPSR(IP3_11_8, A11),
777 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
778 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
780 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
781 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
782 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
783 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
784 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
786 PINMUX_IPSR_GPSR(IP3_15_12, A12),
787 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
788 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
789 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
790 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
791 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
793 PINMUX_IPSR_GPSR(IP3_19_16, A13),
794 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
795 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
796 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
797 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
798 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
800 PINMUX_IPSR_GPSR(IP3_23_20, A14),
801 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
802 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
803 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
804 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
805 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
807 PINMUX_IPSR_GPSR(IP3_27_24, A15),
808 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
809 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
810 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
811 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
812 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
814 PINMUX_IPSR_GPSR(IP3_31_28, A16),
815 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
816 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
817 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
820 PINMUX_IPSR_GPSR(IP4_3_0, A17),
821 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
822 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
823 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
825 PINMUX_IPSR_GPSR(IP4_7_4, A18),
826 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
827 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
828 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
830 PINMUX_IPSR_GPSR(IP4_11_8, A19),
831 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
832 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
833 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
835 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
836 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
838 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
839 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
840 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
842 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
843 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
844 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
845 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
846 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
847 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
848 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
849 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
851 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
852 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
853 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
856 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
858 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
859 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
860 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
861 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
862 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
863 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
866 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
867 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
868 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
869 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
870 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
871 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
872 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
874 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
875 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
876 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
877 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
878 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
879 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
880 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
881 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
883 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
884 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
885 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
886 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
888 PINMUX_IPSR_GPSR(IP5_15_12, D0),
889 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
890 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
891 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
892 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
894 PINMUX_IPSR_GPSR(IP5_19_16, D1),
895 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
896 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
897 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
898 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
900 PINMUX_IPSR_GPSR(IP5_23_20, D2),
901 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
902 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
903 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
905 PINMUX_IPSR_GPSR(IP5_27_24, D3),
906 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
907 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
908 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
910 PINMUX_IPSR_GPSR(IP5_31_28, D4),
911 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
912 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
913 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
916 PINMUX_IPSR_GPSR(IP6_3_0, D5),
917 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
918 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
919 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
921 PINMUX_IPSR_GPSR(IP6_7_4, D6),
922 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
923 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
924 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
926 PINMUX_IPSR_GPSR(IP6_11_8, D7),
927 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
928 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
929 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
931 PINMUX_IPSR_GPSR(IP6_15_12, D8),
932 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
933 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
935 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
936 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
938 PINMUX_IPSR_GPSR(IP6_19_16, D9),
939 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
940 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
941 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
942 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
944 PINMUX_IPSR_GPSR(IP6_23_20, D10),
945 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
946 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
947 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
948 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
949 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
950 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
952 PINMUX_IPSR_GPSR(IP6_27_24, D11),
953 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
954 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
955 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
956 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
957 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
958 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
960 PINMUX_IPSR_GPSR(IP6_31_28, D12),
961 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
962 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
963 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
964 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
965 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
968 PINMUX_IPSR_GPSR(IP7_3_0, D13),
969 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
970 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
971 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
972 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
975 PINMUX_IPSR_GPSR(IP7_7_4, D14),
976 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
977 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
978 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
979 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
980 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
981 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
983 PINMUX_IPSR_GPSR(IP7_11_8, D15),
984 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
985 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
986 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
987 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
988 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
989 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
991 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
992 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
995 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
996 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
999 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1000 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1002 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1004 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1005 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1006 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1007 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1010 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1011 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1012 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1013 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1015 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1016 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1017 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1018 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1020 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1021 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1025 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1027 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1028 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1030 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1031 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1032 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1034 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1037 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1038 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1039 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1041 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1044 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1045 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1046 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1048 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1051 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1052 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1053 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1054 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1055 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1056 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1059 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1060 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1062 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1063 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1065 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1066 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1068 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1069 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1071 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1072 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1074 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1075 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1077 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1078 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1080 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1081 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1084 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1085 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1087 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1088 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1090 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1091 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1093 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1094 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1096 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1097 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1099 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1100 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1101 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1103 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1104 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1105 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1107 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1108 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1109 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1112 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1113 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1114 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1116 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1117 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1119 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1120 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1121 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1123 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1124 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1126 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1127 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1129 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1130 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1132 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1133 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1137 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1138 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1139 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1140 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1141 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1143 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1144 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1145 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1146 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1147 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1150 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1151 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1152 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1153 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1154 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1156 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1157 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1158 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1159 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1160 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1161 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1162 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1163 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1165 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1166 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1168 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1169 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1170 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1171 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1172 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1174 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1175 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1176 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1177 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1178 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1182 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1183 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1184 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1186 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1187 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1188 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1189 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1190 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1191 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1192 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1194 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1195 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1196 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1197 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1199 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1200 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1202 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1204 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1205 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1206 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1207 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1208 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1211 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1213 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1214 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1215 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1216 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1218 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1220 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1221 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1222 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1223 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1225 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1226 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1228 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1229 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1230 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1231 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1232 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1234 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1235 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1237 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1238 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1239 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1241 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1242 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1244 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1245 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1246 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1248 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1249 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1250 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1252 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1253 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1254 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1255 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1257 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1258 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1259 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1260 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1261 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1262 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1263 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1265 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1266 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1267 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1268 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1271 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1272 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1273 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1275 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1276 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1277 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1278 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1280 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1281 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1283 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1285 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1286 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1287 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1289 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1290 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1291 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1293 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1294 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1295 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1296 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1298 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1299 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1300 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1302 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1303 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1305 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1306 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1308 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1309 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1312 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1314 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1315 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1317 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1318 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1319 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1321 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1322 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1323 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1324 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1326 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1327 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1332 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1334 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1335 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1340 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1342 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1343 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1348 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1350 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1351 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1356 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1359 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1360 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1362 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1363 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1365 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1366 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1368 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1369 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1371 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1376 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1377 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1378 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1379 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1384 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1385 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1386 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1387 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1391 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1393 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1394 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1395 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1396 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1402 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1406 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1428 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1429 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1430 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1435 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1438 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1445 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1446 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1447 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1448 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1455 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1467 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1468 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1469 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1470 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1478 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1488 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1499 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1500 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1501 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1504 * Static pins can not be muxed between different functions but
1505 * still needs a mark entry in the pinmux list. Add each static
1506 * pin to the list without an associated function. The sh-pfc
1507 * core will do the right thing and skip trying to mux then pin
1508 * while still applying configuration to it
1510 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1516 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1517 * Physical layout rows: A - AW, cols: 1 - 39.
1519 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1520 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1521 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1523 static const struct sh_pfc_pin pinmux_pins[] = {
1524 PINMUX_GPIO_GP_ALL(),
1527 * Pins not associated with a GPIO port.
1529 * The pin positions are different between different r8a7796
1530 * packages, all that is needed for the pfc driver is a unique
1531 * number for each pin. To this end use the pin layout from
1532 * R-Car M3SiP to calculate a unique number for each pin.
1534 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1578 /* - AUDIO CLOCK ------------------------------------------------------------ */
1579 static const unsigned int audio_clk_a_a_pins[] = {
1583 static const unsigned int audio_clk_a_a_mux[] = {
1586 static const unsigned int audio_clk_a_b_pins[] = {
1590 static const unsigned int audio_clk_a_b_mux[] = {
1593 static const unsigned int audio_clk_a_c_pins[] = {
1597 static const unsigned int audio_clk_a_c_mux[] = {
1600 static const unsigned int audio_clk_b_a_pins[] = {
1604 static const unsigned int audio_clk_b_a_mux[] = {
1607 static const unsigned int audio_clk_b_b_pins[] = {
1611 static const unsigned int audio_clk_b_b_mux[] = {
1614 static const unsigned int audio_clk_c_a_pins[] = {
1618 static const unsigned int audio_clk_c_a_mux[] = {
1621 static const unsigned int audio_clk_c_b_pins[] = {
1625 static const unsigned int audio_clk_c_b_mux[] = {
1628 static const unsigned int audio_clkout_a_pins[] = {
1632 static const unsigned int audio_clkout_a_mux[] = {
1633 AUDIO_CLKOUT_A_MARK,
1635 static const unsigned int audio_clkout_b_pins[] = {
1639 static const unsigned int audio_clkout_b_mux[] = {
1640 AUDIO_CLKOUT_B_MARK,
1642 static const unsigned int audio_clkout_c_pins[] = {
1646 static const unsigned int audio_clkout_c_mux[] = {
1647 AUDIO_CLKOUT_C_MARK,
1649 static const unsigned int audio_clkout_d_pins[] = {
1653 static const unsigned int audio_clkout_d_mux[] = {
1654 AUDIO_CLKOUT_D_MARK,
1656 static const unsigned int audio_clkout1_a_pins[] = {
1660 static const unsigned int audio_clkout1_a_mux[] = {
1661 AUDIO_CLKOUT1_A_MARK,
1663 static const unsigned int audio_clkout1_b_pins[] = {
1667 static const unsigned int audio_clkout1_b_mux[] = {
1668 AUDIO_CLKOUT1_B_MARK,
1670 static const unsigned int audio_clkout2_a_pins[] = {
1674 static const unsigned int audio_clkout2_a_mux[] = {
1675 AUDIO_CLKOUT2_A_MARK,
1677 static const unsigned int audio_clkout2_b_pins[] = {
1681 static const unsigned int audio_clkout2_b_mux[] = {
1682 AUDIO_CLKOUT2_B_MARK,
1685 static const unsigned int audio_clkout3_a_pins[] = {
1689 static const unsigned int audio_clkout3_a_mux[] = {
1690 AUDIO_CLKOUT3_A_MARK,
1692 static const unsigned int audio_clkout3_b_pins[] = {
1696 static const unsigned int audio_clkout3_b_mux[] = {
1697 AUDIO_CLKOUT3_B_MARK,
1700 /* - EtherAVB --------------------------------------------------------------- */
1701 static const unsigned int avb_link_pins[] = {
1705 static const unsigned int avb_link_mux[] = {
1708 static const unsigned int avb_magic_pins[] = {
1712 static const unsigned int avb_magic_mux[] = {
1715 static const unsigned int avb_phy_int_pins[] = {
1719 static const unsigned int avb_phy_int_mux[] = {
1722 static const unsigned int avb_mdc_pins[] = {
1723 /* AVB_MDC, AVB_MDIO */
1724 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1726 static const unsigned int avb_mdc_mux[] = {
1727 AVB_MDC_MARK, AVB_MDIO_MARK,
1729 static const unsigned int avb_mii_pins[] = {
1731 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1732 * AVB_TD1, AVB_TD2, AVB_TD3,
1733 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1734 * AVB_RD1, AVB_RD2, AVB_RD3,
1737 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1738 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1739 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1740 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1741 PIN_NUMBER('A', 12),
1744 static const unsigned int avb_mii_mux[] = {
1745 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1746 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1747 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1748 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1751 static const unsigned int avb_avtp_pps_pins[] = {
1755 static const unsigned int avb_avtp_pps_mux[] = {
1758 static const unsigned int avb_avtp_match_a_pins[] = {
1759 /* AVB_AVTP_MATCH_A */
1762 static const unsigned int avb_avtp_match_a_mux[] = {
1763 AVB_AVTP_MATCH_A_MARK,
1765 static const unsigned int avb_avtp_capture_a_pins[] = {
1766 /* AVB_AVTP_CAPTURE_A */
1769 static const unsigned int avb_avtp_capture_a_mux[] = {
1770 AVB_AVTP_CAPTURE_A_MARK,
1772 static const unsigned int avb_avtp_match_b_pins[] = {
1773 /* AVB_AVTP_MATCH_B */
1776 static const unsigned int avb_avtp_match_b_mux[] = {
1777 AVB_AVTP_MATCH_B_MARK,
1779 static const unsigned int avb_avtp_capture_b_pins[] = {
1780 /* AVB_AVTP_CAPTURE_B */
1783 static const unsigned int avb_avtp_capture_b_mux[] = {
1784 AVB_AVTP_CAPTURE_B_MARK,
1787 /* - CAN ------------------------------------------------------------------ */
1788 static const unsigned int can0_data_a_pins[] = {
1790 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1792 static const unsigned int can0_data_a_mux[] = {
1793 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1795 static const unsigned int can0_data_b_pins[] = {
1797 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1799 static const unsigned int can0_data_b_mux[] = {
1800 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1802 static const unsigned int can1_data_pins[] = {
1804 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1806 static const unsigned int can1_data_mux[] = {
1807 CAN1_TX_MARK, CAN1_RX_MARK,
1810 /* - CAN Clock -------------------------------------------------------------- */
1811 static const unsigned int can_clk_pins[] = {
1815 static const unsigned int can_clk_mux[] = {
1819 /* - CAN FD --------------------------------------------------------------- */
1820 static const unsigned int canfd0_data_a_pins[] = {
1822 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1824 static const unsigned int canfd0_data_a_mux[] = {
1825 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1827 static const unsigned int canfd0_data_b_pins[] = {
1829 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1831 static const unsigned int canfd0_data_b_mux[] = {
1832 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1834 static const unsigned int canfd1_data_pins[] = {
1836 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1838 static const unsigned int canfd1_data_mux[] = {
1839 CANFD1_TX_MARK, CANFD1_RX_MARK,
1842 /* - DRIF0 --------------------------------------------------------------- */
1843 static const unsigned int drif0_ctrl_a_pins[] = {
1845 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1847 static const unsigned int drif0_ctrl_a_mux[] = {
1848 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1850 static const unsigned int drif0_data0_a_pins[] = {
1854 static const unsigned int drif0_data0_a_mux[] = {
1857 static const unsigned int drif0_data1_a_pins[] = {
1861 static const unsigned int drif0_data1_a_mux[] = {
1864 static const unsigned int drif0_ctrl_b_pins[] = {
1866 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1868 static const unsigned int drif0_ctrl_b_mux[] = {
1869 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1871 static const unsigned int drif0_data0_b_pins[] = {
1875 static const unsigned int drif0_data0_b_mux[] = {
1878 static const unsigned int drif0_data1_b_pins[] = {
1882 static const unsigned int drif0_data1_b_mux[] = {
1885 static const unsigned int drif0_ctrl_c_pins[] = {
1887 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1889 static const unsigned int drif0_ctrl_c_mux[] = {
1890 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1892 static const unsigned int drif0_data0_c_pins[] = {
1896 static const unsigned int drif0_data0_c_mux[] = {
1899 static const unsigned int drif0_data1_c_pins[] = {
1903 static const unsigned int drif0_data1_c_mux[] = {
1906 /* - DRIF1 --------------------------------------------------------------- */
1907 static const unsigned int drif1_ctrl_a_pins[] = {
1909 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1911 static const unsigned int drif1_ctrl_a_mux[] = {
1912 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1914 static const unsigned int drif1_data0_a_pins[] = {
1918 static const unsigned int drif1_data0_a_mux[] = {
1921 static const unsigned int drif1_data1_a_pins[] = {
1925 static const unsigned int drif1_data1_a_mux[] = {
1928 static const unsigned int drif1_ctrl_b_pins[] = {
1930 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1932 static const unsigned int drif1_ctrl_b_mux[] = {
1933 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1935 static const unsigned int drif1_data0_b_pins[] = {
1939 static const unsigned int drif1_data0_b_mux[] = {
1942 static const unsigned int drif1_data1_b_pins[] = {
1946 static const unsigned int drif1_data1_b_mux[] = {
1949 static const unsigned int drif1_ctrl_c_pins[] = {
1951 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1953 static const unsigned int drif1_ctrl_c_mux[] = {
1954 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1956 static const unsigned int drif1_data0_c_pins[] = {
1960 static const unsigned int drif1_data0_c_mux[] = {
1963 static const unsigned int drif1_data1_c_pins[] = {
1967 static const unsigned int drif1_data1_c_mux[] = {
1970 /* - DRIF2 --------------------------------------------------------------- */
1971 static const unsigned int drif2_ctrl_a_pins[] = {
1973 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1975 static const unsigned int drif2_ctrl_a_mux[] = {
1976 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1978 static const unsigned int drif2_data0_a_pins[] = {
1982 static const unsigned int drif2_data0_a_mux[] = {
1985 static const unsigned int drif2_data1_a_pins[] = {
1989 static const unsigned int drif2_data1_a_mux[] = {
1992 static const unsigned int drif2_ctrl_b_pins[] = {
1994 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1996 static const unsigned int drif2_ctrl_b_mux[] = {
1997 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1999 static const unsigned int drif2_data0_b_pins[] = {
2003 static const unsigned int drif2_data0_b_mux[] = {
2006 static const unsigned int drif2_data1_b_pins[] = {
2010 static const unsigned int drif2_data1_b_mux[] = {
2013 /* - DRIF3 --------------------------------------------------------------- */
2014 static const unsigned int drif3_ctrl_a_pins[] = {
2016 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2018 static const unsigned int drif3_ctrl_a_mux[] = {
2019 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2021 static const unsigned int drif3_data0_a_pins[] = {
2025 static const unsigned int drif3_data0_a_mux[] = {
2028 static const unsigned int drif3_data1_a_pins[] = {
2032 static const unsigned int drif3_data1_a_mux[] = {
2035 static const unsigned int drif3_ctrl_b_pins[] = {
2037 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2039 static const unsigned int drif3_ctrl_b_mux[] = {
2040 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2042 static const unsigned int drif3_data0_b_pins[] = {
2046 static const unsigned int drif3_data0_b_mux[] = {
2049 static const unsigned int drif3_data1_b_pins[] = {
2053 static const unsigned int drif3_data1_b_mux[] = {
2057 /* - DU --------------------------------------------------------------------- */
2058 static const unsigned int du_rgb666_pins[] = {
2059 /* R[7:2], G[7:2], B[7:2] */
2060 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2061 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2062 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2063 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2064 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2065 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2067 static const unsigned int du_rgb666_mux[] = {
2068 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2069 DU_DR3_MARK, DU_DR2_MARK,
2070 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2071 DU_DG3_MARK, DU_DG2_MARK,
2072 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2073 DU_DB3_MARK, DU_DB2_MARK,
2075 static const unsigned int du_rgb888_pins[] = {
2076 /* R[7:0], G[7:0], B[7:0] */
2077 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2078 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2079 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2080 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2081 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2082 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2083 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2084 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2085 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2087 static const unsigned int du_rgb888_mux[] = {
2088 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2089 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2090 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2091 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2092 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2093 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2095 static const unsigned int du_clk_out_0_pins[] = {
2099 static const unsigned int du_clk_out_0_mux[] = {
2102 static const unsigned int du_clk_out_1_pins[] = {
2106 static const unsigned int du_clk_out_1_mux[] = {
2109 static const unsigned int du_sync_pins[] = {
2110 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2111 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2113 static const unsigned int du_sync_mux[] = {
2114 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2116 static const unsigned int du_oddf_pins[] = {
2117 /* EXDISP/EXODDF/EXCDE */
2120 static const unsigned int du_oddf_mux[] = {
2121 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2123 static const unsigned int du_cde_pins[] = {
2127 static const unsigned int du_cde_mux[] = {
2130 static const unsigned int du_disp_pins[] = {
2134 static const unsigned int du_disp_mux[] = {
2138 /* - HSCIF0 ----------------------------------------------------------------- */
2139 static const unsigned int hscif0_data_pins[] = {
2141 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2143 static const unsigned int hscif0_data_mux[] = {
2144 HRX0_MARK, HTX0_MARK,
2146 static const unsigned int hscif0_clk_pins[] = {
2150 static const unsigned int hscif0_clk_mux[] = {
2153 static const unsigned int hscif0_ctrl_pins[] = {
2155 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2157 static const unsigned int hscif0_ctrl_mux[] = {
2158 HRTS0_N_MARK, HCTS0_N_MARK,
2160 /* - HSCIF1 ----------------------------------------------------------------- */
2161 static const unsigned int hscif1_data_a_pins[] = {
2163 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2165 static const unsigned int hscif1_data_a_mux[] = {
2166 HRX1_A_MARK, HTX1_A_MARK,
2168 static const unsigned int hscif1_clk_a_pins[] = {
2172 static const unsigned int hscif1_clk_a_mux[] = {
2175 static const unsigned int hscif1_ctrl_a_pins[] = {
2177 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2179 static const unsigned int hscif1_ctrl_a_mux[] = {
2180 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2183 static const unsigned int hscif1_data_b_pins[] = {
2185 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2187 static const unsigned int hscif1_data_b_mux[] = {
2188 HRX1_B_MARK, HTX1_B_MARK,
2190 static const unsigned int hscif1_clk_b_pins[] = {
2194 static const unsigned int hscif1_clk_b_mux[] = {
2197 static const unsigned int hscif1_ctrl_b_pins[] = {
2199 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2201 static const unsigned int hscif1_ctrl_b_mux[] = {
2202 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2204 /* - HSCIF2 ----------------------------------------------------------------- */
2205 static const unsigned int hscif2_data_a_pins[] = {
2207 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2209 static const unsigned int hscif2_data_a_mux[] = {
2210 HRX2_A_MARK, HTX2_A_MARK,
2212 static const unsigned int hscif2_clk_a_pins[] = {
2216 static const unsigned int hscif2_clk_a_mux[] = {
2219 static const unsigned int hscif2_ctrl_a_pins[] = {
2221 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2223 static const unsigned int hscif2_ctrl_a_mux[] = {
2224 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2227 static const unsigned int hscif2_data_b_pins[] = {
2229 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2231 static const unsigned int hscif2_data_b_mux[] = {
2232 HRX2_B_MARK, HTX2_B_MARK,
2234 static const unsigned int hscif2_clk_b_pins[] = {
2238 static const unsigned int hscif2_clk_b_mux[] = {
2241 static const unsigned int hscif2_ctrl_b_pins[] = {
2243 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2245 static const unsigned int hscif2_ctrl_b_mux[] = {
2246 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2249 static const unsigned int hscif2_data_c_pins[] = {
2251 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2253 static const unsigned int hscif2_data_c_mux[] = {
2254 HRX2_C_MARK, HTX2_C_MARK,
2256 static const unsigned int hscif2_clk_c_pins[] = {
2260 static const unsigned int hscif2_clk_c_mux[] = {
2263 static const unsigned int hscif2_ctrl_c_pins[] = {
2265 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2267 static const unsigned int hscif2_ctrl_c_mux[] = {
2268 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2270 /* - HSCIF3 ----------------------------------------------------------------- */
2271 static const unsigned int hscif3_data_a_pins[] = {
2273 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2275 static const unsigned int hscif3_data_a_mux[] = {
2276 HRX3_A_MARK, HTX3_A_MARK,
2278 static const unsigned int hscif3_clk_pins[] = {
2282 static const unsigned int hscif3_clk_mux[] = {
2285 static const unsigned int hscif3_ctrl_pins[] = {
2287 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2289 static const unsigned int hscif3_ctrl_mux[] = {
2290 HRTS3_N_MARK, HCTS3_N_MARK,
2293 static const unsigned int hscif3_data_b_pins[] = {
2295 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2297 static const unsigned int hscif3_data_b_mux[] = {
2298 HRX3_B_MARK, HTX3_B_MARK,
2300 static const unsigned int hscif3_data_c_pins[] = {
2302 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2304 static const unsigned int hscif3_data_c_mux[] = {
2305 HRX3_C_MARK, HTX3_C_MARK,
2307 static const unsigned int hscif3_data_d_pins[] = {
2309 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2311 static const unsigned int hscif3_data_d_mux[] = {
2312 HRX3_D_MARK, HTX3_D_MARK,
2314 /* - HSCIF4 ----------------------------------------------------------------- */
2315 static const unsigned int hscif4_data_a_pins[] = {
2317 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2319 static const unsigned int hscif4_data_a_mux[] = {
2320 HRX4_A_MARK, HTX4_A_MARK,
2322 static const unsigned int hscif4_clk_pins[] = {
2326 static const unsigned int hscif4_clk_mux[] = {
2329 static const unsigned int hscif4_ctrl_pins[] = {
2331 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2333 static const unsigned int hscif4_ctrl_mux[] = {
2334 HRTS4_N_MARK, HCTS4_N_MARK,
2337 static const unsigned int hscif4_data_b_pins[] = {
2339 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2341 static const unsigned int hscif4_data_b_mux[] = {
2342 HRX4_B_MARK, HTX4_B_MARK,
2345 /* - I2C -------------------------------------------------------------------- */
2346 static const unsigned int i2c1_a_pins[] = {
2348 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2350 static const unsigned int i2c1_a_mux[] = {
2351 SDA1_A_MARK, SCL1_A_MARK,
2353 static const unsigned int i2c1_b_pins[] = {
2355 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2357 static const unsigned int i2c1_b_mux[] = {
2358 SDA1_B_MARK, SCL1_B_MARK,
2360 static const unsigned int i2c2_a_pins[] = {
2362 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2364 static const unsigned int i2c2_a_mux[] = {
2365 SDA2_A_MARK, SCL2_A_MARK,
2367 static const unsigned int i2c2_b_pins[] = {
2369 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2371 static const unsigned int i2c2_b_mux[] = {
2372 SDA2_B_MARK, SCL2_B_MARK,
2374 static const unsigned int i2c6_a_pins[] = {
2376 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2378 static const unsigned int i2c6_a_mux[] = {
2379 SDA6_A_MARK, SCL6_A_MARK,
2381 static const unsigned int i2c6_b_pins[] = {
2383 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2385 static const unsigned int i2c6_b_mux[] = {
2386 SDA6_B_MARK, SCL6_B_MARK,
2388 static const unsigned int i2c6_c_pins[] = {
2390 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2392 static const unsigned int i2c6_c_mux[] = {
2393 SDA6_C_MARK, SCL6_C_MARK,
2396 /* - MSIOF0 ----------------------------------------------------------------- */
2397 static const unsigned int msiof0_clk_pins[] = {
2401 static const unsigned int msiof0_clk_mux[] = {
2404 static const unsigned int msiof0_sync_pins[] = {
2408 static const unsigned int msiof0_sync_mux[] = {
2411 static const unsigned int msiof0_ss1_pins[] = {
2415 static const unsigned int msiof0_ss1_mux[] = {
2418 static const unsigned int msiof0_ss2_pins[] = {
2422 static const unsigned int msiof0_ss2_mux[] = {
2425 static const unsigned int msiof0_txd_pins[] = {
2429 static const unsigned int msiof0_txd_mux[] = {
2432 static const unsigned int msiof0_rxd_pins[] = {
2436 static const unsigned int msiof0_rxd_mux[] = {
2439 /* - MSIOF1 ----------------------------------------------------------------- */
2440 static const unsigned int msiof1_clk_a_pins[] = {
2444 static const unsigned int msiof1_clk_a_mux[] = {
2447 static const unsigned int msiof1_sync_a_pins[] = {
2451 static const unsigned int msiof1_sync_a_mux[] = {
2454 static const unsigned int msiof1_ss1_a_pins[] = {
2458 static const unsigned int msiof1_ss1_a_mux[] = {
2461 static const unsigned int msiof1_ss2_a_pins[] = {
2465 static const unsigned int msiof1_ss2_a_mux[] = {
2468 static const unsigned int msiof1_txd_a_pins[] = {
2472 static const unsigned int msiof1_txd_a_mux[] = {
2475 static const unsigned int msiof1_rxd_a_pins[] = {
2479 static const unsigned int msiof1_rxd_a_mux[] = {
2482 static const unsigned int msiof1_clk_b_pins[] = {
2486 static const unsigned int msiof1_clk_b_mux[] = {
2489 static const unsigned int msiof1_sync_b_pins[] = {
2493 static const unsigned int msiof1_sync_b_mux[] = {
2496 static const unsigned int msiof1_ss1_b_pins[] = {
2500 static const unsigned int msiof1_ss1_b_mux[] = {
2503 static const unsigned int msiof1_ss2_b_pins[] = {
2507 static const unsigned int msiof1_ss2_b_mux[] = {
2510 static const unsigned int msiof1_txd_b_pins[] = {
2514 static const unsigned int msiof1_txd_b_mux[] = {
2517 static const unsigned int msiof1_rxd_b_pins[] = {
2521 static const unsigned int msiof1_rxd_b_mux[] = {
2524 static const unsigned int msiof1_clk_c_pins[] = {
2528 static const unsigned int msiof1_clk_c_mux[] = {
2531 static const unsigned int msiof1_sync_c_pins[] = {
2535 static const unsigned int msiof1_sync_c_mux[] = {
2538 static const unsigned int msiof1_ss1_c_pins[] = {
2542 static const unsigned int msiof1_ss1_c_mux[] = {
2545 static const unsigned int msiof1_ss2_c_pins[] = {
2549 static const unsigned int msiof1_ss2_c_mux[] = {
2552 static const unsigned int msiof1_txd_c_pins[] = {
2556 static const unsigned int msiof1_txd_c_mux[] = {
2559 static const unsigned int msiof1_rxd_c_pins[] = {
2563 static const unsigned int msiof1_rxd_c_mux[] = {
2566 static const unsigned int msiof1_clk_d_pins[] = {
2570 static const unsigned int msiof1_clk_d_mux[] = {
2573 static const unsigned int msiof1_sync_d_pins[] = {
2577 static const unsigned int msiof1_sync_d_mux[] = {
2580 static const unsigned int msiof1_ss1_d_pins[] = {
2584 static const unsigned int msiof1_ss1_d_mux[] = {
2587 static const unsigned int msiof1_ss2_d_pins[] = {
2591 static const unsigned int msiof1_ss2_d_mux[] = {
2594 static const unsigned int msiof1_txd_d_pins[] = {
2598 static const unsigned int msiof1_txd_d_mux[] = {
2601 static const unsigned int msiof1_rxd_d_pins[] = {
2605 static const unsigned int msiof1_rxd_d_mux[] = {
2608 static const unsigned int msiof1_clk_e_pins[] = {
2612 static const unsigned int msiof1_clk_e_mux[] = {
2615 static const unsigned int msiof1_sync_e_pins[] = {
2619 static const unsigned int msiof1_sync_e_mux[] = {
2622 static const unsigned int msiof1_ss1_e_pins[] = {
2626 static const unsigned int msiof1_ss1_e_mux[] = {
2629 static const unsigned int msiof1_ss2_e_pins[] = {
2633 static const unsigned int msiof1_ss2_e_mux[] = {
2636 static const unsigned int msiof1_txd_e_pins[] = {
2640 static const unsigned int msiof1_txd_e_mux[] = {
2643 static const unsigned int msiof1_rxd_e_pins[] = {
2647 static const unsigned int msiof1_rxd_e_mux[] = {
2650 static const unsigned int msiof1_clk_f_pins[] = {
2654 static const unsigned int msiof1_clk_f_mux[] = {
2657 static const unsigned int msiof1_sync_f_pins[] = {
2661 static const unsigned int msiof1_sync_f_mux[] = {
2664 static const unsigned int msiof1_ss1_f_pins[] = {
2668 static const unsigned int msiof1_ss1_f_mux[] = {
2671 static const unsigned int msiof1_ss2_f_pins[] = {
2675 static const unsigned int msiof1_ss2_f_mux[] = {
2678 static const unsigned int msiof1_txd_f_pins[] = {
2682 static const unsigned int msiof1_txd_f_mux[] = {
2685 static const unsigned int msiof1_rxd_f_pins[] = {
2689 static const unsigned int msiof1_rxd_f_mux[] = {
2692 static const unsigned int msiof1_clk_g_pins[] = {
2696 static const unsigned int msiof1_clk_g_mux[] = {
2699 static const unsigned int msiof1_sync_g_pins[] = {
2703 static const unsigned int msiof1_sync_g_mux[] = {
2706 static const unsigned int msiof1_ss1_g_pins[] = {
2710 static const unsigned int msiof1_ss1_g_mux[] = {
2713 static const unsigned int msiof1_ss2_g_pins[] = {
2717 static const unsigned int msiof1_ss2_g_mux[] = {
2720 static const unsigned int msiof1_txd_g_pins[] = {
2724 static const unsigned int msiof1_txd_g_mux[] = {
2727 static const unsigned int msiof1_rxd_g_pins[] = {
2731 static const unsigned int msiof1_rxd_g_mux[] = {
2734 /* - MSIOF2 ----------------------------------------------------------------- */
2735 static const unsigned int msiof2_clk_a_pins[] = {
2739 static const unsigned int msiof2_clk_a_mux[] = {
2742 static const unsigned int msiof2_sync_a_pins[] = {
2746 static const unsigned int msiof2_sync_a_mux[] = {
2749 static const unsigned int msiof2_ss1_a_pins[] = {
2753 static const unsigned int msiof2_ss1_a_mux[] = {
2756 static const unsigned int msiof2_ss2_a_pins[] = {
2760 static const unsigned int msiof2_ss2_a_mux[] = {
2763 static const unsigned int msiof2_txd_a_pins[] = {
2767 static const unsigned int msiof2_txd_a_mux[] = {
2770 static const unsigned int msiof2_rxd_a_pins[] = {
2774 static const unsigned int msiof2_rxd_a_mux[] = {
2777 static const unsigned int msiof2_clk_b_pins[] = {
2781 static const unsigned int msiof2_clk_b_mux[] = {
2784 static const unsigned int msiof2_sync_b_pins[] = {
2788 static const unsigned int msiof2_sync_b_mux[] = {
2791 static const unsigned int msiof2_ss1_b_pins[] = {
2795 static const unsigned int msiof2_ss1_b_mux[] = {
2798 static const unsigned int msiof2_ss2_b_pins[] = {
2802 static const unsigned int msiof2_ss2_b_mux[] = {
2805 static const unsigned int msiof2_txd_b_pins[] = {
2809 static const unsigned int msiof2_txd_b_mux[] = {
2812 static const unsigned int msiof2_rxd_b_pins[] = {
2816 static const unsigned int msiof2_rxd_b_mux[] = {
2819 static const unsigned int msiof2_clk_c_pins[] = {
2823 static const unsigned int msiof2_clk_c_mux[] = {
2826 static const unsigned int msiof2_sync_c_pins[] = {
2830 static const unsigned int msiof2_sync_c_mux[] = {
2833 static const unsigned int msiof2_ss1_c_pins[] = {
2837 static const unsigned int msiof2_ss1_c_mux[] = {
2840 static const unsigned int msiof2_ss2_c_pins[] = {
2844 static const unsigned int msiof2_ss2_c_mux[] = {
2847 static const unsigned int msiof2_txd_c_pins[] = {
2851 static const unsigned int msiof2_txd_c_mux[] = {
2854 static const unsigned int msiof2_rxd_c_pins[] = {
2858 static const unsigned int msiof2_rxd_c_mux[] = {
2861 static const unsigned int msiof2_clk_d_pins[] = {
2865 static const unsigned int msiof2_clk_d_mux[] = {
2868 static const unsigned int msiof2_sync_d_pins[] = {
2872 static const unsigned int msiof2_sync_d_mux[] = {
2875 static const unsigned int msiof2_ss1_d_pins[] = {
2879 static const unsigned int msiof2_ss1_d_mux[] = {
2882 static const unsigned int msiof2_ss2_d_pins[] = {
2886 static const unsigned int msiof2_ss2_d_mux[] = {
2889 static const unsigned int msiof2_txd_d_pins[] = {
2893 static const unsigned int msiof2_txd_d_mux[] = {
2896 static const unsigned int msiof2_rxd_d_pins[] = {
2900 static const unsigned int msiof2_rxd_d_mux[] = {
2903 /* - MSIOF3 ----------------------------------------------------------------- */
2904 static const unsigned int msiof3_clk_a_pins[] = {
2908 static const unsigned int msiof3_clk_a_mux[] = {
2911 static const unsigned int msiof3_sync_a_pins[] = {
2915 static const unsigned int msiof3_sync_a_mux[] = {
2918 static const unsigned int msiof3_ss1_a_pins[] = {
2922 static const unsigned int msiof3_ss1_a_mux[] = {
2925 static const unsigned int msiof3_ss2_a_pins[] = {
2929 static const unsigned int msiof3_ss2_a_mux[] = {
2932 static const unsigned int msiof3_txd_a_pins[] = {
2936 static const unsigned int msiof3_txd_a_mux[] = {
2939 static const unsigned int msiof3_rxd_a_pins[] = {
2943 static const unsigned int msiof3_rxd_a_mux[] = {
2946 static const unsigned int msiof3_clk_b_pins[] = {
2950 static const unsigned int msiof3_clk_b_mux[] = {
2953 static const unsigned int msiof3_sync_b_pins[] = {
2957 static const unsigned int msiof3_sync_b_mux[] = {
2960 static const unsigned int msiof3_ss1_b_pins[] = {
2964 static const unsigned int msiof3_ss1_b_mux[] = {
2967 static const unsigned int msiof3_ss2_b_pins[] = {
2971 static const unsigned int msiof3_ss2_b_mux[] = {
2974 static const unsigned int msiof3_txd_b_pins[] = {
2978 static const unsigned int msiof3_txd_b_mux[] = {
2981 static const unsigned int msiof3_rxd_b_pins[] = {
2985 static const unsigned int msiof3_rxd_b_mux[] = {
2988 static const unsigned int msiof3_clk_c_pins[] = {
2992 static const unsigned int msiof3_clk_c_mux[] = {
2995 static const unsigned int msiof3_sync_c_pins[] = {
2999 static const unsigned int msiof3_sync_c_mux[] = {
3002 static const unsigned int msiof3_txd_c_pins[] = {
3006 static const unsigned int msiof3_txd_c_mux[] = {
3009 static const unsigned int msiof3_rxd_c_pins[] = {
3013 static const unsigned int msiof3_rxd_c_mux[] = {
3016 static const unsigned int msiof3_clk_d_pins[] = {
3020 static const unsigned int msiof3_clk_d_mux[] = {
3023 static const unsigned int msiof3_sync_d_pins[] = {
3027 static const unsigned int msiof3_sync_d_mux[] = {
3030 static const unsigned int msiof3_ss1_d_pins[] = {
3034 static const unsigned int msiof3_ss1_d_mux[] = {
3037 static const unsigned int msiof3_txd_d_pins[] = {
3041 static const unsigned int msiof3_txd_d_mux[] = {
3044 static const unsigned int msiof3_rxd_d_pins[] = {
3048 static const unsigned int msiof3_rxd_d_mux[] = {
3052 static const unsigned int msiof3_clk_e_pins[] = {
3056 static const unsigned int msiof3_clk_e_mux[] = {
3059 static const unsigned int msiof3_sync_e_pins[] = {
3063 static const unsigned int msiof3_sync_e_mux[] = {
3066 static const unsigned int msiof3_ss1_e_pins[] = {
3070 static const unsigned int msiof3_ss1_e_mux[] = {
3073 static const unsigned int msiof3_ss2_e_pins[] = {
3077 static const unsigned int msiof3_ss2_e_mux[] = {
3080 static const unsigned int msiof3_txd_e_pins[] = {
3084 static const unsigned int msiof3_txd_e_mux[] = {
3087 static const unsigned int msiof3_rxd_e_pins[] = {
3091 static const unsigned int msiof3_rxd_e_mux[] = {
3095 /* - PWM0 --------------------------------------------------------------------*/
3096 static const unsigned int pwm0_pins[] = {
3100 static const unsigned int pwm0_mux[] = {
3103 /* - PWM1 --------------------------------------------------------------------*/
3104 static const unsigned int pwm1_a_pins[] = {
3108 static const unsigned int pwm1_a_mux[] = {
3111 static const unsigned int pwm1_b_pins[] = {
3115 static const unsigned int pwm1_b_mux[] = {
3118 /* - PWM2 --------------------------------------------------------------------*/
3119 static const unsigned int pwm2_a_pins[] = {
3123 static const unsigned int pwm2_a_mux[] = {
3126 static const unsigned int pwm2_b_pins[] = {
3130 static const unsigned int pwm2_b_mux[] = {
3133 /* - PWM3 --------------------------------------------------------------------*/
3134 static const unsigned int pwm3_a_pins[] = {
3138 static const unsigned int pwm3_a_mux[] = {
3141 static const unsigned int pwm3_b_pins[] = {
3145 static const unsigned int pwm3_b_mux[] = {
3148 /* - PWM4 --------------------------------------------------------------------*/
3149 static const unsigned int pwm4_a_pins[] = {
3153 static const unsigned int pwm4_a_mux[] = {
3156 static const unsigned int pwm4_b_pins[] = {
3160 static const unsigned int pwm4_b_mux[] = {
3163 /* - PWM5 --------------------------------------------------------------------*/
3164 static const unsigned int pwm5_a_pins[] = {
3168 static const unsigned int pwm5_a_mux[] = {
3171 static const unsigned int pwm5_b_pins[] = {
3175 static const unsigned int pwm5_b_mux[] = {
3178 /* - PWM6 --------------------------------------------------------------------*/
3179 static const unsigned int pwm6_a_pins[] = {
3183 static const unsigned int pwm6_a_mux[] = {
3186 static const unsigned int pwm6_b_pins[] = {
3190 static const unsigned int pwm6_b_mux[] = {
3194 /* - SCIF0 ------------------------------------------------------------------ */
3195 static const unsigned int scif0_data_pins[] = {
3197 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3199 static const unsigned int scif0_data_mux[] = {
3202 static const unsigned int scif0_clk_pins[] = {
3206 static const unsigned int scif0_clk_mux[] = {
3209 static const unsigned int scif0_ctrl_pins[] = {
3211 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3213 static const unsigned int scif0_ctrl_mux[] = {
3214 RTS0_N_TANS_MARK, CTS0_N_MARK,
3216 /* - SCIF1 ------------------------------------------------------------------ */
3217 static const unsigned int scif1_data_a_pins[] = {
3219 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3221 static const unsigned int scif1_data_a_mux[] = {
3222 RX1_A_MARK, TX1_A_MARK,
3224 static const unsigned int scif1_clk_pins[] = {
3228 static const unsigned int scif1_clk_mux[] = {
3231 static const unsigned int scif1_ctrl_pins[] = {
3233 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3235 static const unsigned int scif1_ctrl_mux[] = {
3236 RTS1_N_TANS_MARK, CTS1_N_MARK,
3239 static const unsigned int scif1_data_b_pins[] = {
3241 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3243 static const unsigned int scif1_data_b_mux[] = {
3244 RX1_B_MARK, TX1_B_MARK,
3246 /* - SCIF2 ------------------------------------------------------------------ */
3247 static const unsigned int scif2_data_a_pins[] = {
3249 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3251 static const unsigned int scif2_data_a_mux[] = {
3252 RX2_A_MARK, TX2_A_MARK,
3254 static const unsigned int scif2_clk_pins[] = {
3258 static const unsigned int scif2_clk_mux[] = {
3261 static const unsigned int scif2_data_b_pins[] = {
3263 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3265 static const unsigned int scif2_data_b_mux[] = {
3266 RX2_B_MARK, TX2_B_MARK,
3268 /* - SCIF3 ------------------------------------------------------------------ */
3269 static const unsigned int scif3_data_a_pins[] = {
3271 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3273 static const unsigned int scif3_data_a_mux[] = {
3274 RX3_A_MARK, TX3_A_MARK,
3276 static const unsigned int scif3_clk_pins[] = {
3280 static const unsigned int scif3_clk_mux[] = {
3283 static const unsigned int scif3_ctrl_pins[] = {
3285 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3287 static const unsigned int scif3_ctrl_mux[] = {
3288 RTS3_N_TANS_MARK, CTS3_N_MARK,
3290 static const unsigned int scif3_data_b_pins[] = {
3292 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3294 static const unsigned int scif3_data_b_mux[] = {
3295 RX3_B_MARK, TX3_B_MARK,
3297 /* - SCIF4 ------------------------------------------------------------------ */
3298 static const unsigned int scif4_data_a_pins[] = {
3300 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3302 static const unsigned int scif4_data_a_mux[] = {
3303 RX4_A_MARK, TX4_A_MARK,
3305 static const unsigned int scif4_clk_a_pins[] = {
3309 static const unsigned int scif4_clk_a_mux[] = {
3312 static const unsigned int scif4_ctrl_a_pins[] = {
3314 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3316 static const unsigned int scif4_ctrl_a_mux[] = {
3317 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3319 static const unsigned int scif4_data_b_pins[] = {
3321 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3323 static const unsigned int scif4_data_b_mux[] = {
3324 RX4_B_MARK, TX4_B_MARK,
3326 static const unsigned int scif4_clk_b_pins[] = {
3330 static const unsigned int scif4_clk_b_mux[] = {
3333 static const unsigned int scif4_ctrl_b_pins[] = {
3335 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3337 static const unsigned int scif4_ctrl_b_mux[] = {
3338 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3340 static const unsigned int scif4_data_c_pins[] = {
3342 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3344 static const unsigned int scif4_data_c_mux[] = {
3345 RX4_C_MARK, TX4_C_MARK,
3347 static const unsigned int scif4_clk_c_pins[] = {
3351 static const unsigned int scif4_clk_c_mux[] = {
3354 static const unsigned int scif4_ctrl_c_pins[] = {
3356 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3358 static const unsigned int scif4_ctrl_c_mux[] = {
3359 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3361 /* - SCIF5 ------------------------------------------------------------------ */
3362 static const unsigned int scif5_data_a_pins[] = {
3364 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3366 static const unsigned int scif5_data_a_mux[] = {
3367 RX5_A_MARK, TX5_A_MARK,
3369 static const unsigned int scif5_clk_a_pins[] = {
3373 static const unsigned int scif5_clk_a_mux[] = {
3377 static const unsigned int scif5_data_b_pins[] = {
3379 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3381 static const unsigned int scif5_data_b_mux[] = {
3382 RX5_B_MARK, TX5_B_MARK,
3384 static const unsigned int scif5_clk_b_pins[] = {
3388 static const unsigned int scif5_clk_b_mux[] = {
3392 /* - SCIF Clock ------------------------------------------------------------- */
3393 static const unsigned int scif_clk_a_pins[] = {
3397 static const unsigned int scif_clk_a_mux[] = {
3400 static const unsigned int scif_clk_b_pins[] = {
3404 static const unsigned int scif_clk_b_mux[] = {
3408 /* - SDHI0 ------------------------------------------------------------------ */
3409 static const unsigned int sdhi0_data1_pins[] = {
3413 static const unsigned int sdhi0_data1_mux[] = {
3416 static const unsigned int sdhi0_data4_pins[] = {
3418 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3419 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3421 static const unsigned int sdhi0_data4_mux[] = {
3422 SD0_DAT0_MARK, SD0_DAT1_MARK,
3423 SD0_DAT2_MARK, SD0_DAT3_MARK,
3425 static const unsigned int sdhi0_ctrl_pins[] = {
3427 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3429 static const unsigned int sdhi0_ctrl_mux[] = {
3430 SD0_CLK_MARK, SD0_CMD_MARK,
3432 static const unsigned int sdhi0_cd_pins[] = {
3436 static const unsigned int sdhi0_cd_mux[] = {
3439 static const unsigned int sdhi0_wp_pins[] = {
3443 static const unsigned int sdhi0_wp_mux[] = {
3446 /* - SDHI1 ------------------------------------------------------------------ */
3447 static const unsigned int sdhi1_data1_pins[] = {
3451 static const unsigned int sdhi1_data1_mux[] = {
3454 static const unsigned int sdhi1_data4_pins[] = {
3456 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3457 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3459 static const unsigned int sdhi1_data4_mux[] = {
3460 SD1_DAT0_MARK, SD1_DAT1_MARK,
3461 SD1_DAT2_MARK, SD1_DAT3_MARK,
3463 static const unsigned int sdhi1_ctrl_pins[] = {
3465 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3467 static const unsigned int sdhi1_ctrl_mux[] = {
3468 SD1_CLK_MARK, SD1_CMD_MARK,
3470 static const unsigned int sdhi1_cd_pins[] = {
3474 static const unsigned int sdhi1_cd_mux[] = {
3477 static const unsigned int sdhi1_wp_pins[] = {
3481 static const unsigned int sdhi1_wp_mux[] = {
3484 /* - SDHI2 ------------------------------------------------------------------ */
3485 static const unsigned int sdhi2_data1_pins[] = {
3489 static const unsigned int sdhi2_data1_mux[] = {
3492 static const unsigned int sdhi2_data4_pins[] = {
3494 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3495 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3497 static const unsigned int sdhi2_data4_mux[] = {
3498 SD2_DAT0_MARK, SD2_DAT1_MARK,
3499 SD2_DAT2_MARK, SD2_DAT3_MARK,
3501 static const unsigned int sdhi2_data8_pins[] = {
3503 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3504 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3505 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3506 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3508 static const unsigned int sdhi2_data8_mux[] = {
3509 SD2_DAT0_MARK, SD2_DAT1_MARK,
3510 SD2_DAT2_MARK, SD2_DAT3_MARK,
3511 SD2_DAT4_MARK, SD2_DAT5_MARK,
3512 SD2_DAT6_MARK, SD2_DAT7_MARK,
3514 static const unsigned int sdhi2_ctrl_pins[] = {
3516 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3518 static const unsigned int sdhi2_ctrl_mux[] = {
3519 SD2_CLK_MARK, SD2_CMD_MARK,
3521 static const unsigned int sdhi2_cd_a_pins[] = {
3525 static const unsigned int sdhi2_cd_a_mux[] = {
3528 static const unsigned int sdhi2_cd_b_pins[] = {
3532 static const unsigned int sdhi2_cd_b_mux[] = {
3535 static const unsigned int sdhi2_wp_a_pins[] = {
3539 static const unsigned int sdhi2_wp_a_mux[] = {
3542 static const unsigned int sdhi2_wp_b_pins[] = {
3546 static const unsigned int sdhi2_wp_b_mux[] = {
3549 static const unsigned int sdhi2_ds_pins[] = {
3553 static const unsigned int sdhi2_ds_mux[] = {
3556 /* - SDHI3 ------------------------------------------------------------------ */
3557 static const unsigned int sdhi3_data1_pins[] = {
3561 static const unsigned int sdhi3_data1_mux[] = {
3564 static const unsigned int sdhi3_data4_pins[] = {
3566 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3567 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3569 static const unsigned int sdhi3_data4_mux[] = {
3570 SD3_DAT0_MARK, SD3_DAT1_MARK,
3571 SD3_DAT2_MARK, SD3_DAT3_MARK,
3573 static const unsigned int sdhi3_data8_pins[] = {
3575 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3576 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3577 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3578 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3580 static const unsigned int sdhi3_data8_mux[] = {
3581 SD3_DAT0_MARK, SD3_DAT1_MARK,
3582 SD3_DAT2_MARK, SD3_DAT3_MARK,
3583 SD3_DAT4_MARK, SD3_DAT5_MARK,
3584 SD3_DAT6_MARK, SD3_DAT7_MARK,
3586 static const unsigned int sdhi3_ctrl_pins[] = {
3588 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3590 static const unsigned int sdhi3_ctrl_mux[] = {
3591 SD3_CLK_MARK, SD3_CMD_MARK,
3593 static const unsigned int sdhi3_cd_pins[] = {
3597 static const unsigned int sdhi3_cd_mux[] = {
3600 static const unsigned int sdhi3_wp_pins[] = {
3604 static const unsigned int sdhi3_wp_mux[] = {
3607 static const unsigned int sdhi3_ds_pins[] = {
3611 static const unsigned int sdhi3_ds_mux[] = {
3615 /* - SSI -------------------------------------------------------------------- */
3616 static const unsigned int ssi0_data_pins[] = {
3620 static const unsigned int ssi0_data_mux[] = {
3623 static const unsigned int ssi01239_ctrl_pins[] = {
3625 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3627 static const unsigned int ssi01239_ctrl_mux[] = {
3628 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3630 static const unsigned int ssi1_data_a_pins[] = {
3634 static const unsigned int ssi1_data_a_mux[] = {
3637 static const unsigned int ssi1_data_b_pins[] = {
3641 static const unsigned int ssi1_data_b_mux[] = {
3644 static const unsigned int ssi1_ctrl_a_pins[] = {
3646 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3648 static const unsigned int ssi1_ctrl_a_mux[] = {
3649 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3651 static const unsigned int ssi1_ctrl_b_pins[] = {
3653 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3655 static const unsigned int ssi1_ctrl_b_mux[] = {
3656 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3658 static const unsigned int ssi2_data_a_pins[] = {
3662 static const unsigned int ssi2_data_a_mux[] = {
3665 static const unsigned int ssi2_data_b_pins[] = {
3669 static const unsigned int ssi2_data_b_mux[] = {
3672 static const unsigned int ssi2_ctrl_a_pins[] = {
3674 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3676 static const unsigned int ssi2_ctrl_a_mux[] = {
3677 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3679 static const unsigned int ssi2_ctrl_b_pins[] = {
3681 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3683 static const unsigned int ssi2_ctrl_b_mux[] = {
3684 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3686 static const unsigned int ssi3_data_pins[] = {
3690 static const unsigned int ssi3_data_mux[] = {
3693 static const unsigned int ssi349_ctrl_pins[] = {
3695 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3697 static const unsigned int ssi349_ctrl_mux[] = {
3698 SSI_SCK349_MARK, SSI_WS349_MARK,
3700 static const unsigned int ssi4_data_pins[] = {
3704 static const unsigned int ssi4_data_mux[] = {
3707 static const unsigned int ssi4_ctrl_pins[] = {
3709 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3711 static const unsigned int ssi4_ctrl_mux[] = {
3712 SSI_SCK4_MARK, SSI_WS4_MARK,
3714 static const unsigned int ssi5_data_pins[] = {
3718 static const unsigned int ssi5_data_mux[] = {
3721 static const unsigned int ssi5_ctrl_pins[] = {
3723 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3725 static const unsigned int ssi5_ctrl_mux[] = {
3726 SSI_SCK5_MARK, SSI_WS5_MARK,
3728 static const unsigned int ssi6_data_pins[] = {
3732 static const unsigned int ssi6_data_mux[] = {
3735 static const unsigned int ssi6_ctrl_pins[] = {
3737 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3739 static const unsigned int ssi6_ctrl_mux[] = {
3740 SSI_SCK6_MARK, SSI_WS6_MARK,
3742 static const unsigned int ssi7_data_pins[] = {
3746 static const unsigned int ssi7_data_mux[] = {
3749 static const unsigned int ssi78_ctrl_pins[] = {
3751 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3753 static const unsigned int ssi78_ctrl_mux[] = {
3754 SSI_SCK78_MARK, SSI_WS78_MARK,
3756 static const unsigned int ssi8_data_pins[] = {
3760 static const unsigned int ssi8_data_mux[] = {
3763 static const unsigned int ssi9_data_a_pins[] = {
3767 static const unsigned int ssi9_data_a_mux[] = {
3770 static const unsigned int ssi9_data_b_pins[] = {
3774 static const unsigned int ssi9_data_b_mux[] = {
3777 static const unsigned int ssi9_ctrl_a_pins[] = {
3779 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3781 static const unsigned int ssi9_ctrl_a_mux[] = {
3782 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3784 static const unsigned int ssi9_ctrl_b_pins[] = {
3786 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3788 static const unsigned int ssi9_ctrl_b_mux[] = {
3789 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3792 /* - USB0 ------------------------------------------------------------------- */
3793 static const unsigned int usb0_pins[] = {
3795 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3797 static const unsigned int usb0_mux[] = {
3798 USB0_PWEN_MARK, USB0_OVC_MARK,
3800 /* - USB1 ------------------------------------------------------------------- */
3801 static const unsigned int usb1_pins[] = {
3803 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3805 static const unsigned int usb1_mux[] = {
3806 USB1_PWEN_MARK, USB1_OVC_MARK,
3809 /* - USB30 ------------------------------------------------------------------ */
3810 static const unsigned int usb30_pins[] = {
3812 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3814 static const unsigned int usb30_mux[] = {
3815 USB30_PWEN_MARK, USB30_OVC_MARK,
3818 static const struct sh_pfc_pin_group pinmux_groups[] = {
3819 SH_PFC_PIN_GROUP(audio_clk_a_a),
3820 SH_PFC_PIN_GROUP(audio_clk_a_b),
3821 SH_PFC_PIN_GROUP(audio_clk_a_c),
3822 SH_PFC_PIN_GROUP(audio_clk_b_a),
3823 SH_PFC_PIN_GROUP(audio_clk_b_b),
3824 SH_PFC_PIN_GROUP(audio_clk_c_a),
3825 SH_PFC_PIN_GROUP(audio_clk_c_b),
3826 SH_PFC_PIN_GROUP(audio_clkout_a),
3827 SH_PFC_PIN_GROUP(audio_clkout_b),
3828 SH_PFC_PIN_GROUP(audio_clkout_c),
3829 SH_PFC_PIN_GROUP(audio_clkout_d),
3830 SH_PFC_PIN_GROUP(audio_clkout1_a),
3831 SH_PFC_PIN_GROUP(audio_clkout1_b),
3832 SH_PFC_PIN_GROUP(audio_clkout2_a),
3833 SH_PFC_PIN_GROUP(audio_clkout2_b),
3834 SH_PFC_PIN_GROUP(audio_clkout3_a),
3835 SH_PFC_PIN_GROUP(audio_clkout3_b),
3836 SH_PFC_PIN_GROUP(avb_link),
3837 SH_PFC_PIN_GROUP(avb_magic),
3838 SH_PFC_PIN_GROUP(avb_phy_int),
3839 SH_PFC_PIN_GROUP(avb_mdc),
3840 SH_PFC_PIN_GROUP(avb_mii),
3841 SH_PFC_PIN_GROUP(avb_avtp_pps),
3842 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3843 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3844 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3845 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3846 SH_PFC_PIN_GROUP(can0_data_a),
3847 SH_PFC_PIN_GROUP(can0_data_b),
3848 SH_PFC_PIN_GROUP(can1_data),
3849 SH_PFC_PIN_GROUP(can_clk),
3850 SH_PFC_PIN_GROUP(canfd0_data_a),
3851 SH_PFC_PIN_GROUP(canfd0_data_b),
3852 SH_PFC_PIN_GROUP(canfd1_data),
3853 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3854 SH_PFC_PIN_GROUP(drif0_data0_a),
3855 SH_PFC_PIN_GROUP(drif0_data1_a),
3856 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3857 SH_PFC_PIN_GROUP(drif0_data0_b),
3858 SH_PFC_PIN_GROUP(drif0_data1_b),
3859 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3860 SH_PFC_PIN_GROUP(drif0_data0_c),
3861 SH_PFC_PIN_GROUP(drif0_data1_c),
3862 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3863 SH_PFC_PIN_GROUP(drif1_data0_a),
3864 SH_PFC_PIN_GROUP(drif1_data1_a),
3865 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3866 SH_PFC_PIN_GROUP(drif1_data0_b),
3867 SH_PFC_PIN_GROUP(drif1_data1_b),
3868 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3869 SH_PFC_PIN_GROUP(drif1_data0_c),
3870 SH_PFC_PIN_GROUP(drif1_data1_c),
3871 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3872 SH_PFC_PIN_GROUP(drif2_data0_a),
3873 SH_PFC_PIN_GROUP(drif2_data1_a),
3874 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3875 SH_PFC_PIN_GROUP(drif2_data0_b),
3876 SH_PFC_PIN_GROUP(drif2_data1_b),
3877 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3878 SH_PFC_PIN_GROUP(drif3_data0_a),
3879 SH_PFC_PIN_GROUP(drif3_data1_a),
3880 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3881 SH_PFC_PIN_GROUP(drif3_data0_b),
3882 SH_PFC_PIN_GROUP(drif3_data1_b),
3883 SH_PFC_PIN_GROUP(du_rgb666),
3884 SH_PFC_PIN_GROUP(du_rgb888),
3885 SH_PFC_PIN_GROUP(du_clk_out_0),
3886 SH_PFC_PIN_GROUP(du_clk_out_1),
3887 SH_PFC_PIN_GROUP(du_sync),
3888 SH_PFC_PIN_GROUP(du_oddf),
3889 SH_PFC_PIN_GROUP(du_cde),
3890 SH_PFC_PIN_GROUP(du_disp),
3891 SH_PFC_PIN_GROUP(hscif0_data),
3892 SH_PFC_PIN_GROUP(hscif0_clk),
3893 SH_PFC_PIN_GROUP(hscif0_ctrl),
3894 SH_PFC_PIN_GROUP(hscif1_data_a),
3895 SH_PFC_PIN_GROUP(hscif1_clk_a),
3896 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3897 SH_PFC_PIN_GROUP(hscif1_data_b),
3898 SH_PFC_PIN_GROUP(hscif1_clk_b),
3899 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3900 SH_PFC_PIN_GROUP(hscif2_data_a),
3901 SH_PFC_PIN_GROUP(hscif2_clk_a),
3902 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3903 SH_PFC_PIN_GROUP(hscif2_data_b),
3904 SH_PFC_PIN_GROUP(hscif2_clk_b),
3905 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3906 SH_PFC_PIN_GROUP(hscif2_data_c),
3907 SH_PFC_PIN_GROUP(hscif2_clk_c),
3908 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3909 SH_PFC_PIN_GROUP(hscif3_data_a),
3910 SH_PFC_PIN_GROUP(hscif3_clk),
3911 SH_PFC_PIN_GROUP(hscif3_ctrl),
3912 SH_PFC_PIN_GROUP(hscif3_data_b),
3913 SH_PFC_PIN_GROUP(hscif3_data_c),
3914 SH_PFC_PIN_GROUP(hscif3_data_d),
3915 SH_PFC_PIN_GROUP(hscif4_data_a),
3916 SH_PFC_PIN_GROUP(hscif4_clk),
3917 SH_PFC_PIN_GROUP(hscif4_ctrl),
3918 SH_PFC_PIN_GROUP(hscif4_data_b),
3919 SH_PFC_PIN_GROUP(i2c1_a),
3920 SH_PFC_PIN_GROUP(i2c1_b),
3921 SH_PFC_PIN_GROUP(i2c2_a),
3922 SH_PFC_PIN_GROUP(i2c2_b),
3923 SH_PFC_PIN_GROUP(i2c6_a),
3924 SH_PFC_PIN_GROUP(i2c6_b),
3925 SH_PFC_PIN_GROUP(i2c6_c),
3926 SH_PFC_PIN_GROUP(msiof0_clk),
3927 SH_PFC_PIN_GROUP(msiof0_sync),
3928 SH_PFC_PIN_GROUP(msiof0_ss1),
3929 SH_PFC_PIN_GROUP(msiof0_ss2),
3930 SH_PFC_PIN_GROUP(msiof0_txd),
3931 SH_PFC_PIN_GROUP(msiof0_rxd),
3932 SH_PFC_PIN_GROUP(msiof1_clk_a),
3933 SH_PFC_PIN_GROUP(msiof1_sync_a),
3934 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3935 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3936 SH_PFC_PIN_GROUP(msiof1_txd_a),
3937 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3938 SH_PFC_PIN_GROUP(msiof1_clk_b),
3939 SH_PFC_PIN_GROUP(msiof1_sync_b),
3940 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3941 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3942 SH_PFC_PIN_GROUP(msiof1_txd_b),
3943 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3944 SH_PFC_PIN_GROUP(msiof1_clk_c),
3945 SH_PFC_PIN_GROUP(msiof1_sync_c),
3946 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3947 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3948 SH_PFC_PIN_GROUP(msiof1_txd_c),
3949 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3950 SH_PFC_PIN_GROUP(msiof1_clk_d),
3951 SH_PFC_PIN_GROUP(msiof1_sync_d),
3952 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3953 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3954 SH_PFC_PIN_GROUP(msiof1_txd_d),
3955 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3956 SH_PFC_PIN_GROUP(msiof1_clk_e),
3957 SH_PFC_PIN_GROUP(msiof1_sync_e),
3958 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3959 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3960 SH_PFC_PIN_GROUP(msiof1_txd_e),
3961 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3962 SH_PFC_PIN_GROUP(msiof1_clk_f),
3963 SH_PFC_PIN_GROUP(msiof1_sync_f),
3964 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3965 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3966 SH_PFC_PIN_GROUP(msiof1_txd_f),
3967 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3968 SH_PFC_PIN_GROUP(msiof1_clk_g),
3969 SH_PFC_PIN_GROUP(msiof1_sync_g),
3970 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3971 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3972 SH_PFC_PIN_GROUP(msiof1_txd_g),
3973 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3974 SH_PFC_PIN_GROUP(msiof2_clk_a),
3975 SH_PFC_PIN_GROUP(msiof2_sync_a),
3976 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3977 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3978 SH_PFC_PIN_GROUP(msiof2_txd_a),
3979 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3980 SH_PFC_PIN_GROUP(msiof2_clk_b),
3981 SH_PFC_PIN_GROUP(msiof2_sync_b),
3982 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3983 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3984 SH_PFC_PIN_GROUP(msiof2_txd_b),
3985 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3986 SH_PFC_PIN_GROUP(msiof2_clk_c),
3987 SH_PFC_PIN_GROUP(msiof2_sync_c),
3988 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3989 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3990 SH_PFC_PIN_GROUP(msiof2_txd_c),
3991 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3992 SH_PFC_PIN_GROUP(msiof2_clk_d),
3993 SH_PFC_PIN_GROUP(msiof2_sync_d),
3994 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3995 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3996 SH_PFC_PIN_GROUP(msiof2_txd_d),
3997 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3998 SH_PFC_PIN_GROUP(msiof3_clk_a),
3999 SH_PFC_PIN_GROUP(msiof3_sync_a),
4000 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4001 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4002 SH_PFC_PIN_GROUP(msiof3_txd_a),
4003 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4004 SH_PFC_PIN_GROUP(msiof3_clk_b),
4005 SH_PFC_PIN_GROUP(msiof3_sync_b),
4006 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4007 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4008 SH_PFC_PIN_GROUP(msiof3_txd_b),
4009 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4010 SH_PFC_PIN_GROUP(msiof3_clk_c),
4011 SH_PFC_PIN_GROUP(msiof3_sync_c),
4012 SH_PFC_PIN_GROUP(msiof3_txd_c),
4013 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4014 SH_PFC_PIN_GROUP(msiof3_clk_d),
4015 SH_PFC_PIN_GROUP(msiof3_sync_d),
4016 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4017 SH_PFC_PIN_GROUP(msiof3_txd_d),
4018 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4019 SH_PFC_PIN_GROUP(msiof3_clk_e),
4020 SH_PFC_PIN_GROUP(msiof3_sync_e),
4021 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4022 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4023 SH_PFC_PIN_GROUP(msiof3_txd_e),
4024 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4025 SH_PFC_PIN_GROUP(pwm0),
4026 SH_PFC_PIN_GROUP(pwm1_a),
4027 SH_PFC_PIN_GROUP(pwm1_b),
4028 SH_PFC_PIN_GROUP(pwm2_a),
4029 SH_PFC_PIN_GROUP(pwm2_b),
4030 SH_PFC_PIN_GROUP(pwm3_a),
4031 SH_PFC_PIN_GROUP(pwm3_b),
4032 SH_PFC_PIN_GROUP(pwm4_a),
4033 SH_PFC_PIN_GROUP(pwm4_b),
4034 SH_PFC_PIN_GROUP(pwm5_a),
4035 SH_PFC_PIN_GROUP(pwm5_b),
4036 SH_PFC_PIN_GROUP(pwm6_a),
4037 SH_PFC_PIN_GROUP(pwm6_b),
4038 SH_PFC_PIN_GROUP(scif0_data),
4039 SH_PFC_PIN_GROUP(scif0_clk),
4040 SH_PFC_PIN_GROUP(scif0_ctrl),
4041 SH_PFC_PIN_GROUP(scif1_data_a),
4042 SH_PFC_PIN_GROUP(scif1_clk),
4043 SH_PFC_PIN_GROUP(scif1_ctrl),
4044 SH_PFC_PIN_GROUP(scif1_data_b),
4045 SH_PFC_PIN_GROUP(scif2_data_a),
4046 SH_PFC_PIN_GROUP(scif2_clk),
4047 SH_PFC_PIN_GROUP(scif2_data_b),
4048 SH_PFC_PIN_GROUP(scif3_data_a),
4049 SH_PFC_PIN_GROUP(scif3_clk),
4050 SH_PFC_PIN_GROUP(scif3_ctrl),
4051 SH_PFC_PIN_GROUP(scif3_data_b),
4052 SH_PFC_PIN_GROUP(scif4_data_a),
4053 SH_PFC_PIN_GROUP(scif4_clk_a),
4054 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4055 SH_PFC_PIN_GROUP(scif4_data_b),
4056 SH_PFC_PIN_GROUP(scif4_clk_b),
4057 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4058 SH_PFC_PIN_GROUP(scif4_data_c),
4059 SH_PFC_PIN_GROUP(scif4_clk_c),
4060 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4061 SH_PFC_PIN_GROUP(scif5_data_a),
4062 SH_PFC_PIN_GROUP(scif5_clk_a),
4063 SH_PFC_PIN_GROUP(scif5_data_b),
4064 SH_PFC_PIN_GROUP(scif5_clk_b),
4065 SH_PFC_PIN_GROUP(scif_clk_a),
4066 SH_PFC_PIN_GROUP(scif_clk_b),
4067 SH_PFC_PIN_GROUP(sdhi0_data1),
4068 SH_PFC_PIN_GROUP(sdhi0_data4),
4069 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4070 SH_PFC_PIN_GROUP(sdhi0_cd),
4071 SH_PFC_PIN_GROUP(sdhi0_wp),
4072 SH_PFC_PIN_GROUP(sdhi1_data1),
4073 SH_PFC_PIN_GROUP(sdhi1_data4),
4074 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4075 SH_PFC_PIN_GROUP(sdhi1_cd),
4076 SH_PFC_PIN_GROUP(sdhi1_wp),
4077 SH_PFC_PIN_GROUP(sdhi2_data1),
4078 SH_PFC_PIN_GROUP(sdhi2_data4),
4079 SH_PFC_PIN_GROUP(sdhi2_data8),
4080 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4081 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4082 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4083 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4084 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4085 SH_PFC_PIN_GROUP(sdhi2_ds),
4086 SH_PFC_PIN_GROUP(sdhi3_data1),
4087 SH_PFC_PIN_GROUP(sdhi3_data4),
4088 SH_PFC_PIN_GROUP(sdhi3_data8),
4089 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4090 SH_PFC_PIN_GROUP(sdhi3_cd),
4091 SH_PFC_PIN_GROUP(sdhi3_wp),
4092 SH_PFC_PIN_GROUP(sdhi3_ds),
4093 SH_PFC_PIN_GROUP(ssi0_data),
4094 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4095 SH_PFC_PIN_GROUP(ssi1_data_a),
4096 SH_PFC_PIN_GROUP(ssi1_data_b),
4097 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4098 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4099 SH_PFC_PIN_GROUP(ssi2_data_a),
4100 SH_PFC_PIN_GROUP(ssi2_data_b),
4101 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4102 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4103 SH_PFC_PIN_GROUP(ssi3_data),
4104 SH_PFC_PIN_GROUP(ssi349_ctrl),
4105 SH_PFC_PIN_GROUP(ssi4_data),
4106 SH_PFC_PIN_GROUP(ssi4_ctrl),
4107 SH_PFC_PIN_GROUP(ssi5_data),
4108 SH_PFC_PIN_GROUP(ssi5_ctrl),
4109 SH_PFC_PIN_GROUP(ssi6_data),
4110 SH_PFC_PIN_GROUP(ssi6_ctrl),
4111 SH_PFC_PIN_GROUP(ssi7_data),
4112 SH_PFC_PIN_GROUP(ssi78_ctrl),
4113 SH_PFC_PIN_GROUP(ssi8_data),
4114 SH_PFC_PIN_GROUP(ssi9_data_a),
4115 SH_PFC_PIN_GROUP(ssi9_data_b),
4116 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4117 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4118 SH_PFC_PIN_GROUP(usb0),
4119 SH_PFC_PIN_GROUP(usb1),
4120 SH_PFC_PIN_GROUP(usb30),
4123 static const char * const audio_clk_groups[] = {
4143 static const char * const avb_groups[] = {
4151 "avb_avtp_capture_a",
4153 "avb_avtp_capture_b",
4156 static const char * const can0_groups[] = {
4161 static const char * const can1_groups[] = {
4165 static const char * const can_clk_groups[] = {
4169 static const char * const canfd0_groups[] = {
4174 static const char * const canfd1_groups[] = {
4178 static const char * const drif0_groups[] = {
4190 static const char * const drif1_groups[] = {
4202 static const char * const drif2_groups[] = {
4211 static const char * const drif3_groups[] = {
4220 static const char * const du_groups[] = {
4231 static const char * const hscif0_groups[] = {
4237 static const char * const hscif1_groups[] = {
4246 static const char * const hscif2_groups[] = {
4258 static const char * const hscif3_groups[] = {
4267 static const char * const hscif4_groups[] = {
4274 static const char * const i2c1_groups[] = {
4279 static const char * const i2c2_groups[] = {
4284 static const char * const i2c6_groups[] = {
4290 static const char * const msiof0_groups[] = {
4299 static const char * const msiof1_groups[] = {
4344 static const char * const msiof2_groups[] = {
4371 static const char * const msiof3_groups[] = {
4401 static const char * const pwm0_groups[] = {
4405 static const char * const pwm1_groups[] = {
4410 static const char * const pwm2_groups[] = {
4415 static const char * const pwm3_groups[] = {
4420 static const char * const pwm4_groups[] = {
4425 static const char * const pwm5_groups[] = {
4430 static const char * const pwm6_groups[] = {
4435 static const char * const scif0_groups[] = {
4441 static const char * const scif1_groups[] = {
4448 static const char * const scif2_groups[] = {
4454 static const char * const scif3_groups[] = {
4461 static const char * const scif4_groups[] = {
4473 static const char * const scif5_groups[] = {
4480 static const char * const scif_clk_groups[] = {
4485 static const char * const sdhi0_groups[] = {
4493 static const char * const sdhi1_groups[] = {
4501 static const char * const sdhi2_groups[] = {
4513 static const char * const sdhi3_groups[] = {
4523 static const char * const ssi_groups[] = {
4551 static const char * const usb0_groups[] = {
4555 static const char * const usb1_groups[] = {
4559 static const char * const usb30_groups[] = {
4563 static const struct sh_pfc_function pinmux_functions[] = {
4564 SH_PFC_FUNCTION(audio_clk),
4565 SH_PFC_FUNCTION(avb),
4566 SH_PFC_FUNCTION(can0),
4567 SH_PFC_FUNCTION(can1),
4568 SH_PFC_FUNCTION(can_clk),
4569 SH_PFC_FUNCTION(canfd0),
4570 SH_PFC_FUNCTION(canfd1),
4571 SH_PFC_FUNCTION(drif0),
4572 SH_PFC_FUNCTION(drif1),
4573 SH_PFC_FUNCTION(drif2),
4574 SH_PFC_FUNCTION(drif3),
4575 SH_PFC_FUNCTION(du),
4576 SH_PFC_FUNCTION(hscif0),
4577 SH_PFC_FUNCTION(hscif1),
4578 SH_PFC_FUNCTION(hscif2),
4579 SH_PFC_FUNCTION(hscif3),
4580 SH_PFC_FUNCTION(hscif4),
4581 SH_PFC_FUNCTION(i2c1),
4582 SH_PFC_FUNCTION(i2c2),
4583 SH_PFC_FUNCTION(i2c6),
4584 SH_PFC_FUNCTION(msiof0),
4585 SH_PFC_FUNCTION(msiof1),
4586 SH_PFC_FUNCTION(msiof2),
4587 SH_PFC_FUNCTION(msiof3),
4588 SH_PFC_FUNCTION(pwm0),
4589 SH_PFC_FUNCTION(pwm1),
4590 SH_PFC_FUNCTION(pwm2),
4591 SH_PFC_FUNCTION(pwm3),
4592 SH_PFC_FUNCTION(pwm4),
4593 SH_PFC_FUNCTION(pwm5),
4594 SH_PFC_FUNCTION(pwm6),
4595 SH_PFC_FUNCTION(scif0),
4596 SH_PFC_FUNCTION(scif1),
4597 SH_PFC_FUNCTION(scif2),
4598 SH_PFC_FUNCTION(scif3),
4599 SH_PFC_FUNCTION(scif4),
4600 SH_PFC_FUNCTION(scif5),
4601 SH_PFC_FUNCTION(scif_clk),
4602 SH_PFC_FUNCTION(sdhi0),
4603 SH_PFC_FUNCTION(sdhi1),
4604 SH_PFC_FUNCTION(sdhi2),
4605 SH_PFC_FUNCTION(sdhi3),
4606 SH_PFC_FUNCTION(ssi),
4607 SH_PFC_FUNCTION(usb0),
4608 SH_PFC_FUNCTION(usb1),
4609 SH_PFC_FUNCTION(usb30),
4612 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4613 #define F_(x, y) FN_##y
4614 #define FM(x) FN_##x
4615 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4632 GP_0_15_FN, GPSR0_15,
4633 GP_0_14_FN, GPSR0_14,
4634 GP_0_13_FN, GPSR0_13,
4635 GP_0_12_FN, GPSR0_12,
4636 GP_0_11_FN, GPSR0_11,
4637 GP_0_10_FN, GPSR0_10,
4647 GP_0_0_FN, GPSR0_0, }
4649 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4653 GP_1_28_FN, GPSR1_28,
4654 GP_1_27_FN, GPSR1_27,
4655 GP_1_26_FN, GPSR1_26,
4656 GP_1_25_FN, GPSR1_25,
4657 GP_1_24_FN, GPSR1_24,
4658 GP_1_23_FN, GPSR1_23,
4659 GP_1_22_FN, GPSR1_22,
4660 GP_1_21_FN, GPSR1_21,
4661 GP_1_20_FN, GPSR1_20,
4662 GP_1_19_FN, GPSR1_19,
4663 GP_1_18_FN, GPSR1_18,
4664 GP_1_17_FN, GPSR1_17,
4665 GP_1_16_FN, GPSR1_16,
4666 GP_1_15_FN, GPSR1_15,
4667 GP_1_14_FN, GPSR1_14,
4668 GP_1_13_FN, GPSR1_13,
4669 GP_1_12_FN, GPSR1_12,
4670 GP_1_11_FN, GPSR1_11,
4671 GP_1_10_FN, GPSR1_10,
4681 GP_1_0_FN, GPSR1_0, }
4683 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4701 GP_2_14_FN, GPSR2_14,
4702 GP_2_13_FN, GPSR2_13,
4703 GP_2_12_FN, GPSR2_12,
4704 GP_2_11_FN, GPSR2_11,
4705 GP_2_10_FN, GPSR2_10,
4715 GP_2_0_FN, GPSR2_0, }
4717 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4734 GP_3_15_FN, GPSR3_15,
4735 GP_3_14_FN, GPSR3_14,
4736 GP_3_13_FN, GPSR3_13,
4737 GP_3_12_FN, GPSR3_12,
4738 GP_3_11_FN, GPSR3_11,
4739 GP_3_10_FN, GPSR3_10,
4749 GP_3_0_FN, GPSR3_0, }
4751 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4766 GP_4_17_FN, GPSR4_17,
4767 GP_4_16_FN, GPSR4_16,
4768 GP_4_15_FN, GPSR4_15,
4769 GP_4_14_FN, GPSR4_14,
4770 GP_4_13_FN, GPSR4_13,
4771 GP_4_12_FN, GPSR4_12,
4772 GP_4_11_FN, GPSR4_11,
4773 GP_4_10_FN, GPSR4_10,
4783 GP_4_0_FN, GPSR4_0, }
4785 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4792 GP_5_25_FN, GPSR5_25,
4793 GP_5_24_FN, GPSR5_24,
4794 GP_5_23_FN, GPSR5_23,
4795 GP_5_22_FN, GPSR5_22,
4796 GP_5_21_FN, GPSR5_21,
4797 GP_5_20_FN, GPSR5_20,
4798 GP_5_19_FN, GPSR5_19,
4799 GP_5_18_FN, GPSR5_18,
4800 GP_5_17_FN, GPSR5_17,
4801 GP_5_16_FN, GPSR5_16,
4802 GP_5_15_FN, GPSR5_15,
4803 GP_5_14_FN, GPSR5_14,
4804 GP_5_13_FN, GPSR5_13,
4805 GP_5_12_FN, GPSR5_12,
4806 GP_5_11_FN, GPSR5_11,
4807 GP_5_10_FN, GPSR5_10,
4817 GP_5_0_FN, GPSR5_0, }
4819 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4820 GP_6_31_FN, GPSR6_31,
4821 GP_6_30_FN, GPSR6_30,
4822 GP_6_29_FN, GPSR6_29,
4823 GP_6_28_FN, GPSR6_28,
4824 GP_6_27_FN, GPSR6_27,
4825 GP_6_26_FN, GPSR6_26,
4826 GP_6_25_FN, GPSR6_25,
4827 GP_6_24_FN, GPSR6_24,
4828 GP_6_23_FN, GPSR6_23,
4829 GP_6_22_FN, GPSR6_22,
4830 GP_6_21_FN, GPSR6_21,
4831 GP_6_20_FN, GPSR6_20,
4832 GP_6_19_FN, GPSR6_19,
4833 GP_6_18_FN, GPSR6_18,
4834 GP_6_17_FN, GPSR6_17,
4835 GP_6_16_FN, GPSR6_16,
4836 GP_6_15_FN, GPSR6_15,
4837 GP_6_14_FN, GPSR6_14,
4838 GP_6_13_FN, GPSR6_13,
4839 GP_6_12_FN, GPSR6_12,
4840 GP_6_11_FN, GPSR6_11,
4841 GP_6_10_FN, GPSR6_10,
4851 GP_6_0_FN, GPSR6_0, }
4853 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4885 GP_7_0_FN, GPSR7_0, }
4891 #define FM(x) FN_##x,
4892 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4902 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4912 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4922 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4932 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4942 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4952 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4962 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4967 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4972 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4982 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4992 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5002 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5012 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5022 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5032 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5042 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5052 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5062 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5072 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5073 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5074 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5075 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5076 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5077 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5078 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5086 #define FM(x) FN_##x,
5087 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5088 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5089 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5100 0, 0, /* RESERVED 15 */
5109 /* RESERVED 2, 1, 0 */
5110 0, 0, 0, 0, 0, 0, 0, 0 }
5112 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5113 2, 3, 1, 2, 3, 1, 1, 2, 1,
5114 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5130 0, 0, 0, 0, /* RESERVED 8, 7 */
5139 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5140 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5156 /* RESERVED 15, 14, 13, 12 */
5157 0, 0, 0, 0, 0, 0, 0, 0,
5158 0, 0, 0, 0, 0, 0, 0, 0,
5159 /* RESERVED 11, 10, 9, 8 */
5160 0, 0, 0, 0, 0, 0, 0, 0,
5161 0, 0, 0, 0, 0, 0, 0, 0,
5162 /* RESERVED 7, 6, 5, 4 */
5163 0, 0, 0, 0, 0, 0, 0, 0,
5164 0, 0, 0, 0, 0, 0, 0, 0,
5165 /* RESERVED 3, 2, 1 */
5166 0, 0, 0, 0, 0, 0, 0, 0,
5172 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5173 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5174 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5175 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5176 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5177 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5178 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5179 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5180 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5181 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5183 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5184 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5185 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5186 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5187 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5188 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5189 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5190 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5191 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5193 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5194 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5195 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5196 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5197 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5198 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5199 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5200 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5201 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5203 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5204 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5205 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5206 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5207 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5208 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5209 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5210 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5211 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5213 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5214 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5215 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5216 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5217 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5218 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5219 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5220 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5221 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5223 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5224 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5225 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5226 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5227 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5228 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5229 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5230 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5231 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5233 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5234 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5235 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5236 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5237 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5238 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5239 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5240 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5241 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5243 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5244 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5245 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5246 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5247 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5248 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5249 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5250 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5251 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5253 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5254 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5255 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5256 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5257 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5258 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5259 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5260 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5261 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5263 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5264 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5265 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5266 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5267 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5268 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5269 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5270 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5271 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5273 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5274 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5275 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5276 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5277 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5278 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5279 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5280 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5281 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5283 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5284 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5285 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5286 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5287 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5288 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5289 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5290 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5291 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5293 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5294 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
5295 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
5296 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5298 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5299 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5300 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5301 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5302 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5303 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5304 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5305 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5306 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5308 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5309 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5310 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5311 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5312 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5313 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5314 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5315 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5316 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5318 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5319 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5320 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5321 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5322 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5323 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5324 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5325 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5326 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5328 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5329 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5330 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5331 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5332 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5333 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5334 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5335 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5336 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5338 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5339 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5340 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5341 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5342 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5343 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5344 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5345 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5346 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5348 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5349 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5350 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5351 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5352 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5353 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5354 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5355 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5356 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5358 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5359 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5360 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5361 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5362 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5363 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5364 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5365 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5366 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5368 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5369 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5370 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5371 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5372 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5373 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5374 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5375 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5376 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5378 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5379 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5380 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5381 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5382 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5383 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5384 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5385 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5386 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5388 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5389 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5390 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5391 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5392 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5393 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5394 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5395 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5396 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5398 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5399 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5400 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5401 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5402 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5403 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5404 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5405 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5406 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5408 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5409 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5410 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5411 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5412 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5413 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5414 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5415 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5420 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5424 *pocctrl = 0xe6060380;
5426 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5429 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5430 bit = (pin & 0x1f) + 12;
5435 #define PUEN 0xe6060400
5436 #define PUD 0xe6060440
5446 static const struct sh_pfc_bias_info bias_info[] = {
5447 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
5448 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
5449 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
5450 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
5451 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
5452 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
5453 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
5454 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
5455 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
5456 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
5457 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
5458 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
5459 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
5460 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
5461 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
5462 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
5463 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
5464 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
5465 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
5466 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
5467 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
5468 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
5469 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
5470 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
5471 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
5472 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
5473 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
5474 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
5475 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
5476 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
5477 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
5478 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
5480 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
5481 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
5482 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
5483 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
5484 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
5485 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
5486 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
5487 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
5488 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
5489 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
5490 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
5491 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
5492 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
5493 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
5494 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
5495 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
5496 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
5497 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
5498 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
5499 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
5500 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
5501 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
5502 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
5503 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
5504 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
5505 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
5506 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
5507 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
5508 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
5509 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
5510 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
5511 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
5513 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
5514 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
5515 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */
5516 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
5517 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
5518 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
5519 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
5520 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
5521 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
5522 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
5523 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
5524 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
5525 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
5526 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
5527 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
5528 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
5529 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
5530 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
5531 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
5532 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
5533 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
5534 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
5535 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
5536 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
5537 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
5538 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
5539 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
5540 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
5541 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
5542 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
5543 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
5544 { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */
5546 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
5547 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
5548 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
5549 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
5550 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
5551 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
5552 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
5553 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
5554 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
5555 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
5556 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
5557 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
5558 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
5559 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
5560 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
5561 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
5562 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
5563 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
5564 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
5565 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
5566 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
5567 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
5568 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
5570 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
5571 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
5572 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
5573 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
5574 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
5575 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */
5576 /* bit 1 n/a on M3*/
5577 { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */
5579 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
5580 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
5581 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
5582 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
5583 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
5584 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
5585 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
5586 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
5587 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
5588 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
5589 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
5590 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
5591 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
5592 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
5593 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
5594 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
5595 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
5596 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
5597 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
5598 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
5599 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
5600 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
5601 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
5602 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
5603 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
5604 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
5605 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
5606 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
5607 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
5608 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
5609 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
5610 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
5612 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
5613 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
5614 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
5615 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
5616 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
5617 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
5618 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
5619 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
5620 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
5621 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
5622 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
5623 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
5624 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
5625 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
5626 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
5627 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
5628 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
5629 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
5630 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
5631 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
5632 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
5633 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
5634 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
5635 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
5636 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
5637 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
5638 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
5639 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
5640 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
5641 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
5642 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
5643 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
5645 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */
5646 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */
5647 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
5648 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
5649 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
5650 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
5651 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
5654 static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
5657 const struct sh_pfc_bias_info *info;
5661 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5663 return PIN_CONFIG_BIAS_DISABLE;
5666 bit = BIT(info->bit);
5668 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
5669 return PIN_CONFIG_BIAS_DISABLE;
5670 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
5671 return PIN_CONFIG_BIAS_PULL_UP;
5673 return PIN_CONFIG_BIAS_PULL_DOWN;
5676 static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5679 const struct sh_pfc_bias_info *info;
5684 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5689 bit = BIT(info->bit);
5691 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5692 if (bias != PIN_CONFIG_BIAS_DISABLE)
5695 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
5696 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5699 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
5700 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
5703 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
5704 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
5705 .get_bias = r8a7796_pinmux_get_bias,
5706 .set_bias = r8a7796_pinmux_set_bias,
5709 const struct sh_pfc_soc_info r8a7796_pinmux_info = {
5710 .name = "r8a77960_pfc",
5711 .ops = &r8a7796_pinmux_ops,
5712 .unlock_reg = 0xe6060000, /* PMMR */
5714 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5716 .pins = pinmux_pins,
5717 .nr_pins = ARRAY_SIZE(pinmux_pins),
5718 .groups = pinmux_groups,
5719 .nr_groups = ARRAY_SIZE(pinmux_groups),
5720 .functions = pinmux_functions,
5721 .nr_functions = ARRAY_SIZE(pinmux_functions),
5723 .cfg_regs = pinmux_config_regs,
5724 .drive_regs = pinmux_drive_regs,
5726 .pinmux_data = pinmux_data,
5727 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
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