git.sur5r.net Git - u-boot/blob - drivers/pinctrl/renesas/pfc-r8a77970.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R8A77970 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2016 Renesas Electronics Corp.
   6  *
   7  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   8  *
   9  * R-Car Gen3 processor support - PFC hardware block.
  10  *
  11  * Copyright (C) 2015  Renesas Electronics Corporation
  12  */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <dm/pinctrl.h>
  18 #include <linux/kernel.h>
  19
  20 #include "sh_pfc.h"
  21
  22 #define CPU_ALL_PORT(fn, sfx)                                           \
  23         PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  24         PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  25         PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  26         PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH |      \
  27                                    SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  28         PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),       \
  29         PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
  30 /*
  31  * F_() : just information
  32  * FM() : macro for FN_xxx / xxx_MARK
  33  */
  34
  35 /* GPSR0 */
  36 #define GPSR0_21        F_(DU_EXODDF_DU_ODDF_DISP_CDE,  IP2_23_20)
  37 #define GPSR0_20        F_(DU_EXVSYNC_DU_VSYNC,         IP2_19_16)
  38 #define GPSR0_19        F_(DU_EXHSYNC_DU_HSYNC,         IP2_15_12)
  39 #define GPSR0_18        F_(DU_DOTCLKOUT,                IP2_11_8)
  40 #define GPSR0_17        F_(DU_DB7,                      IP2_7_4)
  41 #define GPSR0_16        F_(DU_DB6,                      IP2_3_0)
  42 #define GPSR0_15        F_(DU_DB5,                      IP1_31_28)
  43 #define GPSR0_14        F_(DU_DB4,                      IP1_27_24)
  44 #define GPSR0_13        F_(DU_DB3,                      IP1_23_20)
  45 #define GPSR0_12        F_(DU_DB2,                      IP1_19_16)
  46 #define GPSR0_11        F_(DU_DG7,                      IP1_15_12)
  47 #define GPSR0_10        F_(DU_DG6,                      IP1_11_8)
  48 #define GPSR0_9         F_(DU_DG5,                      IP1_7_4)
  49 #define GPSR0_8         F_(DU_DG4,                      IP1_3_0)
  50 #define GPSR0_7         F_(DU_DG3,                      IP0_31_28)
  51 #define GPSR0_6         F_(DU_DG2,                      IP0_27_24)
  52 #define GPSR0_5         F_(DU_DR7,                      IP0_23_20)
  53 #define GPSR0_4         F_(DU_DR6,                      IP0_19_16)
  54 #define GPSR0_3         F_(DU_DR5,                      IP0_15_12)
  55 #define GPSR0_2         F_(DU_DR4,                      IP0_11_8)
  56 #define GPSR0_1         F_(DU_DR3,                      IP0_7_4)
  57 #define GPSR0_0         F_(DU_DR2,                      IP0_3_0)
  58
  59 /* GPSR1 */
  60 #define GPSR1_27        F_(DIGRF_CLKOUT,        IP8_27_24)
  61 #define GPSR1_26        F_(DIGRF_CLKIN,         IP8_23_20)
  62 #define GPSR1_25        F_(CANFD_CLK_A,         IP8_19_16)
  63 #define GPSR1_24        F_(CANFD1_RX,           IP8_15_12)
  64 #define GPSR1_23        F_(CANFD1_TX,           IP8_11_8)
  65 #define GPSR1_22        F_(CANFD0_RX_A,         IP8_7_4)
  66 #define GPSR1_21        F_(CANFD0_TX_A,         IP8_3_0)
  67 #define GPSR1_20        F_(AVB0_AVTP_CAPTURE,   IP7_31_28)
  68 #define GPSR1_19        FM(AVB0_AVTP_MATCH)
  69 #define GPSR1_18        FM(AVB0_LINK)
  70 #define GPSR1_17        FM(AVB0_PHY_INT)
  71 #define GPSR1_16        FM(AVB0_MAGIC)
  72 #define GPSR1_15        FM(AVB0_MDC)
  73 #define GPSR1_14        FM(AVB0_MDIO)
  74 #define GPSR1_13        FM(AVB0_TXCREFCLK)
  75 #define GPSR1_12        FM(AVB0_TD3)
  76 #define GPSR1_11        FM(AVB0_TD2)
  77 #define GPSR1_10        FM(AVB0_TD1)
  78 #define GPSR1_9         FM(AVB0_TD0)
  79 #define GPSR1_8         FM(AVB0_TXC)
  80 #define GPSR1_7         FM(AVB0_TX_CTL)
  81 #define GPSR1_6         FM(AVB0_RD3)
  82 #define GPSR1_5         FM(AVB0_RD2)
  83 #define GPSR1_4         FM(AVB0_RD1)
  84 #define GPSR1_3         FM(AVB0_RD0)
  85 #define GPSR1_2         FM(AVB0_RXC)
  86 #define GPSR1_1         FM(AVB0_RX_CTL)
  87 #define GPSR1_0         F_(IRQ0,                IP2_27_24)
  88
  89 /* GPSR2 */
  90 #define GPSR2_16        F_(VI0_FIELD,           IP4_31_28)
  91 #define GPSR2_15        F_(VI0_DATA11,          IP4_27_24)
  92 #define GPSR2_14        F_(VI0_DATA10,          IP4_23_20)
  93 #define GPSR2_13        F_(VI0_DATA9,           IP4_19_16)
  94 #define GPSR2_12        F_(VI0_DATA8,           IP4_15_12)
  95 #define GPSR2_11        F_(VI0_DATA7,           IP4_11_8)
  96 #define GPSR2_10        F_(VI0_DATA6,           IP4_7_4)
  97 #define GPSR2_9         F_(VI0_DATA5,           IP4_3_0)
  98 #define GPSR2_8         F_(VI0_DATA4,           IP3_31_28)
  99 #define GPSR2_7         F_(VI0_DATA3,           IP3_27_24)
 100 #define GPSR2_6         F_(VI0_DATA2,           IP3_23_20)
 101 #define GPSR2_5         F_(VI0_DATA1,           IP3_19_16)
 102 #define GPSR2_4         F_(VI0_DATA0,           IP3_15_12)
 103 #define GPSR2_3         F_(VI0_VSYNC_N,         IP3_11_8)
 104 #define GPSR2_2         F_(VI0_HSYNC_N,         IP3_7_4)
 105 #define GPSR2_1         F_(VI0_CLKENB,          IP3_3_0)
 106 #define GPSR2_0         F_(VI0_CLK,             IP2_31_28)
 107
 108 /* GPSR3 */
 109 #define GPSR3_16        F_(VI1_FIELD,           IP7_3_0)
 110 #define GPSR3_15        F_(VI1_DATA11,          IP6_31_28)
 111 #define GPSR3_14        F_(VI1_DATA10,          IP6_27_24)
 112 #define GPSR3_13        F_(VI1_DATA9,           IP6_23_20)
 113 #define GPSR3_12        F_(VI1_DATA8,           IP6_19_16)
 114 #define GPSR3_11        F_(VI1_DATA7,           IP6_15_12)
 115 #define GPSR3_10        F_(VI1_DATA6,           IP6_11_8)
 116 #define GPSR3_9         F_(VI1_DATA5,           IP6_7_4)
 117 #define GPSR3_8         F_(VI1_DATA4,           IP6_3_0)
 118 #define GPSR3_7         F_(VI1_DATA3,           IP5_31_28)
 119 #define GPSR3_6         F_(VI1_DATA2,           IP5_27_24)
 120 #define GPSR3_5         F_(VI1_DATA1,           IP5_23_20)
 121 #define GPSR3_4         F_(VI1_DATA0,           IP5_19_16)
 122 #define GPSR3_3         F_(VI1_VSYNC_N,         IP5_15_12)
 123 #define GPSR3_2         F_(VI1_HSYNC_N,         IP5_11_8)
 124 #define GPSR3_1         F_(VI1_CLKENB,          IP5_7_4)
 125 #define GPSR3_0         F_(VI1_CLK,             IP5_3_0)
 126
 127 /* GPSR4 */
 128 #define GPSR4_5         F_(SDA2,                IP7_27_24)
 129 #define GPSR4_4         F_(SCL2,                IP7_23_20)
 130 #define GPSR4_3         F_(SDA1,                IP7_19_16)
 131 #define GPSR4_2         F_(SCL1,                IP7_15_12)
 132 #define GPSR4_1         F_(SDA0,                IP7_11_8)
 133 #define GPSR4_0         F_(SCL0,                IP7_7_4)
 134
 135 /* GPSR5 */
 136 #define GPSR5_14        FM(RPC_INT_N)
 137 #define GPSR5_13        FM(RPC_WP_N)
 138 #define GPSR5_12        FM(RPC_RESET_N)
 139 #define GPSR5_11        FM(QSPI1_SSL)
 140 #define GPSR5_10        FM(QSPI1_IO3)
 141 #define GPSR5_9         FM(QSPI1_IO2)
 142 #define GPSR5_8         FM(QSPI1_MISO_IO1)
 143 #define GPSR5_7         FM(QSPI1_MOSI_IO0)
 144 #define GPSR5_6         FM(QSPI1_SPCLK)
 145 #define GPSR5_5         FM(QSPI0_SSL)
 146 #define GPSR5_4         FM(QSPI0_IO3)
 147 #define GPSR5_3         FM(QSPI0_IO2)
 148 #define GPSR5_2         FM(QSPI0_MISO_IO1)
 149 #define GPSR5_1         FM(QSPI0_MOSI_IO0)
 150 #define GPSR5_0         FM(QSPI0_SPCLK)
 151
 152
 153 /* IPSRx */             /* 0 */                         /* 1 */                 /* 2 */         /* 3 */         /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 */         /* A */         /* B */         /* C */         /* D */         /* E */         /* F */
 154 #define IP0_3_0         FM(DU_DR2)                      FM(HSCK0)               F_(0, 0)        FM(A0)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 155 #define IP0_7_4         FM(DU_DR3)                      FM(HRTS0_N)             F_(0, 0)        FM(A1)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 156 #define IP0_11_8        FM(DU_DR4)                      FM(HCTS0_N)             F_(0, 0)        FM(A2)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 157 #define IP0_15_12       FM(DU_DR5)                      FM(HTX0)                F_(0, 0)        FM(A3)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 158 #define IP0_19_16       FM(DU_DR6)                      FM(MSIOF3_RXD)          F_(0, 0)        FM(A4)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 159 #define IP0_23_20       FM(DU_DR7)                      FM(MSIOF3_TXD)          F_(0, 0)        FM(A5)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 160 #define IP0_27_24       FM(DU_DG2)                      FM(MSIOF3_SS1)          F_(0, 0)        FM(A6)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 161 #define IP0_31_28       FM(DU_DG3)                      FM(MSIOF3_SS2)          F_(0, 0)        FM(A7)          FM(PWMFSW0)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 162 #define IP1_3_0         FM(DU_DG4)                      F_(0, 0)                F_(0, 0)        FM(A8)          FM(FSO_CFE_0_N_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 163 #define IP1_7_4         FM(DU_DG5)                      F_(0, 0)                F_(0, 0)        FM(A9)          FM(FSO_CFE_1_N_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 164 #define IP1_11_8        FM(DU_DG6)                      F_(0, 0)                F_(0, 0)        FM(A10)         FM(FSO_TOE_N_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 165 #define IP1_15_12       FM(DU_DG7)                      F_(0, 0)                F_(0, 0)        FM(A11)         FM(IRQ1)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 166 #define IP1_19_16       FM(DU_DB2)                      F_(0, 0)                F_(0, 0)        FM(A12)         FM(IRQ2)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 167 #define IP1_23_20       FM(DU_DB3)                      F_(0, 0)                F_(0, 0)        FM(A13)         FM(FXR_CLKOUT1)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 168 #define IP1_27_24       FM(DU_DB4)                      F_(0, 0)                F_(0, 0)        FM(A14)         FM(FXR_CLKOUT2)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 169 #define IP1_31_28       FM(DU_DB5)                      F_(0, 0)                F_(0, 0)        FM(A15)         FM(FXR_TXENA_N)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 170 #define IP2_3_0         FM(DU_DB6)                      F_(0, 0)                F_(0, 0)        FM(A16)         FM(FXR_TXENB_N)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 171 #define IP2_7_4         FM(DU_DB7)                      F_(0, 0)                F_(0, 0)        FM(A17)         FM(STPWT_EXTFXR)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 172 #define IP2_11_8        FM(DU_DOTCLKOUT)                FM(SCIF_CLK_A)          F_(0, 0)        FM(A18)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 173 #define IP2_15_12       FM(DU_EXHSYNC_DU_HSYNC)         FM(HRX0)                F_(0, 0)        FM(A19)         FM(IRQ3)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 174 #define IP2_19_16       FM(DU_EXVSYNC_DU_VSYNC)         FM(MSIOF3_SCK)          F_(0, 0)        FM(A20)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 175 #define IP2_23_20       FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(MSIOF3_SYNC)         F_(0, 0)        FM(A21)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 176 #define IP2_27_24       FM(IRQ0)                        FM(CC5_OSCOUT)          F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 177 #define IP2_31_28       FM(VI0_CLK)                     FM(MSIOF2_SCK)          FM(SCK3)        F_(0, 0)        FM(HSCK3)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 178 #define IP3_3_0         FM(VI0_CLKENB)                  FM(MSIOF2_RXD)          FM(RX3)         FM(RD_WR_N)     FM(HCTS3_N)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 179 #define IP3_7_4         FM(VI0_HSYNC_N)                 FM(MSIOF2_TXD)          FM(TX3)         F_(0, 0)        FM(HRTS3_N)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 180 #define IP3_11_8        FM(VI0_VSYNC_N)                 FM(MSIOF2_SYNC)         FM(CTS3_N)      F_(0, 0)        FM(HTX3)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 181 #define IP3_15_12       FM(VI0_DATA0)                   FM(MSIOF2_SS1)          FM(RTS3_N_TANS) F_(0, 0)        FM(HRX3)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 182 #define IP3_19_16       FM(VI0_DATA1)                   FM(MSIOF2_SS2)          FM(SCK1)        F_(0, 0)        FM(SPEEDIN_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 183 #define IP3_23_20       FM(VI0_DATA2)                   FM(AVB0_AVTP_PPS)       FM(SDA3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 184 #define IP3_27_24       FM(VI0_DATA3)                   FM(HSCK1)               FM(SCL3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 185 #define IP3_31_28       FM(VI0_DATA4)                   FM(HRTS1_N)             FM(RX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 186 #define IP4_3_0         FM(VI0_DATA5)                   FM(HCTS1_N)             FM(TX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 187 #define IP4_7_4         FM(VI0_DATA6)                   FM(HTX1)                FM(CTS1_N)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 188 #define IP4_11_8        FM(VI0_DATA7)                   FM(HRX1)                FM(RTS1_N_TANS) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 189 #define IP4_15_12       FM(VI0_DATA8)                   FM(HSCK2)               FM(PWM0_A)      FM(A22)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 190 #define IP4_19_16       FM(VI0_DATA9)                   FM(HCTS2_N)             FM(PWM1_A)      FM(A23)         FM(FSO_CFE_0_N_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 191 #define IP4_23_20       FM(VI0_DATA10)                  FM(HRTS2_N)             FM(PWM2_A)      FM(A24)         FM(FSO_CFE_1_N_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 192 #define IP4_27_24       FM(VI0_DATA11)                  FM(HTX2)                FM(PWM3_A)      FM(A25)         FM(FSO_TOE_N_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 193 #define IP4_31_28       FM(VI0_FIELD)                   FM(HRX2)                FM(PWM4_A)      FM(CS1_N_A26)   FM(FSCLKST2_N_A)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 194 #define IP5_3_0         FM(VI1_CLK)                     FM(MSIOF1_RXD)          F_(0, 0)        FM(CS0_N)       F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 195 #define IP5_7_4         FM(VI1_CLKENB)                  FM(MSIOF1_TXD)          F_(0, 0)        FM(D0)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 196 #define IP5_11_8        FM(VI1_HSYNC_N)                 FM(MSIOF1_SCK)          F_(0, 0)        FM(D1)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 197 #define IP5_15_12       FM(VI1_VSYNC_N)                 FM(MSIOF1_SYNC)         F_(0, 0)        FM(D2)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 198 #define IP5_19_16       FM(VI1_DATA0)                   FM(MSIOF1_SS1)          F_(0, 0)        FM(D3)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 199 #define IP5_23_20       FM(VI1_DATA1)                   FM(MSIOF1_SS2)          F_(0, 0)        FM(D4)          FM(MMC_CMD)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 200 #define IP5_27_24       FM(VI1_DATA2)                   FM(CANFD0_TX_B)         F_(0, 0)        FM(D5)          FM(MMC_D0)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 201 #define IP5_31_28       FM(VI1_DATA3)                   FM(CANFD0_RX_B)         F_(0, 0)        FM(D6)          FM(MMC_D1)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 202 #define IP6_3_0         FM(VI1_DATA4)                   FM(CANFD_CLK_B)         F_(0, 0)        FM(D7)          FM(MMC_D2)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 203 #define IP6_7_4         FM(VI1_DATA5)                   F_(0,0)                 FM(SCK4)        FM(D8)          FM(MMC_D3)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 204 #define IP6_11_8        FM(VI1_DATA6)                   F_(0,0)                 FM(RX4)         FM(D9)          FM(MMC_CLK)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 205 #define IP6_15_12       FM(VI1_DATA7)                   F_(0,0)                 FM(TX4)         FM(D10)         FM(MMC_D4)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 206 #define IP6_19_16       FM(VI1_DATA8)                   F_(0,0)                 FM(CTS4_N)      FM(D11)         FM(MMC_D5)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 207 #define IP6_23_20       FM(VI1_DATA9)                   F_(0,0)                 FM(RTS4_N_TANS) FM(D12)         FM(MMC_D6)              FM(SCL3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 208 #define IP6_27_24       FM(VI1_DATA10)                  F_(0,0)                 F_(0, 0)        FM(D13)         FM(MMC_D7)              FM(SDA3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 209 #define IP6_31_28       FM(VI1_DATA11)                  FM(SCL4)                FM(IRQ4)        FM(D14)         FM(MMC_WP)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 210 #define IP7_3_0         FM(VI1_FIELD)                   FM(SDA4)                FM(IRQ5)        FM(D15)         FM(MMC_CD)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 211 #define IP7_7_4         FM(SCL0)                        FM(DU_DR0)              FM(TPU0TO0)     FM(CLKOUT)      F_(0, 0)                FM(MSIOF0_RXD)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 212 #define IP7_11_8        FM(SDA0)                        FM(DU_DR1)              FM(TPU0TO1)     FM(BS_N)        FM(SCK0)                FM(MSIOF0_TXD)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 213 #define IP7_15_12       FM(SCL1)                        FM(DU_DG0)              FM(TPU0TO2)     FM(RD_N)        FM(CTS0_N)              FM(MSIOF0_SCK)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 214 #define IP7_19_16       FM(SDA1)                        FM(DU_DG1)              FM(TPU0TO3)     FM(WE0_N)       FM(RTS0_N_TANS)         FM(MSIOF0_SYNC) F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 215 #define IP7_23_20       FM(SCL2)                        FM(DU_DB0)              FM(TCLK1_A)     FM(WE1_N)       FM(RX0)                 FM(MSIOF0_SS1)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 216 #define IP7_27_24       FM(SDA2)                        FM(DU_DB1)              FM(TCLK2_A)     FM(EX_WAIT0)    FM(TX0)                 FM(MSIOF0_SS2)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 217 #define IP7_31_28       FM(AVB0_AVTP_CAPTURE)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(FSCLKST2_N_B)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 218 #define IP8_3_0         FM(CANFD0_TX_A)                 FM(FXR_TXDA)            FM(PWM0_B)      FM(DU_DISP)     FM(FSCLKST2_N_C)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 219 #define IP8_7_4         FM(CANFD0_RX_A)                 FM(RXDA_EXTFXR)         FM(PWM1_B)      FM(DU_CDE)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 220 #define IP8_11_8        FM(CANFD1_TX)                   FM(FXR_TXDB)            FM(PWM2_B)      FM(TCLK1_B)     FM(TX1_B)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 221 #define IP8_15_12       FM(CANFD1_RX)                   FM(RXDB_EXTFXR)         FM(PWM3_B)      FM(TCLK2_B)     FM(RX1_B)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 222 #define IP8_19_16       FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)      FM(SPEEDIN_B)   FM(SCIF_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 223 #define IP8_23_20       FM(DIGRF_CLKIN)                 FM(DIGRF_CLKEN_IN)      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 224 #define IP8_27_24       FM(DIGRF_CLKOUT)                FM(DIGRF_CLKEN_OUT)     F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 225 #define IP8_31_28       F_(0, 0)                        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 226
 227 #define PINMUX_GPSR     \
 228 \
 229                 GPSR1_27 \
 230                 GPSR1_26 \
 231                 GPSR1_25 \
 232                 GPSR1_24 \
 233                 GPSR1_23 \
 234                 GPSR1_22 \
 235 GPSR0_21        GPSR1_21 \
 236 GPSR0_20        GPSR1_20 \
 237 GPSR0_19        GPSR1_19 \
 238 GPSR0_18        GPSR1_18 \
 239 GPSR0_17        GPSR1_17 \
 240 GPSR0_16        GPSR1_16        GPSR2_16        GPSR3_16 \
 241 GPSR0_15        GPSR1_15        GPSR2_15        GPSR3_15 \
 242 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14                        GPSR5_14 \
 243 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13                        GPSR5_13 \
 244 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12                        GPSR5_12 \
 245 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11                        GPSR5_11 \
 246 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10                        GPSR5_10 \
 247 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9                         GPSR5_9 \
 248 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8                         GPSR5_8 \
 249 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7                         GPSR5_7 \
 250 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6                         GPSR5_6 \
 251 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5 \
 252 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4 \
 253 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3 \
 254 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2 \
 255 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1 \
 256 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0
 257
 258 #define PINMUX_IPSR     \
 259 \
 260 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 261 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 262 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 263 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 264 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 265 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 266 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 267 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 268 \
 269 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 270 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 271 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 272 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 273 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 274 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 275 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 276 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 277 \
 278 FM(IP8_3_0)     IP8_3_0 \
 279 FM(IP8_7_4)     IP8_7_4 \
 280 FM(IP8_11_8)    IP8_11_8 \
 281 FM(IP8_15_12)   IP8_15_12 \
 282 FM(IP8_19_16)   IP8_19_16 \
 283 FM(IP8_23_20)   IP8_23_20 \
 284 FM(IP8_27_24)   IP8_27_24 \
 285 FM(IP8_31_28)   IP8_31_28
 286
 287 /*
 288                         Set Value = H'0                 Set Value = H'1
 289 Register        Function        Pin                     Function        Pin
 290 ------------------------------------------------------------
 291 sel_i2c3        SDA3_A          VI0_DATA2       SDA3_B          VI1_DATA10
 292                 SCL3_A          VI0_DATA3       SCL3_B          VI1_DATA9
 293 sel_hscif0      HSCIF0_A        SCIF_CLK        HSCIF0_B        SCIF_CLK
 294 sel_scif1       SCIF1_A         RX1             SCIF1_B         TX1
 295                 SCIF1_A         TX1             SCIF1_B         RX1
 296 sel_canfd0      CANFD0_A        CANFD0_TX       CANFD0_B        CANFD0_TX
 297                 CANFD0_A        CANFD0_RX       CANFD0_B        CANFD0_RX
 298                 CANFD0_A        CANFD_CLK       CANFD0_B        CANFD_CLK
 299 sel_pwm4        PWM4_A          PWM4            PWM4_B          PWM4
 300 sel_pwm3        PWM3_A          PWM3            PWM3_B          PWM3
 301 sel_pwm2        PWM2_A          PWM2            PWM2_B          PWM2
 302 sel_pwm1        PWM1_A          PWM1            PWM1_B          PWM1
 303 sel_pwm0        PWM0_A          PWM0            PWM0_B          PWM0
 304 sel_rfso        RFSO_A          FSO_CFE_0_N     RFSO_B          FSO_CFE_0_N
 305                 RFSO_A          FSO_CFE_1_N     RFSO_B          FSO_CFE_1_N
 306                 RFSO_A          FSO_TOE_N       RFSO_B          FSO_TOE_N
 307 sel_rsp         RSP_A           SPEEDIN         RSP_B           SPEEDIN
 308 sel_tmu         TMU_A           TCLK1           TMU_B           TCLK1
 309                 TMU_A           TCLK2           TMU_B           TCLK2
 310 */
 311 /* MOD_SEL0 */          /* 0 */                 /* 1 */                 /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
 312 #define MOD_SEL0_11     FM(SEL_I2C3_0)          FM(SEL_I2C3_1)
 313 #define MOD_SEL0_10     FM(SEL_HSCIF0_0)        FM(SEL_HSCIF0_1)
 314 #define MOD_SEL0_9      FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 315 #define MOD_SEL0_8      FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 316 #define MOD_SEL0_7      FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 317 #define MOD_SEL0_6      FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 318 #define MOD_SEL0_5      FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 319 #define MOD_SEL0_4      FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 320 #define MOD_SEL0_3      FM(SEL_PWM0_0)          FM(SEL_PWM0_1)
 321 #define MOD_SEL0_2      FM(SEL_RFSO_0)          FM(SEL_RFSO_1)
 322 #define MOD_SEL0_1      FM(SEL_RSP_0)           FM(SEL_RSP_1)
 323 #define MOD_SEL0_0      FM(SEL_TMU_0)           FM(SEL_TMU_1)
 324
 325 #define PINMUX_MOD_SELS \
 326 \
 327 MOD_SEL0_11 \
 328 MOD_SEL0_10 \
 329 MOD_SEL0_9 \
 330 MOD_SEL0_8 \
 331 MOD_SEL0_7 \
 332 MOD_SEL0_6 \
 333 MOD_SEL0_5 \
 334 MOD_SEL0_4 \
 335 MOD_SEL0_3 \
 336 MOD_SEL0_2 \
 337 MOD_SEL0_1 \
 338 MOD_SEL0_0
 339
 340 enum {
 341         PINMUX_RESERVED = 0,
 342
 343         PINMUX_DATA_BEGIN,
 344         GP_ALL(DATA),
 345         PINMUX_DATA_END,
 346
 347 #define F_(x, y)
 348 #define FM(x)   FN_##x,
 349         PINMUX_FUNCTION_BEGIN,
 350         GP_ALL(FN),
 351         PINMUX_GPSR
 352         PINMUX_IPSR
 353         PINMUX_MOD_SELS
 354         PINMUX_FUNCTION_END,
 355 #undef F_
 356 #undef FM
 357
 358 #define F_(x, y)
 359 #define FM(x)   x##_MARK,
 360         PINMUX_MARK_BEGIN,
 361         PINMUX_GPSR
 362         PINMUX_IPSR
 363         PINMUX_MOD_SELS
 364         PINMUX_MARK_END,
 365 #undef F_
 366 #undef FM
 367 };
 368
 369 static const u16 pinmux_data[] = {
 370         PINMUX_DATA_GP_ALL(),
 371
 372         PINMUX_SINGLE(AVB0_RX_CTL),
 373         PINMUX_SINGLE(AVB0_RXC),
 374         PINMUX_SINGLE(AVB0_RD0),
 375         PINMUX_SINGLE(AVB0_RD1),
 376         PINMUX_SINGLE(AVB0_RD2),
 377         PINMUX_SINGLE(AVB0_RD3),
 378         PINMUX_SINGLE(AVB0_TX_CTL),
 379         PINMUX_SINGLE(AVB0_TXC),
 380         PINMUX_SINGLE(AVB0_TD0),
 381         PINMUX_SINGLE(AVB0_TD1),
 382         PINMUX_SINGLE(AVB0_TD2),
 383         PINMUX_SINGLE(AVB0_TD3),
 384         PINMUX_SINGLE(AVB0_TXCREFCLK),
 385         PINMUX_SINGLE(AVB0_MDIO),
 386         PINMUX_SINGLE(AVB0_MDC),
 387         PINMUX_SINGLE(AVB0_MAGIC),
 388         PINMUX_SINGLE(AVB0_PHY_INT),
 389         PINMUX_SINGLE(AVB0_LINK),
 390         PINMUX_SINGLE(AVB0_AVTP_MATCH),
 391
 392         PINMUX_SINGLE(QSPI0_SPCLK),
 393         PINMUX_SINGLE(QSPI0_MOSI_IO0),
 394         PINMUX_SINGLE(QSPI0_MISO_IO1),
 395         PINMUX_SINGLE(QSPI0_IO2),
 396         PINMUX_SINGLE(QSPI0_IO3),
 397         PINMUX_SINGLE(QSPI0_SSL),
 398         PINMUX_SINGLE(QSPI1_SPCLK),
 399         PINMUX_SINGLE(QSPI1_MOSI_IO0),
 400         PINMUX_SINGLE(QSPI1_MISO_IO1),
 401         PINMUX_SINGLE(QSPI1_IO2),
 402         PINMUX_SINGLE(QSPI1_IO3),
 403         PINMUX_SINGLE(QSPI1_SSL),
 404         PINMUX_SINGLE(RPC_RESET_N),
 405         PINMUX_SINGLE(RPC_WP_N),
 406         PINMUX_SINGLE(RPC_INT_N),
 407
 408         /* IPSR0 */
 409         PINMUX_IPSR_GPSR(IP0_3_0,       DU_DR2),
 410         PINMUX_IPSR_GPSR(IP0_3_0,       HSCK0),
 411         PINMUX_IPSR_GPSR(IP0_3_0,       A0),
 412
 413         PINMUX_IPSR_GPSR(IP0_7_4,       DU_DR3),
 414         PINMUX_IPSR_GPSR(IP0_7_4,       HRTS0_N),
 415         PINMUX_IPSR_GPSR(IP0_7_4,       A1),
 416
 417         PINMUX_IPSR_GPSR(IP0_11_8,      DU_DR4),
 418         PINMUX_IPSR_GPSR(IP0_11_8,      HCTS0_N),
 419         PINMUX_IPSR_GPSR(IP0_11_8,      A2),
 420
 421         PINMUX_IPSR_GPSR(IP0_15_12,     DU_DR5),
 422         PINMUX_IPSR_GPSR(IP0_15_12,     HTX0),
 423         PINMUX_IPSR_GPSR(IP0_15_12,     A3),
 424
 425         PINMUX_IPSR_GPSR(IP0_19_16,     DU_DR6),
 426         PINMUX_IPSR_GPSR(IP0_19_16,     MSIOF3_RXD),
 427         PINMUX_IPSR_GPSR(IP0_19_16,     A4),
 428
 429         PINMUX_IPSR_GPSR(IP0_23_20,     DU_DR7),
 430         PINMUX_IPSR_GPSR(IP0_23_20,     MSIOF3_TXD),
 431         PINMUX_IPSR_GPSR(IP0_23_20,     A5),
 432
 433         PINMUX_IPSR_GPSR(IP0_27_24,     DU_DG2),
 434         PINMUX_IPSR_GPSR(IP0_27_24,     MSIOF3_SS1),
 435         PINMUX_IPSR_GPSR(IP0_27_24,     A6),
 436
 437         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DG3),
 438         PINMUX_IPSR_GPSR(IP0_31_28,     MSIOF3_SS2),
 439         PINMUX_IPSR_GPSR(IP0_31_28,     A7),
 440         PINMUX_IPSR_GPSR(IP0_31_28,     PWMFSW0),
 441
 442         /* IPSR1 */
 443         PINMUX_IPSR_GPSR(IP1_3_0,       DU_DG4),
 444         PINMUX_IPSR_GPSR(IP1_3_0,       A8),
 445         PINMUX_IPSR_MSEL(IP1_3_0,       FSO_CFE_0_N_A,  SEL_RFSO_0),
 446
 447         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DG5),
 448         PINMUX_IPSR_GPSR(IP1_7_4,       A9),
 449         PINMUX_IPSR_MSEL(IP1_7_4,       FSO_CFE_1_N_A,  SEL_RFSO_0),
 450
 451         PINMUX_IPSR_GPSR(IP1_11_8,      DU_DG6),
 452         PINMUX_IPSR_GPSR(IP1_11_8,      A10),
 453         PINMUX_IPSR_MSEL(IP1_11_8,      FSO_TOE_N_A,    SEL_RFSO_0),
 454
 455         PINMUX_IPSR_GPSR(IP1_15_12,     DU_DG7),
 456         PINMUX_IPSR_GPSR(IP1_15_12,     A11),
 457         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ1),
 458
 459         PINMUX_IPSR_GPSR(IP1_19_16,     DU_DB2),
 460         PINMUX_IPSR_GPSR(IP1_19_16,     A12),
 461         PINMUX_IPSR_GPSR(IP1_19_16,     IRQ2),
 462
 463         PINMUX_IPSR_GPSR(IP1_23_20,     DU_DB3),
 464         PINMUX_IPSR_GPSR(IP1_23_20,     A13),
 465         PINMUX_IPSR_GPSR(IP1_23_20,     FXR_CLKOUT1),
 466
 467         PINMUX_IPSR_GPSR(IP1_27_24,     DU_DB4),
 468         PINMUX_IPSR_GPSR(IP1_27_24,     A14),
 469         PINMUX_IPSR_GPSR(IP1_27_24,     FXR_CLKOUT2),
 470
 471         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB5),
 472         PINMUX_IPSR_GPSR(IP1_31_28,     A15),
 473         PINMUX_IPSR_GPSR(IP1_31_28,     FXR_TXENA_N),
 474
 475         /* IPSR2 */
 476         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB6),
 477         PINMUX_IPSR_GPSR(IP2_3_0,       A16),
 478         PINMUX_IPSR_GPSR(IP2_3_0,       FXR_TXENB_N),
 479
 480         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB7),
 481         PINMUX_IPSR_GPSR(IP2_7_4,       A17),
 482         PINMUX_IPSR_GPSR(IP2_7_4,       STPWT_EXTFXR),
 483
 484         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DOTCLKOUT),
 485         PINMUX_IPSR_MSEL(IP2_11_8,      SCIF_CLK_A,     SEL_HSCIF0_0),
 486         PINMUX_IPSR_GPSR(IP2_11_8,      A18),
 487
 488         PINMUX_IPSR_GPSR(IP2_15_12,     DU_EXHSYNC_DU_HSYNC),
 489         PINMUX_IPSR_GPSR(IP2_15_12,     HRX0),
 490         PINMUX_IPSR_GPSR(IP2_15_12,     A19),
 491         PINMUX_IPSR_GPSR(IP2_15_12,     IRQ3),
 492
 493         PINMUX_IPSR_GPSR(IP2_19_16,     DU_EXVSYNC_DU_VSYNC),
 494         PINMUX_IPSR_GPSR(IP2_19_16,     MSIOF3_SCK),
 495         PINMUX_IPSR_GPSR(IP2_19_16,     A20),
 496
 497         PINMUX_IPSR_GPSR(IP2_23_20,     DU_EXODDF_DU_ODDF_DISP_CDE),
 498         PINMUX_IPSR_GPSR(IP2_23_20,     MSIOF3_SYNC),
 499         PINMUX_IPSR_GPSR(IP2_23_20,     A21),
 500
 501         PINMUX_IPSR_GPSR(IP2_27_24,     IRQ0),
 502         PINMUX_IPSR_GPSR(IP2_27_24,     CC5_OSCOUT),
 503
 504         PINMUX_IPSR_GPSR(IP2_31_28,     VI0_CLK),
 505         PINMUX_IPSR_GPSR(IP2_31_28,     MSIOF2_SCK),
 506         PINMUX_IPSR_GPSR(IP2_31_28,     SCK3),
 507         PINMUX_IPSR_GPSR(IP2_31_28,     HSCK3),
 508
 509         /* IPSR3 */
 510         PINMUX_IPSR_GPSR(IP3_3_0,       VI0_CLKENB),
 511         PINMUX_IPSR_GPSR(IP3_3_0,       MSIOF2_RXD),
 512         PINMUX_IPSR_GPSR(IP3_3_0,       RX3),
 513         PINMUX_IPSR_GPSR(IP3_3_0,       RD_WR_N),
 514         PINMUX_IPSR_GPSR(IP3_3_0,       HCTS3_N),
 515
 516         PINMUX_IPSR_GPSR(IP3_7_4,       VI0_HSYNC_N),
 517         PINMUX_IPSR_GPSR(IP3_7_4,       MSIOF2_TXD),
 518         PINMUX_IPSR_GPSR(IP3_7_4,       TX3),
 519         PINMUX_IPSR_GPSR(IP3_7_4,       HRTS3_N),
 520
 521         PINMUX_IPSR_GPSR(IP3_11_8,      VI0_VSYNC_N),
 522         PINMUX_IPSR_GPSR(IP3_11_8,      MSIOF2_SYNC),
 523         PINMUX_IPSR_GPSR(IP3_11_8,      CTS3_N),
 524         PINMUX_IPSR_GPSR(IP3_11_8,      HTX3),
 525
 526         PINMUX_IPSR_GPSR(IP3_15_12,     VI0_DATA0),
 527         PINMUX_IPSR_GPSR(IP3_15_12,     MSIOF2_SS1),
 528         PINMUX_IPSR_GPSR(IP3_15_12,     RTS3_N_TANS),
 529         PINMUX_IPSR_GPSR(IP3_15_12,     HRX3),
 530
 531         PINMUX_IPSR_GPSR(IP3_19_16,     VI0_DATA1),
 532         PINMUX_IPSR_GPSR(IP3_19_16,     MSIOF2_SS2),
 533         PINMUX_IPSR_GPSR(IP3_19_16,     SCK1),
 534         PINMUX_IPSR_MSEL(IP3_19_16,     SPEEDIN_A,      SEL_RSP_1),
 535
 536         PINMUX_IPSR_GPSR(IP3_23_20,     VI0_DATA2),
 537         PINMUX_IPSR_GPSR(IP3_23_20,     AVB0_AVTP_PPS),
 538         PINMUX_IPSR_GPSR(IP3_23_20,     SDA3_A),
 539
 540         PINMUX_IPSR_GPSR(IP3_27_24,     VI0_DATA3),
 541         PINMUX_IPSR_GPSR(IP3_27_24,     HSCK1),
 542         PINMUX_IPSR_GPSR(IP3_27_24,     SCL3_A),
 543
 544         PINMUX_IPSR_GPSR(IP3_31_28,     VI0_DATA4),
 545         PINMUX_IPSR_GPSR(IP3_31_28,     HRTS1_N),
 546         PINMUX_IPSR_MSEL(IP3_31_28,     RX1_A,  SEL_SCIF1_0),
 547
 548         /* IPSR4 */
 549         PINMUX_IPSR_GPSR(IP4_3_0,       VI0_DATA5),
 550         PINMUX_IPSR_GPSR(IP4_3_0,       HCTS1_N),
 551         PINMUX_IPSR_MSEL(IP4_3_0,       TX1_A,  SEL_SCIF1_0),
 552
 553         PINMUX_IPSR_GPSR(IP4_7_4,       VI0_DATA6),
 554         PINMUX_IPSR_GPSR(IP4_7_4,       HTX1),
 555         PINMUX_IPSR_GPSR(IP4_7_4,       CTS1_N),
 556
 557         PINMUX_IPSR_GPSR(IP4_11_8,      VI0_DATA7),
 558         PINMUX_IPSR_GPSR(IP4_11_8,      HRX1),
 559         PINMUX_IPSR_GPSR(IP4_11_8,      RTS1_N_TANS),
 560
 561         PINMUX_IPSR_GPSR(IP4_15_12,     VI0_DATA8),
 562         PINMUX_IPSR_GPSR(IP4_15_12,     HSCK2),
 563         PINMUX_IPSR_MSEL(IP4_15_12,     PWM0_A, SEL_PWM0_0),
 564         PINMUX_IPSR_GPSR(IP4_15_12,     A22),
 565
 566         PINMUX_IPSR_GPSR(IP4_19_16,     VI0_DATA9),
 567         PINMUX_IPSR_GPSR(IP4_19_16,     HCTS2_N),
 568         PINMUX_IPSR_MSEL(IP4_19_16,     PWM1_A, SEL_PWM1_0),
 569         PINMUX_IPSR_GPSR(IP4_19_16,     A23),
 570         PINMUX_IPSR_MSEL(IP4_19_16,     FSO_CFE_0_N_B,  SEL_RFSO_1),
 571
 572         PINMUX_IPSR_GPSR(IP4_23_20,     VI0_DATA10),
 573         PINMUX_IPSR_GPSR(IP4_23_20,     HRTS2_N),
 574         PINMUX_IPSR_MSEL(IP4_23_20,     PWM2_A, SEL_PWM2_0),
 575         PINMUX_IPSR_GPSR(IP4_23_20,     A24),
 576         PINMUX_IPSR_MSEL(IP4_23_20,     FSO_CFE_1_N_B,  SEL_RFSO_1),
 577
 578         PINMUX_IPSR_GPSR(IP4_27_24,     VI0_DATA11),
 579         PINMUX_IPSR_GPSR(IP4_27_24,     HTX2),
 580         PINMUX_IPSR_MSEL(IP4_27_24,     PWM3_A, SEL_PWM3_0),
 581         PINMUX_IPSR_GPSR(IP4_27_24,     A25),
 582         PINMUX_IPSR_MSEL(IP4_27_24,     FSO_TOE_N_B,    SEL_RFSO_1),
 583
 584         PINMUX_IPSR_GPSR(IP4_31_28,     VI0_FIELD),
 585         PINMUX_IPSR_GPSR(IP4_31_28,     HRX2),
 586         PINMUX_IPSR_MSEL(IP4_31_28,     PWM4_A, SEL_PWM4_0),
 587         PINMUX_IPSR_GPSR(IP4_31_28,     CS1_N_A26),
 588         PINMUX_IPSR_GPSR(IP4_31_28,     FSCLKST2_N_A),
 589
 590         /* IPSR5 */
 591         PINMUX_IPSR_GPSR(IP5_3_0,       VI1_CLK),
 592         PINMUX_IPSR_GPSR(IP5_3_0,       MSIOF1_RXD),
 593         PINMUX_IPSR_GPSR(IP5_3_0,       CS0_N),
 594
 595         PINMUX_IPSR_GPSR(IP5_7_4,       VI1_CLKENB),
 596         PINMUX_IPSR_GPSR(IP5_7_4,       MSIOF1_TXD),
 597         PINMUX_IPSR_GPSR(IP5_7_4,       D0),
 598
 599         PINMUX_IPSR_GPSR(IP5_11_8,      VI1_HSYNC_N),
 600         PINMUX_IPSR_GPSR(IP5_11_8,      MSIOF1_SCK),
 601         PINMUX_IPSR_GPSR(IP5_11_8,      D1),
 602
 603         PINMUX_IPSR_GPSR(IP5_15_12,     VI1_VSYNC_N),
 604         PINMUX_IPSR_GPSR(IP5_15_12,     MSIOF1_SYNC),
 605         PINMUX_IPSR_GPSR(IP5_15_12,     D2),
 606
 607         PINMUX_IPSR_GPSR(IP5_19_16,     VI1_DATA0),
 608         PINMUX_IPSR_GPSR(IP5_19_16,     MSIOF1_SS1),
 609         PINMUX_IPSR_GPSR(IP5_19_16,     D3),
 610
 611         PINMUX_IPSR_GPSR(IP5_23_20,     VI1_DATA1),
 612         PINMUX_IPSR_GPSR(IP5_23_20,     MSIOF1_SS2),
 613         PINMUX_IPSR_GPSR(IP5_23_20,     D4),
 614         PINMUX_IPSR_GPSR(IP5_23_20,     MMC_CMD),
 615
 616         PINMUX_IPSR_GPSR(IP5_27_24,     VI1_DATA2),
 617         PINMUX_IPSR_MSEL(IP5_27_24,     CANFD0_TX_B,    SEL_CANFD0_1),
 618         PINMUX_IPSR_GPSR(IP5_27_24,     D5),
 619         PINMUX_IPSR_GPSR(IP5_27_24,     MMC_D0),
 620
 621         PINMUX_IPSR_GPSR(IP5_31_28,     VI1_DATA3),
 622         PINMUX_IPSR_MSEL(IP5_31_28,     CANFD0_RX_B,    SEL_CANFD0_1),
 623         PINMUX_IPSR_GPSR(IP5_31_28,     D6),
 624         PINMUX_IPSR_GPSR(IP5_31_28,     MMC_D1),
 625
 626         /* IPSR6 */
 627         PINMUX_IPSR_GPSR(IP6_3_0,       VI1_DATA4),
 628         PINMUX_IPSR_MSEL(IP6_3_0,       CANFD_CLK_B,    SEL_CANFD0_1),
 629         PINMUX_IPSR_GPSR(IP6_3_0,       D7),
 630         PINMUX_IPSR_GPSR(IP6_3_0,       MMC_D2),
 631
 632         PINMUX_IPSR_GPSR(IP6_7_4,       VI1_DATA5),
 633         PINMUX_IPSR_GPSR(IP6_7_4,       SCK4),
 634         PINMUX_IPSR_GPSR(IP6_7_4,       D8),
 635         PINMUX_IPSR_GPSR(IP6_7_4,       MMC_D3),
 636
 637         PINMUX_IPSR_GPSR(IP6_11_8,      VI1_DATA6),
 638         PINMUX_IPSR_GPSR(IP6_11_8,      RX4),
 639         PINMUX_IPSR_GPSR(IP6_11_8,      D9),
 640         PINMUX_IPSR_GPSR(IP6_11_8,      MMC_CLK),
 641
 642         PINMUX_IPSR_GPSR(IP6_15_12,     VI1_DATA7),
 643         PINMUX_IPSR_GPSR(IP6_15_12,     TX4),
 644         PINMUX_IPSR_GPSR(IP6_15_12,     D10),
 645         PINMUX_IPSR_GPSR(IP6_15_12,     MMC_D4),
 646
 647         PINMUX_IPSR_GPSR(IP6_19_16,     VI1_DATA8),
 648         PINMUX_IPSR_GPSR(IP6_19_16,     CTS4_N),
 649         PINMUX_IPSR_GPSR(IP6_19_16,     D11),
 650         PINMUX_IPSR_GPSR(IP6_19_16,     MMC_D5),
 651
 652         PINMUX_IPSR_GPSR(IP6_23_20,     VI1_DATA9),
 653         PINMUX_IPSR_GPSR(IP6_23_20,     RTS4_N_TANS),
 654         PINMUX_IPSR_GPSR(IP6_23_20,     D12),
 655         PINMUX_IPSR_GPSR(IP6_23_20,     MMC_D6),
 656         PINMUX_IPSR_GPSR(IP6_23_20,     SCL3_B),
 657
 658         PINMUX_IPSR_GPSR(IP6_27_24,     VI1_DATA10),
 659         PINMUX_IPSR_GPSR(IP6_27_24,     D13),
 660         PINMUX_IPSR_GPSR(IP6_27_24,     MMC_D7),
 661         PINMUX_IPSR_GPSR(IP6_27_24,     SDA3_B),
 662
 663         PINMUX_IPSR_GPSR(IP6_31_28,     VI1_DATA11),
 664         PINMUX_IPSR_GPSR(IP6_31_28,     SCL4),
 665         PINMUX_IPSR_GPSR(IP6_31_28,     IRQ4),
 666         PINMUX_IPSR_GPSR(IP6_31_28,     D14),
 667         PINMUX_IPSR_GPSR(IP6_31_28,     MMC_WP),
 668
 669         /* IPSR7 */
 670         PINMUX_IPSR_GPSR(IP7_3_0,       VI1_FIELD),
 671         PINMUX_IPSR_GPSR(IP7_3_0,       SDA4),
 672         PINMUX_IPSR_GPSR(IP7_3_0,       IRQ5),
 673         PINMUX_IPSR_GPSR(IP7_3_0,       D15),
 674         PINMUX_IPSR_GPSR(IP7_3_0,       MMC_CD),
 675
 676         PINMUX_IPSR_GPSR(IP7_7_4,       SCL0),
 677         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR0),
 678         PINMUX_IPSR_GPSR(IP7_7_4,       TPU0TO0),
 679         PINMUX_IPSR_GPSR(IP7_7_4,       CLKOUT),
 680         PINMUX_IPSR_GPSR(IP7_7_4,       MSIOF0_RXD),
 681
 682         PINMUX_IPSR_GPSR(IP7_11_8,      SDA0),
 683         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR1),
 684         PINMUX_IPSR_GPSR(IP7_11_8,      TPU0TO1),
 685         PINMUX_IPSR_GPSR(IP7_11_8,      BS_N),
 686         PINMUX_IPSR_GPSR(IP7_11_8,      SCK0),
 687         PINMUX_IPSR_GPSR(IP7_11_8,      MSIOF0_TXD),
 688
 689         PINMUX_IPSR_GPSR(IP7_15_12,     SCL1),
 690         PINMUX_IPSR_GPSR(IP7_15_12,     DU_DG0),
 691         PINMUX_IPSR_GPSR(IP7_15_12,     TPU0TO2),
 692         PINMUX_IPSR_GPSR(IP7_15_12,     RD_N),
 693         PINMUX_IPSR_GPSR(IP7_15_12,     CTS0_N),
 694         PINMUX_IPSR_GPSR(IP7_15_12,     MSIOF0_SCK),
 695
 696         PINMUX_IPSR_GPSR(IP7_19_16,     SDA1),
 697         PINMUX_IPSR_GPSR(IP7_19_16,     DU_DG1),
 698         PINMUX_IPSR_GPSR(IP7_19_16,     TPU0TO3),
 699         PINMUX_IPSR_GPSR(IP7_19_16,     WE0_N),
 700         PINMUX_IPSR_GPSR(IP7_19_16,     RTS0_N_TANS),
 701         PINMUX_IPSR_GPSR(IP7_19_16,     MSIOF0_SYNC),
 702
 703         PINMUX_IPSR_GPSR(IP7_23_20,     SCL2),
 704         PINMUX_IPSR_GPSR(IP7_23_20,     DU_DB0),
 705         PINMUX_IPSR_MSEL(IP7_23_20,     TCLK1_A,        SEL_TMU_0),
 706         PINMUX_IPSR_GPSR(IP7_23_20,     WE1_N),
 707         PINMUX_IPSR_GPSR(IP7_23_20,     RX0),
 708         PINMUX_IPSR_GPSR(IP7_23_20,     MSIOF0_SS1),
 709
 710         PINMUX_IPSR_GPSR(IP7_27_24,     SDA2),
 711         PINMUX_IPSR_GPSR(IP7_27_24,     DU_DB1),
 712         PINMUX_IPSR_MSEL(IP7_27_24,     TCLK2_A,        SEL_TMU_0),
 713         PINMUX_IPSR_GPSR(IP7_27_24,     EX_WAIT0),
 714         PINMUX_IPSR_GPSR(IP7_27_24,     TX0),
 715         PINMUX_IPSR_GPSR(IP7_27_24,     MSIOF0_SS2),
 716
 717         PINMUX_IPSR_GPSR(IP7_31_28,     AVB0_AVTP_CAPTURE),
 718         PINMUX_IPSR_GPSR(IP7_31_28,     FSCLKST2_N_B),
 719
 720         /* IPSR8 */
 721         PINMUX_IPSR_MSEL(IP8_3_0,       CANFD0_TX_A,    SEL_CANFD0_0),
 722         PINMUX_IPSR_GPSR(IP8_3_0,       FXR_TXDA),
 723         PINMUX_IPSR_MSEL(IP8_3_0,       PWM0_B, SEL_PWM0_1),
 724         PINMUX_IPSR_GPSR(IP8_3_0,       DU_DISP),
 725         PINMUX_IPSR_GPSR(IP8_3_0,       FSCLKST2_N_C),
 726
 727         PINMUX_IPSR_MSEL(IP8_7_4,       CANFD0_RX_A,    SEL_CANFD0_0),
 728         PINMUX_IPSR_GPSR(IP8_7_4,       RXDA_EXTFXR),
 729         PINMUX_IPSR_MSEL(IP8_7_4,       PWM1_B, SEL_PWM1_1),
 730         PINMUX_IPSR_GPSR(IP8_7_4,       DU_CDE),
 731
 732         PINMUX_IPSR_GPSR(IP8_11_8,      CANFD1_TX),
 733         PINMUX_IPSR_GPSR(IP8_11_8,      FXR_TXDB),
 734         PINMUX_IPSR_MSEL(IP8_11_8,      PWM2_B, SEL_PWM2_1),
 735         PINMUX_IPSR_MSEL(IP8_11_8,      TCLK1_B,        SEL_TMU_1),
 736         PINMUX_IPSR_MSEL(IP8_11_8,      TX1_B,  SEL_SCIF1_1),
 737
 738         PINMUX_IPSR_GPSR(IP8_15_12,     CANFD1_RX),
 739         PINMUX_IPSR_GPSR(IP8_15_12,     RXDB_EXTFXR),
 740         PINMUX_IPSR_MSEL(IP8_15_12,     PWM3_B, SEL_PWM3_1),
 741         PINMUX_IPSR_MSEL(IP8_15_12,     TCLK2_B,        SEL_TMU_1),
 742         PINMUX_IPSR_MSEL(IP8_15_12,     RX1_B,  SEL_SCIF1_1),
 743
 744         PINMUX_IPSR_MSEL(IP8_19_16,     CANFD_CLK_A,    SEL_CANFD0_0),
 745         PINMUX_IPSR_GPSR(IP8_19_16,     CLK_EXTFXR),
 746         PINMUX_IPSR_MSEL(IP8_19_16,     PWM4_B, SEL_PWM4_1),
 747         PINMUX_IPSR_MSEL(IP8_19_16,     SPEEDIN_B,      SEL_RSP_0),
 748         PINMUX_IPSR_MSEL(IP8_19_16,     SCIF_CLK_B,     SEL_HSCIF0_1),
 749
 750         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKIN),
 751         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKEN_IN),
 752
 753         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKOUT),
 754         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKEN_OUT),
 755 };
 756
 757 static const struct sh_pfc_pin pinmux_pins[] = {
 758         PINMUX_GPIO_GP_ALL(),
 759 };
 760
 761 /* - EtherAVB --------------------------------------------------------------- */
 762 static const unsigned int avb0_rx_ctrl_pins[] = {
 763         /* AVB0_RX_CTL */
 764         RCAR_GP_PIN(1, 1),
 765 };
 766 static const unsigned int avb0_rx_ctrl_mux[] = {
 767         AVB0_RX_CTL_MARK,
 768 };
 769 static const unsigned int avb0_rxc_pins[] = {
 770         /* AVB0_RXC */
 771         RCAR_GP_PIN(1, 2),
 772 };
 773 static const unsigned int avb0_rxc_mux[] = {
 774         AVB0_RXC_MARK,
 775 };
 776 static const unsigned int avb0_rd0_pins[] = {
 777         /* AVB0_RD[0] */
 778         RCAR_GP_PIN(1, 3),
 779 };
 780 static const unsigned int avb0_rd0_mux[] = {
 781         AVB0_RD0_MARK,
 782 };
 783 static const unsigned int avb0_rd1_pins[] = {
 784         /* AVB0_RD[1] */
 785         RCAR_GP_PIN(1, 4),
 786 };
 787 static const unsigned int avb0_rd1_mux[] = {
 788         AVB0_RD1_MARK,
 789 };
 790 static const unsigned int avb0_rd2_pins[] = {
 791         /* AVB0_RD[2] */
 792         RCAR_GP_PIN(1, 5),
 793 };
 794 static const unsigned int avb0_rd2_mux[] = {
 795         AVB0_RD2_MARK,
 796 };
 797 static const unsigned int avb0_rd3_pins[] = {
 798         /* AVB0_RD[3] */
 799         RCAR_GP_PIN(1, 6),
 800 };
 801 static const unsigned int avb0_rd3_mux[] = {
 802         AVB0_RD3_MARK,
 803 };
 804 static const unsigned int avb0_rd4_pins[] = {
 805         /* AVB0_RD[3:0] */
 806         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
 807         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
 808 };
 809 static const unsigned int avb0_rd4_mux[] = {
 810         AVB0_RD0_MARK, AVB0_RD1_MARK,
 811         AVB0_RD2_MARK, AVB0_RD3_MARK,
 812 };
 813 static const unsigned int avb0_tx_ctrl_pins[] = {
 814         /* AVB0_TX_CTL */
 815         RCAR_GP_PIN(1, 7),
 816 };
 817 static const unsigned int avb0_tx_ctrl_mux[] = {
 818         AVB0_TX_CTL_MARK,
 819 };
 820 static const unsigned int avb0_txc_pins[] = {
 821         /* AVB0_TXC */
 822         RCAR_GP_PIN(1, 8),
 823 };
 824 static const unsigned int avb0_txc_mux[] = {
 825         AVB0_TXC_MARK,
 826 };
 827 static const unsigned int avb0_td0_pins[] = {
 828         /* AVB0_TD[0] */
 829         RCAR_GP_PIN(1, 9),
 830 };
 831 static const unsigned int avb0_td0_mux[] = {
 832         AVB0_TD0_MARK,
 833 };
 834 static const unsigned int avb0_td1_pins[] = {
 835         /* AVB0_TD[1] */
 836         RCAR_GP_PIN(1, 10),
 837 };
 838 static const unsigned int avb0_td1_mux[] = {
 839         AVB0_TD1_MARK,
 840 };
 841 static const unsigned int avb0_td2_pins[] = {
 842         /* AVB0_TD[2] */
 843         RCAR_GP_PIN(1, 11),
 844 };
 845 static const unsigned int avb0_td2_mux[] = {
 846         AVB0_TD2_MARK,
 847 };
 848 static const unsigned int avb0_td3_pins[] = {
 849         /* AVB0_TD[3] */
 850         RCAR_GP_PIN(1, 12),
 851 };
 852 static const unsigned int avb0_td3_mux[] = {
 853         AVB0_TD3_MARK,
 854 };
 855 static const unsigned int avb0_td4_pins[] = {
 856         /* AVB0_TD[3:0] */
 857         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
 858         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
 859 };
 860 static const unsigned int avb0_td4_mux[] = {
 861         AVB0_TD0_MARK, AVB0_TD1_MARK,
 862         AVB0_TD2_MARK, AVB0_TD3_MARK,
 863 };
 864 static const unsigned int avb0_txcrefclk_pins[] = {
 865         /* AVB0_TXCREFCLK */
 866         RCAR_GP_PIN(1, 13),
 867 };
 868 static const unsigned int avb0_txcrefclk_mux[] = {
 869         AVB0_TXCREFCLK_MARK,
 870 };
 871 static const unsigned int avb0_mdio_pins[] = {
 872         /* AVB0_MDIO */
 873         RCAR_GP_PIN(1, 14),
 874 };
 875 static const unsigned int avb0_mdio_mux[] = {
 876         AVB0_MDIO_MARK,
 877 };
 878 static const unsigned int avb0_mdc_pins[] = {
 879         /* AVB0_MDC */
 880         RCAR_GP_PIN(1, 15),
 881 };
 882 static const unsigned int avb0_mdc_mux[] = {
 883         AVB0_MDC_MARK,
 884 };
 885 static const unsigned int avb0_magic_pins[] = {
 886         /* AVB0_MAGIC */
 887         RCAR_GP_PIN(1, 16),
 888 };
 889 static const unsigned int avb0_magic_mux[] = {
 890         AVB0_MAGIC_MARK,
 891 };
 892 static const unsigned int avb0_phy_int_pins[] = {
 893         /* AVB0_PHY_INT */
 894         RCAR_GP_PIN(1, 17),
 895 };
 896 static const unsigned int avb0_phy_int_mux[] = {
 897         AVB0_PHY_INT_MARK,
 898 };
 899 static const unsigned int avb0_link_pins[] = {
 900         /* AVB0_LINK */
 901         RCAR_GP_PIN(1, 18),
 902 };
 903 static const unsigned int avb0_link_mux[] = {
 904         AVB0_LINK_MARK,
 905 };
 906 static const unsigned int avb0_avtp_match_pins[] = {
 907         /* AVB0_AVTP_MATCH */
 908         RCAR_GP_PIN(1, 19),
 909 };
 910 static const unsigned int avb0_avtp_match_mux[] = {
 911         AVB0_AVTP_MATCH_MARK,
 912 };
 913 static const unsigned int avb0_avtp_pps_pins[] = {
 914         /* AVB0_AVTP_PPS */
 915         RCAR_GP_PIN(2, 6),
 916 };
 917 static const unsigned int avb0_avtp_pps_mux[] = {
 918         AVB0_AVTP_PPS_MARK,
 919 };
 920 static const unsigned int avb0_avtp_capture_pins[] = {
 921         /* AVB0_AVTP_CAPTURE */
 922         RCAR_GP_PIN(1, 20),
 923 };
 924 static const unsigned int avb0_avtp_capture_mux[] = {
 925         AVB0_AVTP_CAPTURE_MARK,
 926 };
 927
 928 /* - CANFD0 ----------------------------------------------------------------- */
 929 static const unsigned int canfd0_data_a_pins[] = {
 930         /* TX, RX */
 931         RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
 932 };
 933 static const unsigned int canfd0_data_a_mux[] = {
 934         CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
 935 };
 936 static const unsigned int canfd_clk_a_pins[] = {
 937         /* CLK */
 938         RCAR_GP_PIN(1, 25),
 939 };
 940 static const unsigned int canfd_clk_a_mux[] = {
 941         CANFD_CLK_A_MARK,
 942 };
 943 static const unsigned int canfd0_data_b_pins[] = {
 944         /* TX, RX */
 945         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 946 };
 947 static const unsigned int canfd0_data_b_mux[] = {
 948         CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
 949 };
 950 static const unsigned int canfd_clk_b_pins[] = {
 951         /* CLK */
 952         RCAR_GP_PIN(3, 8),
 953 };
 954 static const unsigned int canfd_clk_b_mux[] = {
 955         CANFD_CLK_B_MARK,
 956 };
 957
 958 /* - CANFD1 ----------------------------------------------------------------- */
 959 static const unsigned int canfd1_data_pins[] = {
 960         /* TX, RX */
 961         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
 962 };
 963 static const unsigned int canfd1_data_mux[] = {
 964         CANFD1_TX_MARK, CANFD1_RX_MARK,
 965 };
 966
 967 /* - DU --------------------------------------------------------------------- */
 968 static const unsigned int du_rgb666_pins[] = {
 969         /* R[7:0] */
 970         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
 971         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 972         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 973         /* G[7:0] */
 974         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 975         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
 976         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
 977         /* B[7:0] */
 978         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
 979         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
 980         RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
 981 };
 982 static const unsigned int du_rgb666_mux[] = {
 983         DU_DR7_MARK, DU_DR6_MARK,
 984         DU_DR5_MARK, DU_DR4_MARK,
 985         DU_DR3_MARK, DU_DR2_MARK,
 986         DU_DG7_MARK, DU_DG6_MARK,
 987         DU_DG5_MARK, DU_DG4_MARK,
 988         DU_DG3_MARK, DU_DG2_MARK,
 989         DU_DB7_MARK, DU_DB6_MARK,
 990         DU_DB5_MARK, DU_DB4_MARK,
 991         DU_DB3_MARK, DU_DB2_MARK,
 992 };
 993 static const unsigned int du_clk_out_0_pins[] = {
 994         /* CLKOUT0 */
 995         RCAR_GP_PIN(0, 18),
 996 };
 997 static const unsigned int du_clk_out_0_mux[] = {
 998         DU_DOTCLKOUT_MARK,
 999 };
1000 static const unsigned int du_clk_out_1_pins[] = {
1001         /* CLKOUT1 */
1002         RCAR_GP_PIN(0, 18),             /* @@ */
1003 };
1004 static const unsigned int du_clk_out_1_mux[] = {
1005         DU_DOTCLKOUT_MARK,
1006 };
1007 static const unsigned int du_sync_pins[] = {
1008         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1009         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1010 };
1011 static const unsigned int du_sync_mux[] = {
1012         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1013 };
1014 static const unsigned int du_oddf_pins[] = {
1015         /* EXDISP/EXODDF/EXCDE */
1016         RCAR_GP_PIN(0, 21),
1017 };
1018 static const unsigned int du_oddf_mux[] = {
1019         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1020 };
1021 static const unsigned int du_cde_pins[] = {
1022         /* CDE */
1023         RCAR_GP_PIN(1, 22),
1024 };
1025 static const unsigned int du_cde_mux[] = {
1026         DU_CDE_MARK,
1027 };
1028 static const unsigned int du_disp_pins[] = {
1029         /* DISP */
1030         RCAR_GP_PIN(1, 21),
1031 };
1032 static const unsigned int du_disp_mux[] = {
1033         DU_DISP_MARK,
1034 };
1035
1036 /* - HSCIF0 ----------------------------------------------------------------- */
1037 static const unsigned int hscif0_data_pins[] = {
1038         /* HRX0, HTX0 */
1039         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
1040 };
1041 static const unsigned int hscif0_data_mux[] = {
1042         HRX0_MARK, HTX0_MARK,
1043 };
1044 static const unsigned int hscif0_clk_pins[] = {
1045         /* HSCK0 */
1046         RCAR_GP_PIN(0, 0),
1047 };
1048 static const unsigned int hscif0_clk_mux[] = {
1049         HSCK0_MARK,
1050 };
1051 static const unsigned int hscif0_ctrl_pins[] = {
1052         /* HRTS0#, HCTS0# */
1053         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1054 };
1055 static const unsigned int hscif0_ctrl_mux[] = {
1056         HRTS0_N_MARK, HCTS0_N_MARK,
1057 };
1058
1059 /* - HSCIF1 ----------------------------------------------------------------- */
1060 static const unsigned int hscif1_data_pins[] = {
1061         /* HRX1, HTX1 */
1062         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1063 };
1064 static const unsigned int hscif1_data_mux[] = {
1065         HRX1_MARK, HTX1_MARK,
1066 };
1067 static const unsigned int hscif1_clk_pins[] = {
1068         /* HSCK1 */
1069         RCAR_GP_PIN(2, 7),
1070 };
1071 static const unsigned int hscif1_clk_mux[] = {
1072         HSCK1_MARK,
1073 };
1074 static const unsigned int hscif1_ctrl_pins[] = {
1075         /* HRTS1#, HCTS1# */
1076         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1077 };
1078 static const unsigned int hscif1_ctrl_mux[] = {
1079         HRTS1_N_MARK, HCTS1_N_MARK,
1080 };
1081
1082 /* - HSCIF2 ----------------------------------------------------------------- */
1083 static const unsigned int hscif2_data_pins[] = {
1084         /* HRX2, HTX2 */
1085         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1086 };
1087 static const unsigned int hscif2_data_mux[] = {
1088         HRX2_MARK, HTX2_MARK,
1089 };
1090 static const unsigned int hscif2_clk_pins[] = {
1091         /* HSCK2 */
1092         RCAR_GP_PIN(2, 12),
1093 };
1094 static const unsigned int hscif2_clk_mux[] = {
1095         HSCK2_MARK,
1096 };
1097 static const unsigned int hscif2_ctrl_pins[] = {
1098         /* HRTS2#, HCTS2# */
1099         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1100 };
1101 static const unsigned int hscif2_ctrl_mux[] = {
1102         HRTS2_N_MARK, HCTS2_N_MARK,
1103 };
1104
1105 /* - HSCIF3 ----------------------------------------------------------------- */
1106 static const unsigned int hscif3_data_pins[] = {
1107         /* HRX3, HTX3 */
1108         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1109 };
1110 static const unsigned int hscif3_data_mux[] = {
1111         HRX3_MARK, HTX3_MARK,
1112 };
1113 static const unsigned int hscif3_clk_pins[] = {
1114         /* HSCK3 */
1115         RCAR_GP_PIN(2, 0),
1116 };
1117 static const unsigned int hscif3_clk_mux[] = {
1118         HSCK3_MARK,
1119 };
1120 static const unsigned int hscif3_ctrl_pins[] = {
1121         /* HRTS3#, HCTS3# */
1122         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1123 };
1124 static const unsigned int hscif3_ctrl_mux[] = {
1125         HRTS3_N_MARK, HCTS3_N_MARK,
1126 };
1127
1128 /* - SCIF Clock ------------------------------------------------------------- */
1129 static const unsigned int scif_clk_a_pins[] = {
1130         /* SCIF_CLK */
1131         RCAR_GP_PIN(0, 18),
1132 };
1133 static const unsigned int scif_clk_a_mux[] = {
1134         SCIF_CLK_A_MARK,
1135 };
1136 static const unsigned int scif_clk_b_pins[] = {
1137         /* SCIF_CLK */
1138         RCAR_GP_PIN(1, 25),
1139 };
1140 static const unsigned int scif_clk_b_mux[] = {
1141         SCIF_CLK_B_MARK,
1142 };
1143
1144 /* - I2C -------------------------------------------------------------------- */
1145 static const unsigned int i2c0_pins[] = {
1146         /* SDA0, SCL0 */
1147         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1148 };
1149 static const unsigned int i2c0_mux[] = {
1150         SDA0_MARK, SCL0_MARK,
1151 };
1152 static const unsigned int i2c1_pins[] = {
1153         /* SDA1, SCL1 */
1154         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1155 };
1156 static const unsigned int i2c1_mux[] = {
1157         SDA1_MARK, SCL1_MARK,
1158 };
1159 static const unsigned int i2c2_pins[] = {
1160         /* SDA2, SCL2 */
1161         RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1162 };
1163 static const unsigned int i2c2_mux[] = {
1164         SDA2_MARK, SCL2_MARK,
1165 };
1166 static const unsigned int i2c3_pins[] = {
1167         /* SDA3_A, SCL3_A */
1168         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1169 };
1170 static const unsigned int i2c3_mux[] = {
1171         SDA3_A_MARK, SCL3_A_MARK,
1172 };
1173 static const unsigned int i2c4_pins[] = {
1174         /* SDA4, SCL4 */
1175         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1176 };
1177 static const unsigned int i2c4_mux[] = {
1178         SDA4_MARK, SCL4_MARK,
1179 };
1180
1181 /* - INTC-EX ---------------------------------------------------------------- */
1182 static const unsigned int intc_ex_irq0_pins[] = {
1183         /* IRQ0 */
1184         RCAR_GP_PIN(1, 0),
1185 };
1186 static const unsigned int intc_ex_irq0_mux[] = {
1187         IRQ0_MARK,
1188 };
1189 static const unsigned int intc_ex_irq1_pins[] = {
1190         /* IRQ1 */
1191         RCAR_GP_PIN(0, 11),
1192 };
1193 static const unsigned int intc_ex_irq1_mux[] = {
1194         IRQ1_MARK,
1195 };
1196 static const unsigned int intc_ex_irq2_pins[] = {
1197         /* IRQ2 */
1198         RCAR_GP_PIN(0, 12),
1199 };
1200 static const unsigned int intc_ex_irq2_mux[] = {
1201         IRQ2_MARK,
1202 };
1203 static const unsigned int intc_ex_irq3_pins[] = {
1204         /* IRQ3 */
1205         RCAR_GP_PIN(0, 19),
1206 };
1207 static const unsigned int intc_ex_irq3_mux[] = {
1208         IRQ3_MARK,
1209 };
1210 static const unsigned int intc_ex_irq4_pins[] = {
1211         /* IRQ4 */
1212         RCAR_GP_PIN(3, 15),
1213 };
1214 static const unsigned int intc_ex_irq4_mux[] = {
1215         IRQ4_MARK,
1216 };
1217 static const unsigned int intc_ex_irq5_pins[] = {
1218         /* IRQ5 */
1219         RCAR_GP_PIN(3, 16),
1220 };
1221 static const unsigned int intc_ex_irq5_mux[] = {
1222         IRQ5_MARK,
1223 };
1224
1225 /* - MSIOF0 ----------------------------------------------------------------- */
1226 static const unsigned int msiof0_clk_pins[] = {
1227         /* SCK */
1228         RCAR_GP_PIN(4, 2),
1229 };
1230 static const unsigned int msiof0_clk_mux[] = {
1231         MSIOF0_SCK_MARK,
1232 };
1233 static const unsigned int msiof0_sync_pins[] = {
1234         /* SYNC */
1235         RCAR_GP_PIN(4, 3),
1236 };
1237 static const unsigned int msiof0_sync_mux[] = {
1238         MSIOF0_SYNC_MARK,
1239 };
1240 static const unsigned int msiof0_ss1_pins[] = {
1241         /* SS1 */
1242         RCAR_GP_PIN(4, 4),
1243 };
1244 static const unsigned int msiof0_ss1_mux[] = {
1245         MSIOF0_SS1_MARK,
1246 };
1247 static const unsigned int msiof0_ss2_pins[] = {
1248         /* SS2 */
1249         RCAR_GP_PIN(4, 5),
1250 };
1251 static const unsigned int msiof0_ss2_mux[] = {
1252         MSIOF0_SS2_MARK,
1253 };
1254 static const unsigned int msiof0_txd_pins[] = {
1255         /* TXD */
1256         RCAR_GP_PIN(4, 1),
1257 };
1258 static const unsigned int msiof0_txd_mux[] = {
1259         MSIOF0_TXD_MARK,
1260 };
1261 static const unsigned int msiof0_rxd_pins[] = {
1262         /* RXD */
1263         RCAR_GP_PIN(4, 0),
1264 };
1265 static const unsigned int msiof0_rxd_mux[] = {
1266         MSIOF0_RXD_MARK,
1267 };
1268
1269 /* - MSIOF1 ----------------------------------------------------------------- */
1270 static const unsigned int msiof1_clk_pins[] = {
1271         /* SCK */
1272         RCAR_GP_PIN(3, 2),
1273 };
1274 static const unsigned int msiof1_clk_mux[] = {
1275         MSIOF1_SCK_MARK,
1276 };
1277 static const unsigned int msiof1_sync_pins[] = {
1278         /* SYNC */
1279         RCAR_GP_PIN(3, 3),
1280 };
1281 static const unsigned int msiof1_sync_mux[] = {
1282         MSIOF1_SYNC_MARK,
1283 };
1284 static const unsigned int msiof1_ss1_pins[] = {
1285         /* SS1 */
1286         RCAR_GP_PIN(3, 4),
1287 };
1288 static const unsigned int msiof1_ss1_mux[] = {
1289         MSIOF1_SS1_MARK,
1290 };
1291 static const unsigned int msiof1_ss2_pins[] = {
1292         /* SS2 */
1293         RCAR_GP_PIN(3, 5),
1294 };
1295 static const unsigned int msiof1_ss2_mux[] = {
1296         MSIOF1_SS2_MARK,
1297 };
1298 static const unsigned int msiof1_txd_pins[] = {
1299         /* TXD */
1300         RCAR_GP_PIN(3, 1),
1301 };
1302 static const unsigned int msiof1_txd_mux[] = {
1303         MSIOF1_TXD_MARK,
1304 };
1305 static const unsigned int msiof1_rxd_pins[] = {
1306         /* RXD */
1307         RCAR_GP_PIN(3, 0),
1308 };
1309 static const unsigned int msiof1_rxd_mux[] = {
1310         MSIOF1_RXD_MARK,
1311 };
1312
1313 /* - MSIOF2 ----------------------------------------------------------------- */
1314 static const unsigned int msiof2_clk_pins[] = {
1315         /* SCK */
1316         RCAR_GP_PIN(2, 0),
1317 };
1318 static const unsigned int msiof2_clk_mux[] = {
1319         MSIOF2_SCK_MARK,
1320 };
1321 static const unsigned int msiof2_sync_pins[] = {
1322         /* SYNC */
1323         RCAR_GP_PIN(2, 3),
1324 };
1325 static const unsigned int msiof2_sync_mux[] = {
1326         MSIOF2_SYNC_MARK,
1327 };
1328 static const unsigned int msiof2_ss1_pins[] = {
1329         /* SS1 */
1330         RCAR_GP_PIN(2, 4),
1331 };
1332 static const unsigned int msiof2_ss1_mux[] = {
1333         MSIOF2_SS1_MARK,
1334 };
1335 static const unsigned int msiof2_ss2_pins[] = {
1336         /* SS2 */
1337         RCAR_GP_PIN(2, 5),
1338 };
1339 static const unsigned int msiof2_ss2_mux[] = {
1340         MSIOF2_SS2_MARK,
1341 };
1342 static const unsigned int msiof2_txd_pins[] = {
1343         /* TXD */
1344         RCAR_GP_PIN(2, 2),
1345 };
1346 static const unsigned int msiof2_txd_mux[] = {
1347         MSIOF2_TXD_MARK,
1348 };
1349 static const unsigned int msiof2_rxd_pins[] = {
1350         /* RXD */
1351         RCAR_GP_PIN(2, 1),
1352 };
1353 static const unsigned int msiof2_rxd_mux[] = {
1354         MSIOF2_RXD_MARK,
1355 };
1356
1357 /* - MSIOF3 ----------------------------------------------------------------- */
1358 static const unsigned int msiof3_clk_pins[] = {
1359         /* SCK */
1360         RCAR_GP_PIN(0, 20),
1361 };
1362 static const unsigned int msiof3_clk_mux[] = {
1363         MSIOF3_SCK_MARK,
1364 };
1365 static const unsigned int msiof3_sync_pins[] = {
1366         /* SYNC */
1367         RCAR_GP_PIN(0, 21),
1368 };
1369 static const unsigned int msiof3_sync_mux[] = {
1370         MSIOF3_SYNC_MARK,
1371 };
1372 static const unsigned int msiof3_ss1_pins[] = {
1373         /* SS1 */
1374         RCAR_GP_PIN(0, 6),
1375 };
1376 static const unsigned int msiof3_ss1_mux[] = {
1377         MSIOF3_SS1_MARK,
1378 };
1379 static const unsigned int msiof3_ss2_pins[] = {
1380         /* SS2 */
1381         RCAR_GP_PIN(0, 7),
1382 };
1383 static const unsigned int msiof3_ss2_mux[] = {
1384         MSIOF3_SS2_MARK,
1385 };
1386 static const unsigned int msiof3_txd_pins[] = {
1387         /* TXD */
1388         RCAR_GP_PIN(0, 5),
1389 };
1390 static const unsigned int msiof3_txd_mux[] = {
1391         MSIOF3_TXD_MARK,
1392 };
1393 static const unsigned int msiof3_rxd_pins[] = {
1394         /* RXD */
1395         RCAR_GP_PIN(0, 4),
1396 };
1397 static const unsigned int msiof3_rxd_mux[] = {
1398         MSIOF3_RXD_MARK,
1399 };
1400
1401 /* - PWM0 ------------------------------------------------------------------- */
1402 static const unsigned int pwm0_a_pins[] = {
1403         /* PWM0 */
1404         RCAR_GP_PIN(2, 12),
1405 };
1406 static const unsigned int pwm0_a_mux[] = {
1407         PWM0_A_MARK,
1408 };
1409 static const unsigned int pwm0_b_pins[] = {
1410         /* PWM0 */
1411         RCAR_GP_PIN(1, 21),
1412 };
1413 static const unsigned int pwm0_b_mux[] = {
1414         PWM0_B_MARK,
1415 };
1416
1417 /* - PWM1 ------------------------------------------------------------------- */
1418 static const unsigned int pwm1_a_pins[] = {
1419         /* PWM1 */
1420         RCAR_GP_PIN(2, 13),
1421 };
1422 static const unsigned int pwm1_a_mux[] = {
1423         PWM1_A_MARK,
1424 };
1425 static const unsigned int pwm1_b_pins[] = {
1426         /* PWM1 */
1427         RCAR_GP_PIN(1, 22),
1428 };
1429 static const unsigned int pwm1_b_mux[] = {
1430         PWM1_B_MARK,
1431 };
1432
1433 /* - PWM2 ------------------------------------------------------------------- */
1434 static const unsigned int pwm2_a_pins[] = {
1435         /* PWM2 */
1436         RCAR_GP_PIN(2, 14),
1437 };
1438 static const unsigned int pwm2_a_mux[] = {
1439         PWM2_A_MARK,
1440 };
1441 static const unsigned int pwm2_b_pins[] = {
1442         /* PWM2 */
1443         RCAR_GP_PIN(1, 23),
1444 };
1445 static const unsigned int pwm2_b_mux[] = {
1446         PWM2_B_MARK,
1447 };
1448
1449 /* - PWM3 ------------------------------------------------------------------- */
1450 static const unsigned int pwm3_a_pins[] = {
1451         /* PWM3 */
1452         RCAR_GP_PIN(2, 15),
1453 };
1454 static const unsigned int pwm3_a_mux[] = {
1455         PWM3_A_MARK,
1456 };
1457 static const unsigned int pwm3_b_pins[] = {
1458         /* PWM3 */
1459         RCAR_GP_PIN(1, 24),
1460 };
1461 static const unsigned int pwm3_b_mux[] = {
1462         PWM3_B_MARK,
1463 };
1464
1465 /* - PWM4 ------------------------------------------------------------------- */
1466 static const unsigned int pwm4_a_pins[] = {
1467         /* PWM4 */
1468         RCAR_GP_PIN(2, 16),
1469 };
1470 static const unsigned int pwm4_a_mux[] = {
1471         PWM4_A_MARK,
1472 };
1473 static const unsigned int pwm4_b_pins[] = {
1474         /* PWM4 */
1475         RCAR_GP_PIN(1, 25),
1476 };
1477 static const unsigned int pwm4_b_mux[] = {
1478         PWM4_B_MARK,
1479 };
1480
1481 /* - SCIF0 ------------------------------------------------------------------ */
1482 static const unsigned int scif0_data_pins[] = {
1483         /* RX, TX */
1484         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1485 };
1486 static const unsigned int scif0_data_mux[] = {
1487         RX0_MARK, TX0_MARK,
1488 };
1489 static const unsigned int scif0_clk_pins[] = {
1490         /* SCK */
1491         RCAR_GP_PIN(4, 1),
1492 };
1493 static const unsigned int scif0_clk_mux[] = {
1494         SCK0_MARK,
1495 };
1496
1497 static const unsigned int scif0_ctrl_pins[] = {
1498         /* RTS, CTS */
1499         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1500 };
1501 static const unsigned int scif0_ctrl_mux[] = {
1502         RTS0_N_TANS_MARK, CTS0_N_MARK,
1503 };
1504
1505 /* - SCIF1 ------------------------------------------------------------------ */
1506 static const unsigned int scif1_data_a_pins[] = {
1507         /* RX, TX */
1508         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1509 };
1510 static const unsigned int scif1_data_a_mux[] = {
1511         RX1_A_MARK, TX1_A_MARK,
1512 };
1513 static const unsigned int scif1_clk_pins[] = {
1514         /* SCK */
1515         RCAR_GP_PIN(2, 5),
1516 };
1517 static const unsigned int scif1_clk_mux[] = {
1518         SCK1_MARK,
1519 };
1520 static const unsigned int scif1_ctrl_pins[] = {
1521         /* RTS, CTS */
1522         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1523 };
1524 static const unsigned int scif1_ctrl_mux[] = {
1525         RTS1_N_TANS_MARK, CTS1_N_MARK,
1526 };
1527 static const unsigned int scif1_data_b_pins[] = {
1528         /* RX, TX */
1529         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1530 };
1531 static const unsigned int scif1_data_b_mux[] = {
1532         RX1_B_MARK, TX1_B_MARK,
1533 };
1534
1535 /* - SCIF3 ------------------------------------------------------------------ */
1536 static const unsigned int scif3_data_pins[] = {
1537         /* RX, TX */
1538         RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1539 };
1540 static const unsigned int scif3_data_mux[] = {
1541         RX3_MARK, TX3_MARK,
1542 };
1543 static const unsigned int scif3_clk_pins[] = {
1544         /* SCK */
1545         RCAR_GP_PIN(2, 0),
1546 };
1547 static const unsigned int scif3_clk_mux[] = {
1548         SCK3_MARK,
1549 };
1550 static const unsigned int scif3_ctrl_pins[] = {
1551         /* RTS, CTS */
1552         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1553 };
1554 static const unsigned int scif3_ctrl_mux[] = {
1555         RTS3_N_TANS_MARK, CTS3_N_MARK,
1556 };
1557
1558 /* - SCIF4 ------------------------------------------------------------------ */
1559 static const unsigned int scif4_data_pins[] = {
1560         /* RX, TX */
1561         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1562 };
1563 static const unsigned int scif4_data_mux[] = {
1564         RX4_MARK, TX4_MARK,
1565 };
1566 static const unsigned int scif4_clk_pins[] = {
1567         /* SCK */
1568         RCAR_GP_PIN(3, 9),
1569 };
1570 static const unsigned int scif4_clk_mux[] = {
1571         SCK4_MARK,
1572 };
1573 static const unsigned int scif4_ctrl_pins[] = {
1574         /* RTS, CTS */
1575         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1576 };
1577 static const unsigned int scif4_ctrl_mux[] = {
1578         RTS4_N_TANS_MARK, CTS4_N_MARK,
1579 };
1580
1581 /* - MMC -------------------------------------------------------------------- */
1582 static const unsigned int mmc_data1_pins[] = {
1583         /* D0 */
1584         RCAR_GP_PIN(3, 6),
1585 };
1586 static const unsigned int mmc_data1_mux[] = {
1587         MMC_D0_MARK,
1588 };
1589 static const unsigned int mmc_data4_pins[] = {
1590         /* D[0:3] */
1591         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1592         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1593 };
1594 static const unsigned int mmc_data4_mux[] = {
1595         MMC_D0_MARK, MMC_D1_MARK,
1596         MMC_D2_MARK, MMC_D3_MARK,
1597 };
1598 static const unsigned int mmc_data8_pins[] = {
1599         /* D[0:7] */
1600         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1601         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1602         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1603         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1604 };
1605 static const unsigned int mmc_data8_mux[] = {
1606         MMC_D0_MARK, MMC_D1_MARK,
1607         MMC_D2_MARK, MMC_D3_MARK,
1608         MMC_D4_MARK, MMC_D5_MARK,
1609         MMC_D6_MARK, MMC_D7_MARK,
1610 };
1611 static const unsigned int mmc_ctrl_pins[] = {
1612         /* CLK, CMD */
1613         RCAR_GP_PIN(3,10), RCAR_GP_PIN(3, 5),
1614 };
1615 static const unsigned int mmc_ctrl_mux[] = {
1616         MMC_CLK_MARK, MMC_CMD_MARK,
1617 };
1618 static const unsigned int mmc_cd_pins[] = {
1619         /* CD */
1620         RCAR_GP_PIN(3, 16),
1621 };
1622 static const unsigned int mmc_cd_mux[] = {
1623         MMC_CD_MARK,
1624 };
1625 static const unsigned int mmc_wp_pins[] = {
1626         /* WP */
1627         RCAR_GP_PIN(3, 15),
1628 };
1629 static const unsigned int mmc_wp_mux[] = {
1630         MMC_WP_MARK,
1631 };
1632
1633 /* - TMU -------------------------------------------------------------------- */
1634 static const unsigned int tmu_tclk1_a_pins[] = {
1635         /* TCLK1 */
1636         RCAR_GP_PIN(4, 4),
1637 };
1638 static const unsigned int tmu_tclk1_a_mux[] = {
1639         TCLK1_A_MARK,
1640 };
1641 static const unsigned int tmu_tclk1_b_pins[] = {
1642         /* TCLK1 */
1643         RCAR_GP_PIN(1, 23),
1644 };
1645 static const unsigned int tmu_tclk1_b_mux[] = {
1646         TCLK1_B_MARK,
1647 };
1648 static const unsigned int tmu_tclk2_a_pins[] = {
1649         /* TCLK2 */
1650         RCAR_GP_PIN(4, 5),
1651 };
1652 static const unsigned int tmu_tclk2_a_mux[] = {
1653         TCLK2_A_MARK,
1654 };
1655 static const unsigned int tmu_tclk2_b_pins[] = {
1656         /* TCLK2 */
1657         RCAR_GP_PIN(1, 24),
1658 };
1659 static const unsigned int tmu_tclk2_b_mux[] = {
1660         TCLK2_B_MARK,
1661 };
1662
1663 /* - VIN0 ------------------------------------------------------------------- */
1664 static const unsigned int vin0_data8_pins[] = {
1665         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1666         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1667         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1668         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1669 };
1670 static const unsigned int vin0_data8_mux[] = {
1671         VI0_DATA0_MARK, VI0_DATA1_MARK,
1672         VI0_DATA2_MARK, VI0_DATA3_MARK,
1673         VI0_DATA4_MARK, VI0_DATA5_MARK,
1674         VI0_DATA6_MARK, VI0_DATA7_MARK,
1675 };
1676 static const unsigned int vin0_data10_pins[] = {
1677         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1678         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1679         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1680         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1681         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1682 };
1683 static const unsigned int vin0_data10_mux[] = {
1684         VI0_DATA0_MARK, VI0_DATA1_MARK,
1685         VI0_DATA2_MARK, VI0_DATA3_MARK,
1686         VI0_DATA4_MARK, VI0_DATA5_MARK,
1687         VI0_DATA6_MARK, VI0_DATA7_MARK,
1688         VI0_DATA8_MARK,  VI0_DATA9_MARK,
1689 };
1690 static const unsigned int vin0_data12_pins[] = {
1691         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1692         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1693         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1694         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1695         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1696         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1697 };
1698 static const unsigned int vin0_data12_mux[] = {
1699         VI0_DATA0_MARK, VI0_DATA1_MARK,
1700         VI0_DATA2_MARK, VI0_DATA3_MARK,
1701         VI0_DATA4_MARK, VI0_DATA5_MARK,
1702         VI0_DATA6_MARK, VI0_DATA7_MARK,
1703         VI0_DATA8_MARK,  VI0_DATA9_MARK,
1704         VI0_DATA10_MARK, VI0_DATA11_MARK,
1705 };
1706 static const unsigned int vin0_sync_pins[] = {
1707         /* VSYNC_N, HSYNC_N */
1708         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1709 };
1710 static const unsigned int vin0_sync_mux[] = {
1711         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1712 };
1713 static const unsigned int vin0_field_pins[] = {
1714         /* FIELD */
1715         RCAR_GP_PIN(2, 16),
1716 };
1717 static const unsigned int vin0_field_mux[] = {
1718         VI0_FIELD_MARK,
1719 };
1720 static const unsigned int vin0_clkenb_pins[] = {
1721         /* CLKENB */
1722         RCAR_GP_PIN(2, 1),
1723 };
1724 static const unsigned int vin0_clkenb_mux[] = {
1725         VI0_CLKENB_MARK,
1726 };
1727 static const unsigned int vin0_clk_pins[] = {
1728         /* CLK */
1729         RCAR_GP_PIN(2, 0),
1730 };
1731 static const unsigned int vin0_clk_mux[] = {
1732         VI0_CLK_MARK,
1733 };
1734 /* - VIN1 ------------------------------------------------------------------- */
1735 static const unsigned int vin1_data8_pins[] = {
1736         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1737         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1738         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1739         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1740 };
1741 static const unsigned int vin1_data8_mux[] = {
1742         VI1_DATA0_MARK, VI1_DATA1_MARK,
1743         VI1_DATA2_MARK, VI1_DATA3_MARK,
1744         VI1_DATA4_MARK, VI1_DATA5_MARK,
1745         VI1_DATA6_MARK, VI1_DATA7_MARK,
1746 };
1747 static const unsigned int vin1_data10_pins[] = {
1748         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1749         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1750         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1751         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1752         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1753 };
1754 static const unsigned int vin1_data10_mux[] = {
1755         VI1_DATA0_MARK, VI1_DATA1_MARK,
1756         VI1_DATA2_MARK, VI1_DATA3_MARK,
1757         VI1_DATA4_MARK, VI1_DATA5_MARK,
1758         VI1_DATA6_MARK, VI1_DATA7_MARK,
1759         VI1_DATA8_MARK,  VI1_DATA9_MARK,
1760 };
1761 static const unsigned int vin1_data12_pins[] = {
1762         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1763         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1764         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1765         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1766         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1767         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1768 };
1769 static const unsigned int vin1_data12_mux[] = {
1770         VI1_DATA0_MARK, VI1_DATA1_MARK,
1771         VI1_DATA2_MARK, VI1_DATA3_MARK,
1772         VI1_DATA4_MARK, VI1_DATA5_MARK,
1773         VI1_DATA6_MARK, VI1_DATA7_MARK,
1774         VI1_DATA8_MARK,  VI1_DATA9_MARK,
1775         VI1_DATA10_MARK, VI1_DATA11_MARK,
1776 };
1777 static const unsigned int vin1_sync_pins[] = {
1778         /* VSYNC_N, HSYNC_N */
1779          RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1780 };
1781 static const unsigned int vin1_sync_mux[] = {
1782         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1783 };
1784 static const unsigned int vin1_field_pins[] = {
1785         /* FIELD */
1786         RCAR_GP_PIN(3, 16),
1787 };
1788 static const unsigned int vin1_field_mux[] = {
1789         VI1_FIELD_MARK,
1790 };
1791 static const unsigned int vin1_clkenb_pins[] = {
1792         /* CLKENB */
1793         RCAR_GP_PIN(3, 1),
1794 };
1795 static const unsigned int vin1_clkenb_mux[] = {
1796         VI1_CLKENB_MARK,
1797 };
1798 static const unsigned int vin1_clk_pins[] = {
1799         /* CLK */
1800         RCAR_GP_PIN(3, 0),
1801 };
1802 static const unsigned int vin1_clk_mux[] = {
1803         VI1_CLK_MARK,
1804 };
1805
1806 static const struct sh_pfc_pin_group pinmux_groups[] = {
1807         SH_PFC_PIN_GROUP(avb0_rx_ctrl),
1808         SH_PFC_PIN_GROUP(avb0_rxc),
1809         SH_PFC_PIN_GROUP(avb0_rd0),
1810         SH_PFC_PIN_GROUP(avb0_rd1),
1811         SH_PFC_PIN_GROUP(avb0_rd2),
1812         SH_PFC_PIN_GROUP(avb0_rd3),
1813         SH_PFC_PIN_GROUP(avb0_rd4),
1814         SH_PFC_PIN_GROUP(avb0_tx_ctrl),
1815         SH_PFC_PIN_GROUP(avb0_txc),
1816         SH_PFC_PIN_GROUP(avb0_td0),
1817         SH_PFC_PIN_GROUP(avb0_td1),
1818         SH_PFC_PIN_GROUP(avb0_td2),
1819         SH_PFC_PIN_GROUP(avb0_td3),
1820         SH_PFC_PIN_GROUP(avb0_td4),
1821         SH_PFC_PIN_GROUP(avb0_txcrefclk),
1822         SH_PFC_PIN_GROUP(avb0_mdio),
1823         SH_PFC_PIN_GROUP(avb0_mdc),
1824         SH_PFC_PIN_GROUP(avb0_magic),
1825         SH_PFC_PIN_GROUP(avb0_phy_int),
1826         SH_PFC_PIN_GROUP(avb0_link),
1827         SH_PFC_PIN_GROUP(avb0_avtp_match),
1828         SH_PFC_PIN_GROUP(avb0_avtp_pps),
1829         SH_PFC_PIN_GROUP(avb0_avtp_capture),
1830         SH_PFC_PIN_GROUP(canfd0_data_a),
1831         SH_PFC_PIN_GROUP(canfd_clk_a),
1832         SH_PFC_PIN_GROUP(canfd0_data_b),
1833         SH_PFC_PIN_GROUP(canfd_clk_b),
1834         SH_PFC_PIN_GROUP(canfd1_data),
1835         SH_PFC_PIN_GROUP(du_rgb666),
1836         SH_PFC_PIN_GROUP(du_clk_out_0),
1837         SH_PFC_PIN_GROUP(du_clk_out_1),
1838         SH_PFC_PIN_GROUP(du_sync),
1839         SH_PFC_PIN_GROUP(du_oddf),
1840         SH_PFC_PIN_GROUP(du_cde),
1841         SH_PFC_PIN_GROUP(du_disp),
1842         SH_PFC_PIN_GROUP(hscif0_data),
1843         SH_PFC_PIN_GROUP(hscif0_clk),
1844         SH_PFC_PIN_GROUP(hscif0_ctrl),
1845         SH_PFC_PIN_GROUP(hscif1_data),
1846         SH_PFC_PIN_GROUP(hscif1_clk),
1847         SH_PFC_PIN_GROUP(hscif1_ctrl),
1848         SH_PFC_PIN_GROUP(hscif2_data),
1849         SH_PFC_PIN_GROUP(hscif2_clk),
1850         SH_PFC_PIN_GROUP(hscif2_ctrl),
1851         SH_PFC_PIN_GROUP(hscif3_data),
1852         SH_PFC_PIN_GROUP(hscif3_clk),
1853         SH_PFC_PIN_GROUP(hscif3_ctrl),
1854         SH_PFC_PIN_GROUP(scif_clk_a),
1855         SH_PFC_PIN_GROUP(scif_clk_b),
1856         SH_PFC_PIN_GROUP(i2c0),
1857         SH_PFC_PIN_GROUP(i2c1),
1858         SH_PFC_PIN_GROUP(i2c2),
1859         SH_PFC_PIN_GROUP(i2c3),
1860         SH_PFC_PIN_GROUP(i2c4),
1861         SH_PFC_PIN_GROUP(intc_ex_irq0),
1862         SH_PFC_PIN_GROUP(intc_ex_irq1),
1863         SH_PFC_PIN_GROUP(intc_ex_irq2),
1864         SH_PFC_PIN_GROUP(intc_ex_irq3),
1865         SH_PFC_PIN_GROUP(intc_ex_irq4),
1866         SH_PFC_PIN_GROUP(intc_ex_irq5),
1867         SH_PFC_PIN_GROUP(msiof0_clk),
1868         SH_PFC_PIN_GROUP(msiof0_sync),
1869         SH_PFC_PIN_GROUP(msiof0_ss1),
1870         SH_PFC_PIN_GROUP(msiof0_ss2),
1871         SH_PFC_PIN_GROUP(msiof0_txd),
1872         SH_PFC_PIN_GROUP(msiof0_rxd),
1873         SH_PFC_PIN_GROUP(msiof1_clk),
1874         SH_PFC_PIN_GROUP(msiof1_sync),
1875         SH_PFC_PIN_GROUP(msiof1_ss1),
1876         SH_PFC_PIN_GROUP(msiof1_ss2),
1877         SH_PFC_PIN_GROUP(msiof1_txd),
1878         SH_PFC_PIN_GROUP(msiof1_rxd),
1879         SH_PFC_PIN_GROUP(msiof2_clk),
1880         SH_PFC_PIN_GROUP(msiof2_sync),
1881         SH_PFC_PIN_GROUP(msiof2_ss1),
1882         SH_PFC_PIN_GROUP(msiof2_ss2),
1883         SH_PFC_PIN_GROUP(msiof2_txd),
1884         SH_PFC_PIN_GROUP(msiof2_rxd),
1885         SH_PFC_PIN_GROUP(msiof3_clk),
1886         SH_PFC_PIN_GROUP(msiof3_sync),
1887         SH_PFC_PIN_GROUP(msiof3_ss1),
1888         SH_PFC_PIN_GROUP(msiof3_ss2),
1889         SH_PFC_PIN_GROUP(msiof3_txd),
1890         SH_PFC_PIN_GROUP(msiof3_rxd),
1891         SH_PFC_PIN_GROUP(pwm0_a),
1892         SH_PFC_PIN_GROUP(pwm0_b),
1893         SH_PFC_PIN_GROUP(pwm1_a),
1894         SH_PFC_PIN_GROUP(pwm1_b),
1895         SH_PFC_PIN_GROUP(pwm2_a),
1896         SH_PFC_PIN_GROUP(pwm2_b),
1897         SH_PFC_PIN_GROUP(pwm3_a),
1898         SH_PFC_PIN_GROUP(pwm3_b),
1899         SH_PFC_PIN_GROUP(pwm4_a),
1900         SH_PFC_PIN_GROUP(pwm4_b),
1901         SH_PFC_PIN_GROUP(scif0_data),
1902         SH_PFC_PIN_GROUP(scif0_clk),
1903         SH_PFC_PIN_GROUP(scif0_ctrl),
1904         SH_PFC_PIN_GROUP(scif1_data_a),
1905         SH_PFC_PIN_GROUP(scif1_clk),
1906         SH_PFC_PIN_GROUP(scif1_ctrl),
1907         SH_PFC_PIN_GROUP(scif1_data_b),
1908         SH_PFC_PIN_GROUP(scif3_data),
1909         SH_PFC_PIN_GROUP(scif3_clk),
1910         SH_PFC_PIN_GROUP(scif3_ctrl),
1911         SH_PFC_PIN_GROUP(scif4_data),
1912         SH_PFC_PIN_GROUP(scif4_clk),
1913         SH_PFC_PIN_GROUP(scif4_ctrl),
1914         SH_PFC_PIN_GROUP(mmc_data1),
1915         SH_PFC_PIN_GROUP(mmc_data4),
1916         SH_PFC_PIN_GROUP(mmc_data8),
1917         SH_PFC_PIN_GROUP(mmc_ctrl),
1918         SH_PFC_PIN_GROUP(mmc_cd),
1919         SH_PFC_PIN_GROUP(mmc_wp),
1920         SH_PFC_PIN_GROUP(tmu_tclk1_a),
1921         SH_PFC_PIN_GROUP(tmu_tclk1_b),
1922         SH_PFC_PIN_GROUP(tmu_tclk2_a),
1923         SH_PFC_PIN_GROUP(tmu_tclk2_b),
1924         SH_PFC_PIN_GROUP(vin0_data8),
1925         SH_PFC_PIN_GROUP(vin0_data10),
1926         SH_PFC_PIN_GROUP(vin0_data12),
1927         SH_PFC_PIN_GROUP(vin0_sync),
1928         SH_PFC_PIN_GROUP(vin0_field),
1929         SH_PFC_PIN_GROUP(vin0_clkenb),
1930         SH_PFC_PIN_GROUP(vin0_clk),
1931         SH_PFC_PIN_GROUP(vin1_data8),
1932         SH_PFC_PIN_GROUP(vin1_data10),
1933         SH_PFC_PIN_GROUP(vin1_data12),
1934         SH_PFC_PIN_GROUP(vin1_sync),
1935         SH_PFC_PIN_GROUP(vin1_field),
1936         SH_PFC_PIN_GROUP(vin1_clkenb),
1937         SH_PFC_PIN_GROUP(vin1_clk),
1938 };
1939
1940 static const char * const avb0_groups[] = {
1941         "avb0_rx_ctrl",
1942         "avb0_rxc",
1943         "avb0_rd1",
1944         "avb0_rd4",
1945         "avb0_tx_ctrl",
1946         "avb0_txc",
1947         "avb0_td1",
1948         "avb0_td4",
1949         "avb0_txcrefclk",
1950         "avb0_mdio",
1951         "avb0_mdc",
1952         "avb0_magic",
1953         "avb0_phy_int",
1954         "avb0_link",
1955         "avb0_avtp_match",
1956         "avb0_avtp_pps",
1957         "avb0_avtp_capture",
1958 };
1959
1960 static const char * const canfd0_groups[] = {
1961         "canfd0_data_a",
1962         "canfd_clk_a",
1963         "canfd0_data_b",
1964         "canfd_clk_b",
1965 };
1966
1967 static const char * const canfd1_groups[] = {
1968         "canfd1_data",
1969 };
1970
1971 static const char * const du_groups[] = {
1972         "du_rgb666",
1973         "du_clk_out_0",
1974         "du_clk_out_1",
1975         "du_sync",
1976         "du_oddf",
1977         "du_cde",
1978         "du_disp",
1979 };
1980
1981 static const char * const hscif0_groups[] = {
1982         "hscif0_data",
1983         "hscif0_clk",
1984         "hscif0_ctrl",
1985 };
1986
1987 static const char * const hscif1_groups[] = {
1988         "hscif1_data",
1989         "hscif1_clk",
1990         "hscif1_ctrl",
1991 };
1992
1993 static const char * const hscif2_groups[] = {
1994         "hscif2_data",
1995         "hscif2_clk",
1996         "hscif2_ctrl",
1997 };
1998
1999 static const char * const hscif3_groups[] = {
2000         "hscif3_data",
2001         "hscif3_clk",
2002         "hscif3_ctrl",
2003 };
2004
2005 static const char * const scif_clk_groups[] = {
2006         "scif_clk_a",
2007         "scif_clk_b",
2008 };
2009
2010 static const char * const i2c0_groups[] = {
2011         "i2c0",
2012 };
2013
2014 static const char * const i2c1_groups[] = {
2015         "i2c1",
2016 };
2017
2018 static const char * const i2c2_groups[] = {
2019         "i2c2",
2020 };
2021
2022 static const char * const i2c3_groups[] = {
2023         "i2c3",
2024 };
2025
2026 static const char * const i2c4_groups[] = {
2027         "i2c4",
2028 };
2029
2030 static const char * const intc_ex_groups[] = {
2031         "intc_ex_irq0",
2032         "intc_ex_irq1",
2033         "intc_ex_irq2",
2034         "intc_ex_irq3",
2035         "intc_ex_irq4",
2036         "intc_ex_irq5",
2037 };
2038
2039 static const char * const msiof0_groups[] = {
2040         "msiof0_clk",
2041         "msiof0_sync",
2042         "msiof0_ss1",
2043         "msiof0_ss2",
2044         "msiof0_txd",
2045         "msiof0_rxd",
2046 };
2047
2048 static const char * const msiof1_groups[] = {
2049         "msiof1_clk",
2050         "msiof1_sync",
2051         "msiof1_ss1",
2052         "msiof1_ss2",
2053         "msiof1_txd",
2054         "msiof1_rxd",
2055 };
2056
2057 static const char * const msiof2_groups[] = {
2058         "msiof2_clk",
2059         "msiof2_sync",
2060         "msiof2_ss1",
2061         "msiof2_ss2",
2062         "msiof2_txd",
2063         "msiof2_rxd",
2064 };
2065
2066 static const char * const msiof3_groups[] = {
2067         "msiof3_clk",
2068         "msiof3_sync",
2069         "msiof3_ss1",
2070         "msiof3_ss2",
2071         "msiof3_txd",
2072         "msiof3_rxd",
2073 };
2074
2075 static const char * const pwm0_groups[] = {
2076         "pwm0_a",
2077         "pwm0_b",
2078 };
2079
2080 static const char * const pwm1_groups[] = {
2081         "pwm1_a",
2082         "pwm1_b",
2083 };
2084
2085 static const char * const pwm2_groups[] = {
2086         "pwm2_a",
2087         "pwm2_b",
2088 };
2089
2090 static const char * const pwm3_groups[] = {
2091         "pwm3_a",
2092         "pwm3_b",
2093 };
2094
2095 static const char * const pwm4_groups[] = {
2096         "pwm4_a",
2097         "pwm4_b",
2098 };
2099
2100 static const char * const scif0_groups[] = {
2101         "scif0_data",
2102 //      "scif0_clk",
2103 //      "scif0_ctrl",
2104 };
2105
2106 static const char * const scif1_groups[] = {
2107         "scif1_data_a",
2108         "scif1_clk",
2109         "scif1_ctrl",
2110         "scif1_data_b",
2111 };
2112
2113 static const char * const scif3_groups[] = {
2114         "scif3_data",
2115         "scif3_clk",
2116         "scif3_ctrl",
2117 };
2118
2119 static const char * const scif4_groups[] = {
2120         "scif4_data",
2121         "scif4_clk",
2122         "scif4_ctrl",
2123 };
2124
2125 static const char * const mmc_groups[] = {
2126         "mmc_data1",
2127         "mmc_data4",
2128         "mmc_data8",
2129         "mmc_ctrl",
2130         "mmc_cd",
2131         "mmc_wp",
2132 };
2133
2134 static const char * const tmu_groups[] = {
2135         "tmu_tclk1_a",
2136         "tmu_tclk1_b",
2137         "tmu_tclk2_a",
2138         "tmu_tclk2_b",
2139 };
2140
2141 static const char * const vin0_groups[] = {
2142         "vin0_data8",
2143         "vin0_data10",
2144         "vin0_data12",
2145         "vin0_sync",
2146         "vin0_field",
2147         "vin0_clkenb",
2148         "vin0_clk",
2149 };
2150
2151 static const char * const vin1_groups[] = {
2152         "vin1_data8",
2153         "vin1_data10",
2154         "vin1_data12",
2155         "vin1_sync",
2156         "vin1_field",
2157         "vin1_clkenb",
2158         "vin1_clk",
2159 };
2160
2161 #define POCCTRL0        0x380
2162 #define POCCTRL1        0x384
2163 #define PIN2POCCTRL0_SHIFT(a) ({ \
2164         int _gp = (a) >> 5; \
2165         int _bit = (a) & 0x1f; \
2166         ((_gp == 3) && (_bit < 17)) ? _bit + 7 : -1; \
2167 })
2168
2169
2170 static const struct sh_pfc_function pinmux_functions[] = {
2171         SH_PFC_FUNCTION(avb0),
2172         SH_PFC_FUNCTION(canfd0),
2173         SH_PFC_FUNCTION(canfd1),
2174         SH_PFC_FUNCTION(du),
2175         SH_PFC_FUNCTION(hscif0),
2176         SH_PFC_FUNCTION(hscif1),
2177         SH_PFC_FUNCTION(hscif2),
2178         SH_PFC_FUNCTION(hscif3),
2179         SH_PFC_FUNCTION(scif_clk),
2180         SH_PFC_FUNCTION(i2c0),
2181         SH_PFC_FUNCTION(i2c1),
2182         SH_PFC_FUNCTION(i2c2),
2183         SH_PFC_FUNCTION(i2c3),
2184         SH_PFC_FUNCTION(i2c4),
2185         SH_PFC_FUNCTION(intc_ex),
2186         SH_PFC_FUNCTION(msiof0),
2187         SH_PFC_FUNCTION(msiof1),
2188         SH_PFC_FUNCTION(msiof2),
2189         SH_PFC_FUNCTION(msiof3),
2190         SH_PFC_FUNCTION(pwm0),
2191         SH_PFC_FUNCTION(pwm1),
2192         SH_PFC_FUNCTION(pwm2),
2193         SH_PFC_FUNCTION(pwm3),
2194         SH_PFC_FUNCTION(pwm4),
2195         SH_PFC_FUNCTION(scif0),
2196         SH_PFC_FUNCTION(scif1),
2197         SH_PFC_FUNCTION(scif3),
2198         SH_PFC_FUNCTION(scif4),
2199         SH_PFC_FUNCTION(mmc),
2200         SH_PFC_FUNCTION(tmu),
2201         SH_PFC_FUNCTION(vin0),
2202         SH_PFC_FUNCTION(vin1),
2203 };
2204
2205 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2206 #define F_(x, y)        FN_##y
2207 #define FM(x)           FN_##x
2208         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2209                 0, 0,
2210                 0, 0,
2211                 0, 0,
2212                 0, 0,
2213                 0, 0,
2214                 0, 0,
2215                 0, 0,
2216                 0, 0,
2217                 0, 0,
2218                 0, 0,
2219                 GP_0_21_FN,     GPSR0_21,
2220                 GP_0_20_FN,     GPSR0_20,
2221                 GP_0_19_FN,     GPSR0_19,
2222                 GP_0_18_FN,     GPSR0_18,
2223                 GP_0_17_FN,     GPSR0_17,
2224                 GP_0_16_FN,     GPSR0_16,
2225                 GP_0_15_FN,     GPSR0_15,
2226                 GP_0_14_FN,     GPSR0_14,
2227                 GP_0_13_FN,     GPSR0_13,
2228                 GP_0_12_FN,     GPSR0_12,
2229                 GP_0_11_FN,     GPSR0_11,
2230                 GP_0_10_FN,     GPSR0_10,
2231                 GP_0_9_FN,      GPSR0_9,
2232                 GP_0_8_FN,      GPSR0_8,
2233                 GP_0_7_FN,      GPSR0_7,
2234                 GP_0_6_FN,      GPSR0_6,
2235                 GP_0_5_FN,      GPSR0_5,
2236                 GP_0_4_FN,      GPSR0_4,
2237                 GP_0_3_FN,      GPSR0_3,
2238                 GP_0_2_FN,      GPSR0_2,
2239                 GP_0_1_FN,      GPSR0_1,
2240                 GP_0_0_FN,      GPSR0_0, }
2241         },
2242         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2243                 0, 0,
2244                 0, 0,
2245                 0, 0,
2246                 0, 0,
2247                 GP_1_27_FN,     GPSR1_27,
2248                 GP_1_26_FN,     GPSR1_26,
2249                 GP_1_25_FN,     GPSR1_25,
2250                 GP_1_24_FN,     GPSR1_24,
2251                 GP_1_23_FN,     GPSR1_23,
2252                 GP_1_22_FN,     GPSR1_22,
2253                 GP_1_21_FN,     GPSR1_21,
2254                 GP_1_20_FN,     GPSR1_20,
2255                 GP_1_19_FN,     GPSR1_19,
2256                 GP_1_18_FN,     GPSR1_18,
2257                 GP_1_17_FN,     GPSR1_17,
2258                 GP_1_16_FN,     GPSR1_16,
2259                 GP_1_15_FN,     GPSR1_15,
2260                 GP_1_14_FN,     GPSR1_14,
2261                 GP_1_13_FN,     GPSR1_13,
2262                 GP_1_12_FN,     GPSR1_12,
2263                 GP_1_11_FN,     GPSR1_11,
2264                 GP_1_10_FN,     GPSR1_10,
2265                 GP_1_9_FN,      GPSR1_9,
2266                 GP_1_8_FN,      GPSR1_8,
2267                 GP_1_7_FN,      GPSR1_7,
2268                 GP_1_6_FN,      GPSR1_6,
2269                 GP_1_5_FN,      GPSR1_5,
2270                 GP_1_4_FN,      GPSR1_4,
2271                 GP_1_3_FN,      GPSR1_3,
2272                 GP_1_2_FN,      GPSR1_2,
2273                 GP_1_1_FN,      GPSR1_1,
2274                 GP_1_0_FN,      GPSR1_0, }
2275         },
2276         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2277                 0, 0,
2278                 0, 0,
2279                 0, 0,
2280                 0, 0,
2281                 0, 0,
2282                 0, 0,
2283                 0, 0,
2284                 0, 0,
2285                 0, 0,
2286                 0, 0,
2287                 0, 0,
2288                 0, 0,
2289                 0, 0,
2290                 0, 0,
2291                 0, 0,
2292                 GP_2_16_FN,     GPSR2_16,
2293                 GP_2_15_FN,     GPSR2_15,
2294                 GP_2_14_FN,     GPSR2_14,
2295                 GP_2_13_FN,     GPSR2_13,
2296                 GP_2_12_FN,     GPSR2_12,
2297                 GP_2_11_FN,     GPSR2_11,
2298                 GP_2_10_FN,     GPSR2_10,
2299                 GP_2_9_FN,      GPSR2_9,
2300                 GP_2_8_FN,      GPSR2_8,
2301                 GP_2_7_FN,      GPSR2_7,
2302                 GP_2_6_FN,      GPSR2_6,
2303                 GP_2_5_FN,      GPSR2_5,
2304                 GP_2_4_FN,      GPSR2_4,
2305                 GP_2_3_FN,      GPSR2_3,
2306                 GP_2_2_FN,      GPSR2_2,
2307                 GP_2_1_FN,      GPSR2_1,
2308                 GP_2_0_FN,      GPSR2_0, }
2309         },
2310         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2311                 0, 0,
2312                 0, 0,
2313                 0, 0,
2314                 0, 0,
2315                 0, 0,
2316                 0, 0,
2317                 0, 0,
2318                 0, 0,
2319                 0, 0,
2320                 0, 0,
2321                 0, 0,
2322                 0, 0,
2323                 0, 0,
2324                 0, 0,
2325                 0, 0,
2326                 GP_3_16_FN,     GPSR3_16,
2327                 GP_3_15_FN,     GPSR3_15,
2328                 GP_3_14_FN,     GPSR3_14,
2329                 GP_3_13_FN,     GPSR3_13,
2330                 GP_3_12_FN,     GPSR3_12,
2331                 GP_3_11_FN,     GPSR3_11,
2332                 GP_3_10_FN,     GPSR3_10,
2333                 GP_3_9_FN,      GPSR3_9,
2334                 GP_3_8_FN,      GPSR3_8,
2335                 GP_3_7_FN,      GPSR3_7,
2336                 GP_3_6_FN,      GPSR3_6,
2337                 GP_3_5_FN,      GPSR3_5,
2338                 GP_3_4_FN,      GPSR3_4,
2339                 GP_3_3_FN,      GPSR3_3,
2340                 GP_3_2_FN,      GPSR3_2,
2341                 GP_3_1_FN,      GPSR3_1,
2342                 GP_3_0_FN,      GPSR3_0, }
2343         },
2344         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2345                 0, 0,
2346                 0, 0,
2347                 0, 0,
2348                 0, 0,
2349                 0, 0,
2350                 0, 0,
2351                 0, 0,
2352                 0, 0,
2353                 0, 0,
2354                 0, 0,
2355                 0, 0,
2356                 0, 0,
2357                 0, 0,
2358                 0, 0,
2359                 0, 0,
2360                 0, 0,
2361                 0, 0,
2362                 0, 0,
2363                 0, 0,
2364                 0, 0,
2365                 0, 0,
2366                 0, 0,
2367                 0, 0,
2368                 0, 0,
2369                 0, 0,
2370                 0, 0,
2371                 GP_4_5_FN,      GPSR4_5,
2372                 GP_4_4_FN,      GPSR4_4,
2373                 GP_4_3_FN,      GPSR4_3,
2374                 GP_4_2_FN,      GPSR4_2,
2375                 GP_4_1_FN,      GPSR4_1,
2376                 GP_4_0_FN,      GPSR4_0, }
2377         },
2378         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2379                 0, 0,
2380                 0, 0,
2381                 0, 0,
2382                 0, 0,
2383                 0, 0,
2384                 0, 0,
2385                 0, 0,
2386                 0, 0,
2387                 0, 0,
2388                 0, 0,
2389                 0, 0,
2390                 0, 0,
2391                 0, 0,
2392                 0, 0,
2393                 0, 0,
2394                 0, 0,
2395                 0, 0,
2396                 GP_5_14_FN,     GPSR5_14,
2397                 GP_5_13_FN,     GPSR5_13,
2398                 GP_5_12_FN,     GPSR5_12,
2399                 GP_5_11_FN,     GPSR5_11,
2400                 GP_5_10_FN,     GPSR5_10,
2401                 GP_5_9_FN,      GPSR5_9,
2402                 GP_5_8_FN,      GPSR5_8,
2403                 GP_5_7_FN,      GPSR5_7,
2404                 GP_5_6_FN,      GPSR5_6,
2405                 GP_5_5_FN,      GPSR5_5,
2406                 GP_5_4_FN,      GPSR5_4,
2407                 GP_5_3_FN,      GPSR5_3,
2408                 GP_5_2_FN,      GPSR5_2,
2409                 GP_5_1_FN,      GPSR5_1,
2410                 GP_5_0_FN,      GPSR5_0, }
2411         },
2412 #undef F_
2413 #undef FM
2414
2415 #define F_(x, y)        x,
2416 #define FM(x)           FN_##x,
2417         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2418                 IP0_31_28
2419                 IP0_27_24
2420                 IP0_23_20
2421                 IP0_19_16
2422                 IP0_15_12
2423                 IP0_11_8
2424                 IP0_7_4
2425                 IP0_3_0 }
2426         },
2427         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2428                 IP1_31_28
2429                 IP1_27_24
2430                 IP1_23_20
2431                 IP1_19_16
2432                 IP1_15_12
2433                 IP1_11_8
2434                 IP1_7_4
2435                 IP1_3_0 }
2436         },
2437         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2438                 IP2_31_28
2439                 IP2_27_24
2440                 IP2_23_20
2441                 IP2_19_16
2442                 IP2_15_12
2443                 IP2_11_8
2444                 IP2_7_4
2445                 IP2_3_0 }
2446         },
2447         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2448                 IP3_31_28
2449                 IP3_27_24
2450                 IP3_23_20
2451                 IP3_19_16
2452                 IP3_15_12
2453                 IP3_11_8
2454                 IP3_7_4
2455                 IP3_3_0 }
2456         },
2457         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2458                 IP4_31_28
2459                 IP4_27_24
2460                 IP4_23_20
2461                 IP4_19_16
2462                 IP4_15_12
2463                 IP4_11_8
2464                 IP4_7_4
2465                 IP4_3_0 }
2466         },
2467         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2468                 IP5_31_28
2469                 IP5_27_24
2470                 IP5_23_20
2471                 IP5_19_16
2472                 IP5_15_12
2473                 IP5_11_8
2474                 IP5_7_4
2475                 IP5_3_0 }
2476         },
2477         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2478                 IP6_31_28
2479                 IP6_27_24
2480                 IP6_23_20
2481                 IP6_19_16
2482                 IP6_15_12
2483                 IP6_11_8
2484                 IP6_7_4
2485                 IP6_3_0 }
2486         },
2487         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2488                 IP7_31_28
2489                 IP7_27_24
2490                 IP7_23_20
2491                 IP7_19_16
2492                 IP7_15_12
2493                 IP7_11_8
2494                 IP7_7_4
2495                 IP7_3_0 }
2496         },
2497         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2498                 IP8_31_28
2499                 IP8_27_24
2500                 IP8_23_20
2501                 IP8_19_16
2502                 IP8_15_12
2503                 IP8_11_8
2504                 IP8_7_4
2505                 IP8_3_0 }
2506         },
2507 #undef F_
2508 #undef FM
2509
2510 #define F_(x, y)        x,
2511 #define FM(x)           FN_##x,
2512         { PINMUX_CFG_REG("MOD_SEL0", 0xe6060500, 32, 1) {
2513                 /* RESERVED 31..12 */
2514                 0, 0,
2515                 0, 0,
2516                 0, 0,
2517                 0, 0,
2518                 0, 0,
2519                 0, 0,
2520                 0, 0,
2521                 0, 0,
2522                 0, 0,
2523                 0, 0,
2524                 0, 0,
2525                 0, 0,
2526                 0, 0,
2527                 0, 0,
2528                 0, 0,
2529                 0, 0,
2530                 0, 0,
2531                 0, 0,
2532                 0, 0,
2533                 0, 0,
2534                 MOD_SEL0_11
2535                 MOD_SEL0_10
2536                 MOD_SEL0_9
2537                 MOD_SEL0_8
2538                 MOD_SEL0_7
2539                 MOD_SEL0_6
2540                 MOD_SEL0_5
2541                 MOD_SEL0_4
2542                 MOD_SEL0_3
2543                 MOD_SEL0_2
2544                 MOD_SEL0_1
2545                 MOD_SEL0_0 }
2546         },
2547         { },
2548 };
2549
2550 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2551 {
2552         int bit = -EINVAL;
2553
2554         *pocctrl = 0xe6060384;
2555
2556         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2557                 bit = (pin & 0x1f) + 7;
2558
2559         return bit;
2560 }
2561
2562 static const struct sh_pfc_soc_operations pinmux_ops = {
2563         .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2564 };
2565
2566 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2567         .name = "r8a77970_pfc",
2568         .ops = &pinmux_ops,
2569         .unlock_reg = 0xe6060000, /* PMMR */
2570
2571         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2572
2573         .pins = pinmux_pins,
2574         .nr_pins = ARRAY_SIZE(pinmux_pins),
2575         .groups = pinmux_groups,
2576         .nr_groups = ARRAY_SIZE(pinmux_groups),
2577         .functions = pinmux_functions,
2578         .nr_functions = ARRAY_SIZE(pinmux_functions),
2579
2580         .cfg_regs = pinmux_config_regs,
2581
2582         .pinmux_data = pinmux_data,
2583         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2584 };