git.sur5r.net Git - u-boot/blob - drivers/pinctrl/renesas/pfc-r8a77970.c

   1 /*
   2  * R8A77970 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  *
   6  * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
   7  *
   8  * R-Car Gen3 processor support - PFC hardware block.
   9  *
  10  * Copyright (C) 2015  Renesas Electronics Corporation
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0
  13  */
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/kernel.h>
  20
  21 #include "sh_pfc.h"
  22
  23 #define CPU_ALL_PORT(fn, sfx)                                           \
  24         PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  25         PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  26         PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
  27         PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH |      \
  28                                    SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  29         PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),       \
  30         PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
  31 /*
  32  * F_() : just information
  33  * FM() : macro for FN_xxx / xxx_MARK
  34  */
  35
  36 /* GPSR0 */
  37 #define GPSR0_21        F_(DU_EXODDF_DU_ODDF_DISP_CDE,  IP2_23_20)
  38 #define GPSR0_20        F_(DU_EXVSYNC_DU_VSYNC,         IP2_19_16)
  39 #define GPSR0_19        F_(DU_EXHSYNC_DU_HSYNC,         IP2_15_12)
  40 #define GPSR0_18        F_(DU_DOTCLKOUT,                IP2_11_8)
  41 #define GPSR0_17        F_(DU_DB7,                      IP2_7_4)
  42 #define GPSR0_16        F_(DU_DB6,                      IP2_3_0)
  43 #define GPSR0_15        F_(DU_DB5,                      IP1_31_28)
  44 #define GPSR0_14        F_(DU_DB4,                      IP1_27_24)
  45 #define GPSR0_13        F_(DU_DB3,                      IP1_23_20)
  46 #define GPSR0_12        F_(DU_DB2,                      IP1_19_16)
  47 #define GPSR0_11        F_(DU_DG7,                      IP1_15_12)
  48 #define GPSR0_10        F_(DU_DG6,                      IP1_11_8)
  49 #define GPSR0_9         F_(DU_DG5,                      IP1_7_4)
  50 #define GPSR0_8         F_(DU_DG4,                      IP1_3_0)
  51 #define GPSR0_7         F_(DU_DG3,                      IP0_31_28)
  52 #define GPSR0_6         F_(DU_DG2,                      IP0_27_24)
  53 #define GPSR0_5         F_(DU_DR7,                      IP0_23_20)
  54 #define GPSR0_4         F_(DU_DR6,                      IP0_19_16)
  55 #define GPSR0_3         F_(DU_DR5,                      IP0_15_12)
  56 #define GPSR0_2         F_(DU_DR4,                      IP0_11_8)
  57 #define GPSR0_1         F_(DU_DR3,                      IP0_7_4)
  58 #define GPSR0_0         F_(DU_DR2,                      IP0_3_0)
  59
  60 /* GPSR1 */
  61 #define GPSR1_27        F_(DIGRF_CLKOUT,        IP8_27_24)
  62 #define GPSR1_26        F_(DIGRF_CLKIN,         IP8_23_20)
  63 #define GPSR1_25        F_(CANFD_CLK_A,         IP8_19_16)
  64 #define GPSR1_24        F_(CANFD1_RX,           IP8_15_12)
  65 #define GPSR1_23        F_(CANFD1_TX,           IP8_11_8)
  66 #define GPSR1_22        F_(CANFD0_RX_A,         IP8_7_4)
  67 #define GPSR1_21        F_(CANFD0_TX_A,         IP8_3_0)
  68 #define GPSR1_20        F_(AVB0_AVTP_CAPTURE,   IP7_31_28)
  69 #define GPSR1_19        FM(AVB0_AVTP_MATCH)
  70 #define GPSR1_18        FM(AVB0_LINK)
  71 #define GPSR1_17        FM(AVB0_PHY_INT)
  72 #define GPSR1_16        FM(AVB0_MAGIC)
  73 #define GPSR1_15        FM(AVB0_MDC)
  74 #define GPSR1_14        FM(AVB0_MDIO)
  75 #define GPSR1_13        FM(AVB0_TXCREFCLK)
  76 #define GPSR1_12        FM(AVB0_TD3)
  77 #define GPSR1_11        FM(AVB0_TD2)
  78 #define GPSR1_10        FM(AVB0_TD1)
  79 #define GPSR1_9         FM(AVB0_TD0)
  80 #define GPSR1_8         FM(AVB0_TXC)
  81 #define GPSR1_7         FM(AVB0_TX_CTL)
  82 #define GPSR1_6         FM(AVB0_RD3)
  83 #define GPSR1_5         FM(AVB0_RD2)
  84 #define GPSR1_4         FM(AVB0_RD1)
  85 #define GPSR1_3         FM(AVB0_RD0)
  86 #define GPSR1_2         FM(AVB0_RXC)
  87 #define GPSR1_1         FM(AVB0_RX_CTL)
  88 #define GPSR1_0         F_(IRQ0,                IP2_27_24)
  89
  90 /* GPSR2 */
  91 #define GPSR2_16        F_(VI0_FIELD,           IP4_31_28)
  92 #define GPSR2_15        F_(VI0_DATA11,          IP4_27_24)
  93 #define GPSR2_14        F_(VI0_DATA10,          IP4_23_20)
  94 #define GPSR2_13        F_(VI0_DATA9,           IP4_19_16)
  95 #define GPSR2_12        F_(VI0_DATA8,           IP4_15_12)
  96 #define GPSR2_11        F_(VI0_DATA7,           IP4_11_8)
  97 #define GPSR2_10        F_(VI0_DATA6,           IP4_7_4)
  98 #define GPSR2_9         F_(VI0_DATA5,           IP4_3_0)
  99 #define GPSR2_8         F_(VI0_DATA4,           IP3_31_28)
 100 #define GPSR2_7         F_(VI0_DATA3,           IP3_27_24)
 101 #define GPSR2_6         F_(VI0_DATA2,           IP3_23_20)
 102 #define GPSR2_5         F_(VI0_DATA1,           IP3_19_16)
 103 #define GPSR2_4         F_(VI0_DATA0,           IP3_15_12)
 104 #define GPSR2_3         F_(VI0_VSYNC_N,         IP3_11_8)
 105 #define GPSR2_2         F_(VI0_HSYNC_N,         IP3_7_4)
 106 #define GPSR2_1         F_(VI0_CLKENB,          IP3_3_0)
 107 #define GPSR2_0         F_(VI0_CLK,             IP2_31_28)
 108
 109 /* GPSR3 */
 110 #define GPSR3_16        F_(VI1_FIELD,           IP7_3_0)
 111 #define GPSR3_15        F_(VI1_DATA11,          IP6_31_28)
 112 #define GPSR3_14        F_(VI1_DATA10,          IP6_27_24)
 113 #define GPSR3_13        F_(VI1_DATA9,           IP6_23_20)
 114 #define GPSR3_12        F_(VI1_DATA8,           IP6_19_16)
 115 #define GPSR3_11        F_(VI1_DATA7,           IP6_15_12)
 116 #define GPSR3_10        F_(VI1_DATA6,           IP6_11_8)
 117 #define GPSR3_9         F_(VI1_DATA5,           IP6_7_4)
 118 #define GPSR3_8         F_(VI1_DATA4,           IP6_3_0)
 119 #define GPSR3_7         F_(VI1_DATA3,           IP5_31_28)
 120 #define GPSR3_6         F_(VI1_DATA2,           IP5_27_24)
 121 #define GPSR3_5         F_(VI1_DATA1,           IP5_23_20)
 122 #define GPSR3_4         F_(VI1_DATA0,           IP5_19_16)
 123 #define GPSR3_3         F_(VI1_VSYNC_N,         IP5_15_12)
 124 #define GPSR3_2         F_(VI1_HSYNC_N,         IP5_11_8)
 125 #define GPSR3_1         F_(VI1_CLKENB,          IP5_7_4)
 126 #define GPSR3_0         F_(VI1_CLK,             IP5_3_0)
 127
 128 /* GPSR4 */
 129 #define GPSR4_5         F_(SDA2,                IP7_27_24)
 130 #define GPSR4_4         F_(SCL2,                IP7_23_20)
 131 #define GPSR4_3         F_(SDA1,                IP7_19_16)
 132 #define GPSR4_2         F_(SCL1,                IP7_15_12)
 133 #define GPSR4_1         F_(SDA0,                IP7_11_8)
 134 #define GPSR4_0         F_(SCL0,                IP7_7_4)
 135
 136 /* GPSR5 */
 137 #define GPSR5_14        FM(RPC_INT_N)
 138 #define GPSR5_13        FM(RPC_WP_N)
 139 #define GPSR5_12        FM(RPC_RESET_N)
 140 #define GPSR5_11        FM(QSPI1_SSL)
 141 #define GPSR5_10        FM(QSPI1_IO3)
 142 #define GPSR5_9         FM(QSPI1_IO2)
 143 #define GPSR5_8         FM(QSPI1_MISO_IO1)
 144 #define GPSR5_7         FM(QSPI1_MOSI_IO0)
 145 #define GPSR5_6         FM(QSPI1_SPCLK)
 146 #define GPSR5_5         FM(QSPI0_SSL)
 147 #define GPSR5_4         FM(QSPI0_IO3)
 148 #define GPSR5_3         FM(QSPI0_IO2)
 149 #define GPSR5_2         FM(QSPI0_MISO_IO1)
 150 #define GPSR5_1         FM(QSPI0_MOSI_IO0)
 151 #define GPSR5_0         FM(QSPI0_SPCLK)
 152
 153
 154 /* IPSRx */             /* 0 */                         /* 1 */                 /* 2 */         /* 3 */         /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 */         /* A */         /* B */         /* C */         /* D */         /* E */         /* F */
 155 #define IP0_3_0         FM(DU_DR2)                      FM(HSCK0)               F_(0, 0)        FM(A0)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 156 #define IP0_7_4         FM(DU_DR3)                      FM(HRTS0_N)             F_(0, 0)        FM(A1)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 157 #define IP0_11_8        FM(DU_DR4)                      FM(HCTS0_N)             F_(0, 0)        FM(A2)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 158 #define IP0_15_12       FM(DU_DR5)                      FM(HTX0)                F_(0, 0)        FM(A3)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 159 #define IP0_19_16       FM(DU_DR6)                      FM(MSIOF3_RXD)          F_(0, 0)        FM(A4)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 160 #define IP0_23_20       FM(DU_DR7)                      FM(MSIOF3_TXD)          F_(0, 0)        FM(A5)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 161 #define IP0_27_24       FM(DU_DG2)                      FM(MSIOF3_SS1)          F_(0, 0)        FM(A6)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 162 #define IP0_31_28       FM(DU_DG3)                      FM(MSIOF3_SS2)          F_(0, 0)        FM(A7)          FM(PWMFSW0)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 163 #define IP1_3_0         FM(DU_DG4)                      F_(0, 0)                F_(0, 0)        FM(A8)          FM(FSO_CFE_0_N_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 164 #define IP1_7_4         FM(DU_DG5)                      F_(0, 0)                F_(0, 0)        FM(A9)          FM(FSO_CFE_1_N_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 165 #define IP1_11_8        FM(DU_DG6)                      F_(0, 0)                F_(0, 0)        FM(A10)         FM(FSO_TOE_N_A)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 166 #define IP1_15_12       FM(DU_DG7)                      F_(0, 0)                F_(0, 0)        FM(A11)         FM(IRQ1)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 167 #define IP1_19_16       FM(DU_DB2)                      F_(0, 0)                F_(0, 0)        FM(A12)         FM(IRQ2)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 168 #define IP1_23_20       FM(DU_DB3)                      F_(0, 0)                F_(0, 0)        FM(A13)         FM(FXR_CLKOUT1)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 169 #define IP1_27_24       FM(DU_DB4)                      F_(0, 0)                F_(0, 0)        FM(A14)         FM(FXR_CLKOUT2)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 170 #define IP1_31_28       FM(DU_DB5)                      F_(0, 0)                F_(0, 0)        FM(A15)         FM(FXR_TXENA_N)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 171 #define IP2_3_0         FM(DU_DB6)                      F_(0, 0)                F_(0, 0)        FM(A16)         FM(FXR_TXENB_N)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 172 #define IP2_7_4         FM(DU_DB7)                      F_(0, 0)                F_(0, 0)        FM(A17)         FM(STPWT_EXTFXR)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 173 #define IP2_11_8        FM(DU_DOTCLKOUT)                FM(SCIF_CLK_A)          F_(0, 0)        FM(A18)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 174 #define IP2_15_12       FM(DU_EXHSYNC_DU_HSYNC)         FM(HRX0)                F_(0, 0)        FM(A19)         FM(IRQ3)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 175 #define IP2_19_16       FM(DU_EXVSYNC_DU_VSYNC)         FM(MSIOF3_SCK)          F_(0, 0)        FM(A20)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 176 #define IP2_23_20       FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(MSIOF3_SYNC)         F_(0, 0)        FM(A21)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 177 #define IP2_27_24       FM(IRQ0)                        FM(CC5_OSCOUT)          F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 178 #define IP2_31_28       FM(VI0_CLK)                     FM(MSIOF2_SCK)          FM(SCK3)        F_(0, 0)        FM(HSCK3)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 179 #define IP3_3_0         FM(VI0_CLKENB)                  FM(MSIOF2_RXD)          FM(RX3)         FM(RD_WR_N)     FM(HCTS3_N)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 180 #define IP3_7_4         FM(VI0_HSYNC_N)                 FM(MSIOF2_TXD)          FM(TX3)         F_(0, 0)        FM(HRTS3_N)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 181 #define IP3_11_8        FM(VI0_VSYNC_N)                 FM(MSIOF2_SYNC)         FM(CTS3_N)      F_(0, 0)        FM(HTX3)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 182 #define IP3_15_12       FM(VI0_DATA0)                   FM(MSIOF2_SS1)          FM(RTS3_N_TANS) F_(0, 0)        FM(HRX3)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 183 #define IP3_19_16       FM(VI0_DATA1)                   FM(MSIOF2_SS2)          FM(SCK1)        F_(0, 0)        FM(SPEEDIN_A)           F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 184 #define IP3_23_20       FM(VI0_DATA2)                   FM(AVB0_AVTP_PPS)       FM(SDA3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 185 #define IP3_27_24       FM(VI0_DATA3)                   FM(HSCK1)               FM(SCL3_A)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 186 #define IP3_31_28       FM(VI0_DATA4)                   FM(HRTS1_N)             FM(RX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 187 #define IP4_3_0         FM(VI0_DATA5)                   FM(HCTS1_N)             FM(TX1_A)       F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 188 #define IP4_7_4         FM(VI0_DATA6)                   FM(HTX1)                FM(CTS1_N)      F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 189 #define IP4_11_8        FM(VI0_DATA7)                   FM(HRX1)                FM(RTS1_N_TANS) F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 190 #define IP4_15_12       FM(VI0_DATA8)                   FM(HSCK2)               FM(PWM0_A)      FM(A22)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 191 #define IP4_19_16       FM(VI0_DATA9)                   FM(HCTS2_N)             FM(PWM1_A)      FM(A23)         FM(FSO_CFE_0_N_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 192 #define IP4_23_20       FM(VI0_DATA10)                  FM(HRTS2_N)             FM(PWM2_A)      FM(A24)         FM(FSO_CFE_1_N_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 193 #define IP4_27_24       FM(VI0_DATA11)                  FM(HTX2)                FM(PWM3_A)      FM(A25)         FM(FSO_TOE_N_B)         F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 194 #define IP4_31_28       FM(VI0_FIELD)                   FM(HRX2)                FM(PWM4_A)      FM(CS1_N_A26)   FM(FSCLKST2_N_A)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 195 #define IP5_3_0         FM(VI1_CLK)                     FM(MSIOF1_RXD)          F_(0, 0)        FM(CS0_N)       F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 196 #define IP5_7_4         FM(VI1_CLKENB)                  FM(MSIOF1_TXD)          F_(0, 0)        FM(D0)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 197 #define IP5_11_8        FM(VI1_HSYNC_N)                 FM(MSIOF1_SCK)          F_(0, 0)        FM(D1)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 198 #define IP5_15_12       FM(VI1_VSYNC_N)                 FM(MSIOF1_SYNC)         F_(0, 0)        FM(D2)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 199 #define IP5_19_16       FM(VI1_DATA0)                   FM(MSIOF1_SS1)          F_(0, 0)        FM(D3)          F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 200 #define IP5_23_20       FM(VI1_DATA1)                   FM(MSIOF1_SS2)          F_(0, 0)        FM(D4)          FM(MMC_CMD)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 201 #define IP5_27_24       FM(VI1_DATA2)                   FM(CANFD0_TX_B)         F_(0, 0)        FM(D5)          FM(MMC_D0)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 202 #define IP5_31_28       FM(VI1_DATA3)                   FM(CANFD0_RX_B)         F_(0, 0)        FM(D6)          FM(MMC_D1)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 203 #define IP6_3_0         FM(VI1_DATA4)                   FM(CANFD_CLK_B)         F_(0, 0)        FM(D7)          FM(MMC_D2)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 204 #define IP6_7_4         FM(VI1_DATA5)                   F_(0,0)                 FM(SCK4)        FM(D8)          FM(MMC_D3)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 205 #define IP6_11_8        FM(VI1_DATA6)                   F_(0,0)                 FM(RX4)         FM(D9)          FM(MMC_CLK)             F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 206 #define IP6_15_12       FM(VI1_DATA7)                   F_(0,0)                 FM(TX4)         FM(D10)         FM(MMC_D4)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 207 #define IP6_19_16       FM(VI1_DATA8)                   F_(0,0)                 FM(CTS4_N)      FM(D11)         FM(MMC_D5)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 208 #define IP6_23_20       FM(VI1_DATA9)                   F_(0,0)                 FM(RTS4_N_TANS) FM(D12)         FM(MMC_D6)              FM(SCL3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 209 #define IP6_27_24       FM(VI1_DATA10)                  F_(0,0)                 F_(0, 0)        FM(D13)         FM(MMC_D7)              FM(SDA3_B)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 210 #define IP6_31_28       FM(VI1_DATA11)                  FM(SCL4)                FM(IRQ4)        FM(D14)         FM(MMC_WP)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 211 #define IP7_3_0         FM(VI1_FIELD)                   FM(SDA4)                FM(IRQ5)        FM(D15)         FM(MMC_CD)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 212 #define IP7_7_4         FM(SCL0)                        FM(DU_DR0)              FM(TPU0TO0)     FM(CLKOUT)      F_(0, 0)                FM(MSIOF0_RXD)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 213 #define IP7_11_8        FM(SDA0)                        FM(DU_DR1)              FM(TPU0TO1)     FM(BS_N)        FM(SCK0)                FM(MSIOF0_TXD)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 214 #define IP7_15_12       FM(SCL1)                        FM(DU_DG0)              FM(TPU0TO2)     FM(RD_N)        FM(CTS0_N)              FM(MSIOF0_SCK)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 215 #define IP7_19_16       FM(SDA1)                        FM(DU_DG1)              FM(TPU0TO3)     FM(WE0_N)       FM(RTS0_N_TANS)         FM(MSIOF0_SYNC) F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 216 #define IP7_23_20       FM(SCL2)                        FM(DU_DB0)              FM(TCLK1_A)     FM(WE1_N)       FM(RX0)                 FM(MSIOF0_SS1)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 217 #define IP7_27_24       FM(SDA2)                        FM(DU_DB1)              FM(TCLK2_A)     FM(EX_WAIT0)    FM(TX0)                 FM(MSIOF0_SS2)  F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 218 #define IP7_31_28       FM(AVB0_AVTP_CAPTURE)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(FSCLKST2_N_B)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 219 #define IP8_3_0         FM(CANFD0_TX_A)                 FM(FXR_TXDA)            FM(PWM0_B)      FM(DU_DISP)     FM(FSCLKST2_N_C)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 220 #define IP8_7_4         FM(CANFD0_RX_A)                 FM(RXDA_EXTFXR)         FM(PWM1_B)      FM(DU_CDE)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 221 #define IP8_11_8        FM(CANFD1_TX)                   FM(FXR_TXDB)            FM(PWM2_B)      FM(TCLK1_B)     FM(TX1_B)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 222 #define IP8_15_12       FM(CANFD1_RX)                   FM(RXDB_EXTFXR)         FM(PWM3_B)      FM(TCLK2_B)     FM(RX1_B)               F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 223 #define IP8_19_16       FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)      FM(SPEEDIN_B)   FM(SCIF_CLK_B)          F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 224 #define IP8_23_20       FM(DIGRF_CLKIN)                 FM(DIGRF_CLKEN_IN)      F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 225 #define IP8_27_24       FM(DIGRF_CLKOUT)                FM(DIGRF_CLKEN_OUT)     F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 226 #define IP8_31_28       F_(0, 0)                        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
 227
 228 #define PINMUX_GPSR     \
 229 \
 230                 GPSR1_27 \
 231                 GPSR1_26 \
 232                 GPSR1_25 \
 233                 GPSR1_24 \
 234                 GPSR1_23 \
 235                 GPSR1_22 \
 236 GPSR0_21        GPSR1_21 \
 237 GPSR0_20        GPSR1_20 \
 238 GPSR0_19        GPSR1_19 \
 239 GPSR0_18        GPSR1_18 \
 240 GPSR0_17        GPSR1_17 \
 241 GPSR0_16        GPSR1_16        GPSR2_16        GPSR3_16 \
 242 GPSR0_15        GPSR1_15        GPSR2_15        GPSR3_15 \
 243 GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14                        GPSR5_14 \
 244 GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13                        GPSR5_13 \
 245 GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12                        GPSR5_12 \
 246 GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11                        GPSR5_11 \
 247 GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10                        GPSR5_10 \
 248 GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9                         GPSR5_9 \
 249 GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8                         GPSR5_8 \
 250 GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7                         GPSR5_7 \
 251 GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6                         GPSR5_6 \
 252 GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5 \
 253 GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4 \
 254 GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3 \
 255 GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2 \
 256 GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1 \
 257 GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0
 258
 259 #define PINMUX_IPSR     \
 260 \
 261 FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
 262 FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
 263 FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
 264 FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
 265 FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
 266 FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
 267 FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
 268 FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
 269 \
 270 FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
 271 FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
 272 FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
 273 FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
 274 FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
 275 FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
 276 FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
 277 FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
 278 \
 279 FM(IP8_3_0)     IP8_3_0 \
 280 FM(IP8_7_4)     IP8_7_4 \
 281 FM(IP8_11_8)    IP8_11_8 \
 282 FM(IP8_15_12)   IP8_15_12 \
 283 FM(IP8_19_16)   IP8_19_16 \
 284 FM(IP8_23_20)   IP8_23_20 \
 285 FM(IP8_27_24)   IP8_27_24 \
 286 FM(IP8_31_28)   IP8_31_28
 287
 288 /*
 289                         Set Value = H'0                 Set Value = H'1
 290 Register        Function        Pin                     Function        Pin
 291 ------------------------------------------------------------
 292 sel_i2c3        SDA3_A          VI0_DATA2       SDA3_B          VI1_DATA10
 293                 SCL3_A          VI0_DATA3       SCL3_B          VI1_DATA9
 294 sel_hscif0      HSCIF0_A        SCIF_CLK        HSCIF0_B        SCIF_CLK
 295 sel_scif1       SCIF1_A         RX1             SCIF1_B         TX1
 296                 SCIF1_A         TX1             SCIF1_B         RX1
 297 sel_canfd0      CANFD0_A        CANFD0_TX       CANFD0_B        CANFD0_TX
 298                 CANFD0_A        CANFD0_RX       CANFD0_B        CANFD0_RX
 299                 CANFD0_A        CANFD_CLK       CANFD0_B        CANFD_CLK
 300 sel_pwm4        PWM4_A          PWM4            PWM4_B          PWM4
 301 sel_pwm3        PWM3_A          PWM3            PWM3_B          PWM3
 302 sel_pwm2        PWM2_A          PWM2            PWM2_B          PWM2
 303 sel_pwm1        PWM1_A          PWM1            PWM1_B          PWM1
 304 sel_pwm0        PWM0_A          PWM0            PWM0_B          PWM0
 305 sel_rfso        RFSO_A          FSO_CFE_0_N     RFSO_B          FSO_CFE_0_N
 306                 RFSO_A          FSO_CFE_1_N     RFSO_B          FSO_CFE_1_N
 307                 RFSO_A          FSO_TOE_N       RFSO_B          FSO_TOE_N
 308 sel_rsp         RSP_A           SPEEDIN         RSP_B           SPEEDIN
 309 sel_tmu         TMU_A           TCLK1           TMU_B           TCLK1
 310                 TMU_A           TCLK2           TMU_B           TCLK2
 311 */
 312 /* MOD_SEL0 */          /* 0 */                 /* 1 */                 /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
 313 #define MOD_SEL0_11     FM(SEL_I2C3_0)          FM(SEL_I2C3_1)
 314 #define MOD_SEL0_10     FM(SEL_HSCIF0_0)        FM(SEL_HSCIF0_1)
 315 #define MOD_SEL0_9      FM(SEL_SCIF1_0)         FM(SEL_SCIF1_1)
 316 #define MOD_SEL0_8      FM(SEL_CANFD0_0)        FM(SEL_CANFD0_1)
 317 #define MOD_SEL0_7      FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
 318 #define MOD_SEL0_6      FM(SEL_PWM3_0)          FM(SEL_PWM3_1)
 319 #define MOD_SEL0_5      FM(SEL_PWM2_0)          FM(SEL_PWM2_1)
 320 #define MOD_SEL0_4      FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
 321 #define MOD_SEL0_3      FM(SEL_PWM0_0)          FM(SEL_PWM0_1)
 322 #define MOD_SEL0_2      FM(SEL_RFSO_0)          FM(SEL_RFSO_1)
 323 #define MOD_SEL0_1      FM(SEL_RSP_0)           FM(SEL_RSP_1)
 324 #define MOD_SEL0_0      FM(SEL_TMU_0)           FM(SEL_TMU_1)
 325
 326 #define PINMUX_MOD_SELS \
 327 \
 328 MOD_SEL0_11 \
 329 MOD_SEL0_10 \
 330 MOD_SEL0_9 \
 331 MOD_SEL0_8 \
 332 MOD_SEL0_7 \
 333 MOD_SEL0_6 \
 334 MOD_SEL0_5 \
 335 MOD_SEL0_4 \
 336 MOD_SEL0_3 \
 337 MOD_SEL0_2 \
 338 MOD_SEL0_1 \
 339 MOD_SEL0_0
 340
 341 enum {
 342         PINMUX_RESERVED = 0,
 343
 344         PINMUX_DATA_BEGIN,
 345         GP_ALL(DATA),
 346         PINMUX_DATA_END,
 347
 348 #define F_(x, y)
 349 #define FM(x)   FN_##x,
 350         PINMUX_FUNCTION_BEGIN,
 351         GP_ALL(FN),
 352         PINMUX_GPSR
 353         PINMUX_IPSR
 354         PINMUX_MOD_SELS
 355         PINMUX_FUNCTION_END,
 356 #undef F_
 357 #undef FM
 358
 359 #define F_(x, y)
 360 #define FM(x)   x##_MARK,
 361         PINMUX_MARK_BEGIN,
 362         PINMUX_GPSR
 363         PINMUX_IPSR
 364         PINMUX_MOD_SELS
 365         PINMUX_MARK_END,
 366 #undef F_
 367 #undef FM
 368 };
 369
 370 static const u16 pinmux_data[] = {
 371         PINMUX_DATA_GP_ALL(),
 372
 373         PINMUX_SINGLE(AVB0_RX_CTL),
 374         PINMUX_SINGLE(AVB0_RXC),
 375         PINMUX_SINGLE(AVB0_RD0),
 376         PINMUX_SINGLE(AVB0_RD1),
 377         PINMUX_SINGLE(AVB0_RD2),
 378         PINMUX_SINGLE(AVB0_RD3),
 379         PINMUX_SINGLE(AVB0_TX_CTL),
 380         PINMUX_SINGLE(AVB0_TXC),
 381         PINMUX_SINGLE(AVB0_TD0),
 382         PINMUX_SINGLE(AVB0_TD1),
 383         PINMUX_SINGLE(AVB0_TD2),
 384         PINMUX_SINGLE(AVB0_TD3),
 385         PINMUX_SINGLE(AVB0_TXCREFCLK),
 386         PINMUX_SINGLE(AVB0_MDIO),
 387         PINMUX_SINGLE(AVB0_MDC),
 388         PINMUX_SINGLE(AVB0_MAGIC),
 389         PINMUX_SINGLE(AVB0_PHY_INT),
 390         PINMUX_SINGLE(AVB0_LINK),
 391         PINMUX_SINGLE(AVB0_AVTP_MATCH),
 392
 393         PINMUX_SINGLE(QSPI0_SPCLK),
 394         PINMUX_SINGLE(QSPI0_MOSI_IO0),
 395         PINMUX_SINGLE(QSPI0_MISO_IO1),
 396         PINMUX_SINGLE(QSPI0_IO2),
 397         PINMUX_SINGLE(QSPI0_IO3),
 398         PINMUX_SINGLE(QSPI0_SSL),
 399         PINMUX_SINGLE(QSPI1_SPCLK),
 400         PINMUX_SINGLE(QSPI1_MOSI_IO0),
 401         PINMUX_SINGLE(QSPI1_MISO_IO1),
 402         PINMUX_SINGLE(QSPI1_IO2),
 403         PINMUX_SINGLE(QSPI1_IO3),
 404         PINMUX_SINGLE(QSPI1_SSL),
 405         PINMUX_SINGLE(RPC_RESET_N),
 406         PINMUX_SINGLE(RPC_WP_N),
 407         PINMUX_SINGLE(RPC_INT_N),
 408
 409         /* IPSR0 */
 410         PINMUX_IPSR_GPSR(IP0_3_0,       DU_DR2),
 411         PINMUX_IPSR_GPSR(IP0_3_0,       HSCK0),
 412         PINMUX_IPSR_GPSR(IP0_3_0,       A0),
 413
 414         PINMUX_IPSR_GPSR(IP0_7_4,       DU_DR3),
 415         PINMUX_IPSR_GPSR(IP0_7_4,       HRTS0_N),
 416         PINMUX_IPSR_GPSR(IP0_7_4,       A1),
 417
 418         PINMUX_IPSR_GPSR(IP0_11_8,      DU_DR4),
 419         PINMUX_IPSR_GPSR(IP0_11_8,      HCTS0_N),
 420         PINMUX_IPSR_GPSR(IP0_11_8,      A2),
 421
 422         PINMUX_IPSR_GPSR(IP0_15_12,     DU_DR5),
 423         PINMUX_IPSR_GPSR(IP0_15_12,     HTX0),
 424         PINMUX_IPSR_GPSR(IP0_15_12,     A3),
 425
 426         PINMUX_IPSR_GPSR(IP0_19_16,     DU_DR6),
 427         PINMUX_IPSR_GPSR(IP0_19_16,     MSIOF3_RXD),
 428         PINMUX_IPSR_GPSR(IP0_19_16,     A4),
 429
 430         PINMUX_IPSR_GPSR(IP0_23_20,     DU_DR7),
 431         PINMUX_IPSR_GPSR(IP0_23_20,     MSIOF3_TXD),
 432         PINMUX_IPSR_GPSR(IP0_23_20,     A5),
 433
 434         PINMUX_IPSR_GPSR(IP0_27_24,     DU_DG2),
 435         PINMUX_IPSR_GPSR(IP0_27_24,     MSIOF3_SS1),
 436         PINMUX_IPSR_GPSR(IP0_27_24,     A6),
 437
 438         PINMUX_IPSR_GPSR(IP0_31_28,     DU_DG3),
 439         PINMUX_IPSR_GPSR(IP0_31_28,     MSIOF3_SS2),
 440         PINMUX_IPSR_GPSR(IP0_31_28,     A7),
 441         PINMUX_IPSR_GPSR(IP0_31_28,     PWMFSW0),
 442
 443         /* IPSR1 */
 444         PINMUX_IPSR_GPSR(IP1_3_0,       DU_DG4),
 445         PINMUX_IPSR_GPSR(IP1_3_0,       A8),
 446         PINMUX_IPSR_MSEL(IP1_3_0,       FSO_CFE_0_N_A,  SEL_RFSO_0),
 447
 448         PINMUX_IPSR_GPSR(IP1_7_4,       DU_DG5),
 449         PINMUX_IPSR_GPSR(IP1_7_4,       A9),
 450         PINMUX_IPSR_MSEL(IP1_7_4,       FSO_CFE_1_N_A,  SEL_RFSO_0),
 451
 452         PINMUX_IPSR_GPSR(IP1_11_8,      DU_DG6),
 453         PINMUX_IPSR_GPSR(IP1_11_8,      A10),
 454         PINMUX_IPSR_MSEL(IP1_11_8,      FSO_TOE_N_A,    SEL_RFSO_0),
 455
 456         PINMUX_IPSR_GPSR(IP1_15_12,     DU_DG7),
 457         PINMUX_IPSR_GPSR(IP1_15_12,     A11),
 458         PINMUX_IPSR_GPSR(IP1_15_12,     IRQ1),
 459
 460         PINMUX_IPSR_GPSR(IP1_19_16,     DU_DB2),
 461         PINMUX_IPSR_GPSR(IP1_19_16,     A12),
 462         PINMUX_IPSR_GPSR(IP1_19_16,     IRQ2),
 463
 464         PINMUX_IPSR_GPSR(IP1_23_20,     DU_DB3),
 465         PINMUX_IPSR_GPSR(IP1_23_20,     A13),
 466         PINMUX_IPSR_GPSR(IP1_23_20,     FXR_CLKOUT1),
 467
 468         PINMUX_IPSR_GPSR(IP1_27_24,     DU_DB4),
 469         PINMUX_IPSR_GPSR(IP1_27_24,     A14),
 470         PINMUX_IPSR_GPSR(IP1_27_24,     FXR_CLKOUT2),
 471
 472         PINMUX_IPSR_GPSR(IP1_31_28,     DU_DB5),
 473         PINMUX_IPSR_GPSR(IP1_31_28,     A15),
 474         PINMUX_IPSR_GPSR(IP1_31_28,     FXR_TXENA_N),
 475
 476         /* IPSR2 */
 477         PINMUX_IPSR_GPSR(IP2_3_0,       DU_DB6),
 478         PINMUX_IPSR_GPSR(IP2_3_0,       A16),
 479         PINMUX_IPSR_GPSR(IP2_3_0,       FXR_TXENB_N),
 480
 481         PINMUX_IPSR_GPSR(IP2_7_4,       DU_DB7),
 482         PINMUX_IPSR_GPSR(IP2_7_4,       A17),
 483         PINMUX_IPSR_GPSR(IP2_7_4,       STPWT_EXTFXR),
 484
 485         PINMUX_IPSR_GPSR(IP2_11_8,      DU_DOTCLKOUT),
 486         PINMUX_IPSR_MSEL(IP2_11_8,      SCIF_CLK_A,     SEL_HSCIF0_0),
 487         PINMUX_IPSR_GPSR(IP2_11_8,      A18),
 488
 489         PINMUX_IPSR_GPSR(IP2_15_12,     DU_EXHSYNC_DU_HSYNC),
 490         PINMUX_IPSR_GPSR(IP2_15_12,     HRX0),
 491         PINMUX_IPSR_GPSR(IP2_15_12,     A19),
 492         PINMUX_IPSR_GPSR(IP2_15_12,     IRQ3),
 493
 494         PINMUX_IPSR_GPSR(IP2_19_16,     DU_EXVSYNC_DU_VSYNC),
 495         PINMUX_IPSR_GPSR(IP2_19_16,     MSIOF3_SCK),
 496         PINMUX_IPSR_GPSR(IP2_19_16,     A20),
 497
 498         PINMUX_IPSR_GPSR(IP2_23_20,     DU_EXODDF_DU_ODDF_DISP_CDE),
 499         PINMUX_IPSR_GPSR(IP2_23_20,     MSIOF3_SYNC),
 500         PINMUX_IPSR_GPSR(IP2_23_20,     A21),
 501
 502         PINMUX_IPSR_GPSR(IP2_27_24,     IRQ0),
 503         PINMUX_IPSR_GPSR(IP2_27_24,     CC5_OSCOUT),
 504
 505         PINMUX_IPSR_GPSR(IP2_31_28,     VI0_CLK),
 506         PINMUX_IPSR_GPSR(IP2_31_28,     MSIOF2_SCK),
 507         PINMUX_IPSR_GPSR(IP2_31_28,     SCK3),
 508         PINMUX_IPSR_GPSR(IP2_31_28,     HSCK3),
 509
 510         /* IPSR3 */
 511         PINMUX_IPSR_GPSR(IP3_3_0,       VI0_CLKENB),
 512         PINMUX_IPSR_GPSR(IP3_3_0,       MSIOF2_RXD),
 513         PINMUX_IPSR_GPSR(IP3_3_0,       RX3),
 514         PINMUX_IPSR_GPSR(IP3_3_0,       RD_WR_N),
 515         PINMUX_IPSR_GPSR(IP3_3_0,       HCTS3_N),
 516
 517         PINMUX_IPSR_GPSR(IP3_7_4,       VI0_HSYNC_N),
 518         PINMUX_IPSR_GPSR(IP3_7_4,       MSIOF2_TXD),
 519         PINMUX_IPSR_GPSR(IP3_7_4,       TX3),
 520         PINMUX_IPSR_GPSR(IP3_7_4,       HRTS3_N),
 521
 522         PINMUX_IPSR_GPSR(IP3_11_8,      VI0_VSYNC_N),
 523         PINMUX_IPSR_GPSR(IP3_11_8,      MSIOF2_SYNC),
 524         PINMUX_IPSR_GPSR(IP3_11_8,      CTS3_N),
 525         PINMUX_IPSR_GPSR(IP3_11_8,      HTX3),
 526
 527         PINMUX_IPSR_GPSR(IP3_15_12,     VI0_DATA0),
 528         PINMUX_IPSR_GPSR(IP3_15_12,     MSIOF2_SS1),
 529         PINMUX_IPSR_GPSR(IP3_15_12,     RTS3_N_TANS),
 530         PINMUX_IPSR_GPSR(IP3_15_12,     HRX3),
 531
 532         PINMUX_IPSR_GPSR(IP3_19_16,     VI0_DATA1),
 533         PINMUX_IPSR_GPSR(IP3_19_16,     MSIOF2_SS2),
 534         PINMUX_IPSR_GPSR(IP3_19_16,     SCK1),
 535         PINMUX_IPSR_MSEL(IP3_19_16,     SPEEDIN_A,      SEL_RSP_1),
 536
 537         PINMUX_IPSR_GPSR(IP3_23_20,     VI0_DATA2),
 538         PINMUX_IPSR_GPSR(IP3_23_20,     AVB0_AVTP_PPS),
 539         PINMUX_IPSR_GPSR(IP3_23_20,     SDA3_A),
 540
 541         PINMUX_IPSR_GPSR(IP3_27_24,     VI0_DATA3),
 542         PINMUX_IPSR_GPSR(IP3_27_24,     HSCK1),
 543         PINMUX_IPSR_GPSR(IP3_27_24,     SCL3_A),
 544
 545         PINMUX_IPSR_GPSR(IP3_31_28,     VI0_DATA4),
 546         PINMUX_IPSR_GPSR(IP3_31_28,     HRTS1_N),
 547         PINMUX_IPSR_MSEL(IP3_31_28,     RX1_A,  SEL_SCIF1_0),
 548
 549         /* IPSR4 */
 550         PINMUX_IPSR_GPSR(IP4_3_0,       VI0_DATA5),
 551         PINMUX_IPSR_GPSR(IP4_3_0,       HCTS1_N),
 552         PINMUX_IPSR_MSEL(IP4_3_0,       TX1_A,  SEL_SCIF1_0),
 553
 554         PINMUX_IPSR_GPSR(IP4_7_4,       VI0_DATA6),
 555         PINMUX_IPSR_GPSR(IP4_7_4,       HTX1),
 556         PINMUX_IPSR_GPSR(IP4_7_4,       CTS1_N),
 557
 558         PINMUX_IPSR_GPSR(IP4_11_8,      VI0_DATA7),
 559         PINMUX_IPSR_GPSR(IP4_11_8,      HRX1),
 560         PINMUX_IPSR_GPSR(IP4_11_8,      RTS1_N_TANS),
 561
 562         PINMUX_IPSR_GPSR(IP4_15_12,     VI0_DATA8),
 563         PINMUX_IPSR_GPSR(IP4_15_12,     HSCK2),
 564         PINMUX_IPSR_MSEL(IP4_15_12,     PWM0_A, SEL_PWM0_0),
 565         PINMUX_IPSR_GPSR(IP4_15_12,     A22),
 566
 567         PINMUX_IPSR_GPSR(IP4_19_16,     VI0_DATA9),
 568         PINMUX_IPSR_GPSR(IP4_19_16,     HCTS2_N),
 569         PINMUX_IPSR_MSEL(IP4_19_16,     PWM1_A, SEL_PWM1_0),
 570         PINMUX_IPSR_GPSR(IP4_19_16,     A23),
 571         PINMUX_IPSR_MSEL(IP4_19_16,     FSO_CFE_0_N_B,  SEL_RFSO_1),
 572
 573         PINMUX_IPSR_GPSR(IP4_23_20,     VI0_DATA10),
 574         PINMUX_IPSR_GPSR(IP4_23_20,     HRTS2_N),
 575         PINMUX_IPSR_MSEL(IP4_23_20,     PWM2_A, SEL_PWM2_0),
 576         PINMUX_IPSR_GPSR(IP4_23_20,     A24),
 577         PINMUX_IPSR_MSEL(IP4_23_20,     FSO_CFE_1_N_B,  SEL_RFSO_1),
 578
 579         PINMUX_IPSR_GPSR(IP4_27_24,     VI0_DATA11),
 580         PINMUX_IPSR_GPSR(IP4_27_24,     HTX2),
 581         PINMUX_IPSR_MSEL(IP4_27_24,     PWM3_A, SEL_PWM3_0),
 582         PINMUX_IPSR_GPSR(IP4_27_24,     A25),
 583         PINMUX_IPSR_MSEL(IP4_27_24,     FSO_TOE_N_B,    SEL_RFSO_1),
 584
 585         PINMUX_IPSR_GPSR(IP4_31_28,     VI0_FIELD),
 586         PINMUX_IPSR_GPSR(IP4_31_28,     HRX2),
 587         PINMUX_IPSR_MSEL(IP4_31_28,     PWM4_A, SEL_PWM4_0),
 588         PINMUX_IPSR_GPSR(IP4_31_28,     CS1_N_A26),
 589         PINMUX_IPSR_GPSR(IP4_31_28,     FSCLKST2_N_A),
 590
 591         /* IPSR5 */
 592         PINMUX_IPSR_GPSR(IP5_3_0,       VI1_CLK),
 593         PINMUX_IPSR_GPSR(IP5_3_0,       MSIOF1_RXD),
 594         PINMUX_IPSR_GPSR(IP5_3_0,       CS0_N),
 595
 596         PINMUX_IPSR_GPSR(IP5_7_4,       VI1_CLKENB),
 597         PINMUX_IPSR_GPSR(IP5_7_4,       MSIOF1_TXD),
 598         PINMUX_IPSR_GPSR(IP5_7_4,       D0),
 599
 600         PINMUX_IPSR_GPSR(IP5_11_8,      VI1_HSYNC_N),
 601         PINMUX_IPSR_GPSR(IP5_11_8,      MSIOF1_SCK),
 602         PINMUX_IPSR_GPSR(IP5_11_8,      D1),
 603
 604         PINMUX_IPSR_GPSR(IP5_15_12,     VI1_VSYNC_N),
 605         PINMUX_IPSR_GPSR(IP5_15_12,     MSIOF1_SYNC),
 606         PINMUX_IPSR_GPSR(IP5_15_12,     D2),
 607
 608         PINMUX_IPSR_GPSR(IP5_19_16,     VI1_DATA0),
 609         PINMUX_IPSR_GPSR(IP5_19_16,     MSIOF1_SS1),
 610         PINMUX_IPSR_GPSR(IP5_19_16,     D3),
 611
 612         PINMUX_IPSR_GPSR(IP5_23_20,     VI1_DATA1),
 613         PINMUX_IPSR_GPSR(IP5_23_20,     MSIOF1_SS2),
 614         PINMUX_IPSR_GPSR(IP5_23_20,     D4),
 615         PINMUX_IPSR_GPSR(IP5_23_20,     MMC_CMD),
 616
 617         PINMUX_IPSR_GPSR(IP5_27_24,     VI1_DATA2),
 618         PINMUX_IPSR_MSEL(IP5_27_24,     CANFD0_TX_B,    SEL_CANFD0_1),
 619         PINMUX_IPSR_GPSR(IP5_27_24,     D5),
 620         PINMUX_IPSR_GPSR(IP5_27_24,     MMC_D0),
 621
 622         PINMUX_IPSR_GPSR(IP5_31_28,     VI1_DATA3),
 623         PINMUX_IPSR_MSEL(IP5_31_28,     CANFD0_RX_B,    SEL_CANFD0_1),
 624         PINMUX_IPSR_GPSR(IP5_31_28,     D6),
 625         PINMUX_IPSR_GPSR(IP5_31_28,     MMC_D1),
 626
 627         /* IPSR6 */
 628         PINMUX_IPSR_GPSR(IP6_3_0,       VI1_DATA4),
 629         PINMUX_IPSR_MSEL(IP6_3_0,       CANFD_CLK_B,    SEL_CANFD0_1),
 630         PINMUX_IPSR_GPSR(IP6_3_0,       D7),
 631         PINMUX_IPSR_GPSR(IP6_3_0,       MMC_D2),
 632
 633         PINMUX_IPSR_GPSR(IP6_7_4,       VI1_DATA5),
 634         PINMUX_IPSR_GPSR(IP6_7_4,       SCK4),
 635         PINMUX_IPSR_GPSR(IP6_7_4,       D8),
 636         PINMUX_IPSR_GPSR(IP6_7_4,       MMC_D3),
 637
 638         PINMUX_IPSR_GPSR(IP6_11_8,      VI1_DATA6),
 639         PINMUX_IPSR_GPSR(IP6_11_8,      RX4),
 640         PINMUX_IPSR_GPSR(IP6_11_8,      D9),
 641         PINMUX_IPSR_GPSR(IP6_11_8,      MMC_CLK),
 642
 643         PINMUX_IPSR_GPSR(IP6_15_12,     VI1_DATA7),
 644         PINMUX_IPSR_GPSR(IP6_15_12,     TX4),
 645         PINMUX_IPSR_GPSR(IP6_15_12,     D10),
 646         PINMUX_IPSR_GPSR(IP6_15_12,     MMC_D4),
 647
 648         PINMUX_IPSR_GPSR(IP6_19_16,     VI1_DATA8),
 649         PINMUX_IPSR_GPSR(IP6_19_16,     CTS4_N),
 650         PINMUX_IPSR_GPSR(IP6_19_16,     D11),
 651         PINMUX_IPSR_GPSR(IP6_19_16,     MMC_D5),
 652
 653         PINMUX_IPSR_GPSR(IP6_23_20,     VI1_DATA9),
 654         PINMUX_IPSR_GPSR(IP6_23_20,     RTS4_N_TANS),
 655         PINMUX_IPSR_GPSR(IP6_23_20,     D12),
 656         PINMUX_IPSR_GPSR(IP6_23_20,     MMC_D6),
 657         PINMUX_IPSR_GPSR(IP6_23_20,     SCL3_B),
 658
 659         PINMUX_IPSR_GPSR(IP6_27_24,     VI1_DATA10),
 660         PINMUX_IPSR_GPSR(IP6_27_24,     D13),
 661         PINMUX_IPSR_GPSR(IP6_27_24,     MMC_D7),
 662         PINMUX_IPSR_GPSR(IP6_27_24,     SDA3_B),
 663
 664         PINMUX_IPSR_GPSR(IP6_31_28,     VI1_DATA11),
 665         PINMUX_IPSR_GPSR(IP6_31_28,     SCL4),
 666         PINMUX_IPSR_GPSR(IP6_31_28,     IRQ4),
 667         PINMUX_IPSR_GPSR(IP6_31_28,     D14),
 668         PINMUX_IPSR_GPSR(IP6_31_28,     MMC_WP),
 669
 670         /* IPSR7 */
 671         PINMUX_IPSR_GPSR(IP7_3_0,       VI1_FIELD),
 672         PINMUX_IPSR_GPSR(IP7_3_0,       SDA4),
 673         PINMUX_IPSR_GPSR(IP7_3_0,       IRQ5),
 674         PINMUX_IPSR_GPSR(IP7_3_0,       D15),
 675         PINMUX_IPSR_GPSR(IP7_3_0,       MMC_CD),
 676
 677         PINMUX_IPSR_GPSR(IP7_7_4,       SCL0),
 678         PINMUX_IPSR_GPSR(IP7_7_4,       DU_DR0),
 679         PINMUX_IPSR_GPSR(IP7_7_4,       TPU0TO0),
 680         PINMUX_IPSR_GPSR(IP7_7_4,       CLKOUT),
 681         PINMUX_IPSR_GPSR(IP7_7_4,       MSIOF0_RXD),
 682
 683         PINMUX_IPSR_GPSR(IP7_11_8,      SDA0),
 684         PINMUX_IPSR_GPSR(IP7_11_8,      DU_DR1),
 685         PINMUX_IPSR_GPSR(IP7_11_8,      TPU0TO1),
 686         PINMUX_IPSR_GPSR(IP7_11_8,      BS_N),
 687         PINMUX_IPSR_GPSR(IP7_11_8,      SCK0),
 688         PINMUX_IPSR_GPSR(IP7_11_8,      MSIOF0_TXD),
 689
 690         PINMUX_IPSR_GPSR(IP7_15_12,     SCL1),
 691         PINMUX_IPSR_GPSR(IP7_15_12,     DU_DG0),
 692         PINMUX_IPSR_GPSR(IP7_15_12,     TPU0TO2),
 693         PINMUX_IPSR_GPSR(IP7_15_12,     RD_N),
 694         PINMUX_IPSR_GPSR(IP7_15_12,     CTS0_N),
 695         PINMUX_IPSR_GPSR(IP7_15_12,     MSIOF0_SCK),
 696
 697         PINMUX_IPSR_GPSR(IP7_19_16,     SDA1),
 698         PINMUX_IPSR_GPSR(IP7_19_16,     DU_DG1),
 699         PINMUX_IPSR_GPSR(IP7_19_16,     TPU0TO3),
 700         PINMUX_IPSR_GPSR(IP7_19_16,     WE0_N),
 701         PINMUX_IPSR_GPSR(IP7_19_16,     RTS0_N_TANS),
 702         PINMUX_IPSR_GPSR(IP7_19_16,     MSIOF0_SYNC),
 703
 704         PINMUX_IPSR_GPSR(IP7_23_20,     SCL2),
 705         PINMUX_IPSR_GPSR(IP7_23_20,     DU_DB0),
 706         PINMUX_IPSR_MSEL(IP7_23_20,     TCLK1_A,        SEL_TMU_0),
 707         PINMUX_IPSR_GPSR(IP7_23_20,     WE1_N),
 708         PINMUX_IPSR_GPSR(IP7_23_20,     RX0),
 709         PINMUX_IPSR_GPSR(IP7_23_20,     MSIOF0_SS1),
 710
 711         PINMUX_IPSR_GPSR(IP7_27_24,     SDA2),
 712         PINMUX_IPSR_GPSR(IP7_27_24,     DU_DB1),
 713         PINMUX_IPSR_MSEL(IP7_27_24,     TCLK2_A,        SEL_TMU_0),
 714         PINMUX_IPSR_GPSR(IP7_27_24,     EX_WAIT0),
 715         PINMUX_IPSR_GPSR(IP7_27_24,     TX0),
 716         PINMUX_IPSR_GPSR(IP7_27_24,     MSIOF0_SS2),
 717
 718         PINMUX_IPSR_GPSR(IP7_31_28,     AVB0_AVTP_CAPTURE),
 719         PINMUX_IPSR_GPSR(IP7_31_28,     FSCLKST2_N_B),
 720
 721         /* IPSR8 */
 722         PINMUX_IPSR_MSEL(IP8_3_0,       CANFD0_TX_A,    SEL_CANFD0_0),
 723         PINMUX_IPSR_GPSR(IP8_3_0,       FXR_TXDA),
 724         PINMUX_IPSR_MSEL(IP8_3_0,       PWM0_B, SEL_PWM0_1),
 725         PINMUX_IPSR_GPSR(IP8_3_0,       DU_DISP),
 726         PINMUX_IPSR_GPSR(IP8_3_0,       FSCLKST2_N_C),
 727
 728         PINMUX_IPSR_MSEL(IP8_7_4,       CANFD0_RX_A,    SEL_CANFD0_0),
 729         PINMUX_IPSR_GPSR(IP8_7_4,       RXDA_EXTFXR),
 730         PINMUX_IPSR_MSEL(IP8_7_4,       PWM1_B, SEL_PWM1_1),
 731         PINMUX_IPSR_GPSR(IP8_7_4,       DU_CDE),
 732
 733         PINMUX_IPSR_GPSR(IP8_11_8,      CANFD1_TX),
 734         PINMUX_IPSR_GPSR(IP8_11_8,      FXR_TXDB),
 735         PINMUX_IPSR_MSEL(IP8_11_8,      PWM2_B, SEL_PWM2_1),
 736         PINMUX_IPSR_MSEL(IP8_11_8,      TCLK1_B,        SEL_TMU_1),
 737         PINMUX_IPSR_MSEL(IP8_11_8,      TX1_B,  SEL_SCIF1_1),
 738
 739         PINMUX_IPSR_GPSR(IP8_15_12,     CANFD1_RX),
 740         PINMUX_IPSR_GPSR(IP8_15_12,     RXDB_EXTFXR),
 741         PINMUX_IPSR_MSEL(IP8_15_12,     PWM3_B, SEL_PWM3_1),
 742         PINMUX_IPSR_MSEL(IP8_15_12,     TCLK2_B,        SEL_TMU_1),
 743         PINMUX_IPSR_MSEL(IP8_15_12,     RX1_B,  SEL_SCIF1_1),
 744
 745         PINMUX_IPSR_MSEL(IP8_19_16,     CANFD_CLK_A,    SEL_CANFD0_0),
 746         PINMUX_IPSR_GPSR(IP8_19_16,     CLK_EXTFXR),
 747         PINMUX_IPSR_MSEL(IP8_19_16,     PWM4_B, SEL_PWM4_1),
 748         PINMUX_IPSR_MSEL(IP8_19_16,     SPEEDIN_B,      SEL_RSP_0),
 749         PINMUX_IPSR_MSEL(IP8_19_16,     SCIF_CLK_B,     SEL_HSCIF0_1),
 750
 751         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKIN),
 752         PINMUX_IPSR_GPSR(IP8_23_20,     DIGRF_CLKEN_IN),
 753
 754         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKOUT),
 755         PINMUX_IPSR_GPSR(IP8_27_24,     DIGRF_CLKEN_OUT),
 756 };
 757
 758 static const struct sh_pfc_pin pinmux_pins[] = {
 759         PINMUX_GPIO_GP_ALL(),
 760 };
 761
 762 /* - EtherAVB --------------------------------------------------------------- */
 763 static const unsigned int avb0_rx_ctrl_pins[] = {
 764         /* AVB0_RX_CTL */
 765         RCAR_GP_PIN(1, 1),
 766 };
 767 static const unsigned int avb0_rx_ctrl_mux[] = {
 768         AVB0_RX_CTL_MARK,
 769 };
 770 static const unsigned int avb0_rxc_pins[] = {
 771         /* AVB0_RXC */
 772         RCAR_GP_PIN(1, 2),
 773 };
 774 static const unsigned int avb0_rxc_mux[] = {
 775         AVB0_RXC_MARK,
 776 };
 777 static const unsigned int avb0_rd0_pins[] = {
 778         /* AVB0_RD[0] */
 779         RCAR_GP_PIN(1, 3),
 780 };
 781 static const unsigned int avb0_rd0_mux[] = {
 782         AVB0_RD0_MARK,
 783 };
 784 static const unsigned int avb0_rd1_pins[] = {
 785         /* AVB0_RD[1] */
 786         RCAR_GP_PIN(1, 4),
 787 };
 788 static const unsigned int avb0_rd1_mux[] = {
 789         AVB0_RD1_MARK,
 790 };
 791 static const unsigned int avb0_rd2_pins[] = {
 792         /* AVB0_RD[2] */
 793         RCAR_GP_PIN(1, 5),
 794 };
 795 static const unsigned int avb0_rd2_mux[] = {
 796         AVB0_RD2_MARK,
 797 };
 798 static const unsigned int avb0_rd3_pins[] = {
 799         /* AVB0_RD[3] */
 800         RCAR_GP_PIN(1, 6),
 801 };
 802 static const unsigned int avb0_rd3_mux[] = {
 803         AVB0_RD3_MARK,
 804 };
 805 static const unsigned int avb0_rd4_pins[] = {
 806         /* AVB0_RD[3:0] */
 807         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
 808         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
 809 };
 810 static const unsigned int avb0_rd4_mux[] = {
 811         AVB0_RD0_MARK, AVB0_RD1_MARK,
 812         AVB0_RD2_MARK, AVB0_RD3_MARK,
 813 };
 814 static const unsigned int avb0_tx_ctrl_pins[] = {
 815         /* AVB0_TX_CTL */
 816         RCAR_GP_PIN(1, 7),
 817 };
 818 static const unsigned int avb0_tx_ctrl_mux[] = {
 819         AVB0_TX_CTL_MARK,
 820 };
 821 static const unsigned int avb0_txc_pins[] = {
 822         /* AVB0_TXC */
 823         RCAR_GP_PIN(1, 8),
 824 };
 825 static const unsigned int avb0_txc_mux[] = {
 826         AVB0_TXC_MARK,
 827 };
 828 static const unsigned int avb0_td0_pins[] = {
 829         /* AVB0_TD[0] */
 830         RCAR_GP_PIN(1, 9),
 831 };
 832 static const unsigned int avb0_td0_mux[] = {
 833         AVB0_TD0_MARK,
 834 };
 835 static const unsigned int avb0_td1_pins[] = {
 836         /* AVB0_TD[1] */
 837         RCAR_GP_PIN(1, 10),
 838 };
 839 static const unsigned int avb0_td1_mux[] = {
 840         AVB0_TD1_MARK,
 841 };
 842 static const unsigned int avb0_td2_pins[] = {
 843         /* AVB0_TD[2] */
 844         RCAR_GP_PIN(1, 11),
 845 };
 846 static const unsigned int avb0_td2_mux[] = {
 847         AVB0_TD2_MARK,
 848 };
 849 static const unsigned int avb0_td3_pins[] = {
 850         /* AVB0_TD[3] */
 851         RCAR_GP_PIN(1, 12),
 852 };
 853 static const unsigned int avb0_td3_mux[] = {
 854         AVB0_TD3_MARK,
 855 };
 856 static const unsigned int avb0_td4_pins[] = {
 857         /* AVB0_TD[3:0] */
 858         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
 859         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
 860 };
 861 static const unsigned int avb0_td4_mux[] = {
 862         AVB0_TD0_MARK, AVB0_TD1_MARK,
 863         AVB0_TD2_MARK, AVB0_TD3_MARK,
 864 };
 865 static const unsigned int avb0_txcrefclk_pins[] = {
 866         /* AVB0_TXCREFCLK */
 867         RCAR_GP_PIN(1, 13),
 868 };
 869 static const unsigned int avb0_txcrefclk_mux[] = {
 870         AVB0_TXCREFCLK_MARK,
 871 };
 872 static const unsigned int avb0_mdio_pins[] = {
 873         /* AVB0_MDIO */
 874         RCAR_GP_PIN(1, 14),
 875 };
 876 static const unsigned int avb0_mdio_mux[] = {
 877         AVB0_MDIO_MARK,
 878 };
 879 static const unsigned int avb0_mdc_pins[] = {
 880         /* AVB0_MDC */
 881         RCAR_GP_PIN(1, 15),
 882 };
 883 static const unsigned int avb0_mdc_mux[] = {
 884         AVB0_MDC_MARK,
 885 };
 886 static const unsigned int avb0_magic_pins[] = {
 887         /* AVB0_MAGIC */
 888         RCAR_GP_PIN(1, 16),
 889 };
 890 static const unsigned int avb0_magic_mux[] = {
 891         AVB0_MAGIC_MARK,
 892 };
 893 static const unsigned int avb0_phy_int_pins[] = {
 894         /* AVB0_PHY_INT */
 895         RCAR_GP_PIN(1, 17),
 896 };
 897 static const unsigned int avb0_phy_int_mux[] = {
 898         AVB0_PHY_INT_MARK,
 899 };
 900 static const unsigned int avb0_link_pins[] = {
 901         /* AVB0_LINK */
 902         RCAR_GP_PIN(1, 18),
 903 };
 904 static const unsigned int avb0_link_mux[] = {
 905         AVB0_LINK_MARK,
 906 };
 907 static const unsigned int avb0_avtp_match_pins[] = {
 908         /* AVB0_AVTP_MATCH */
 909         RCAR_GP_PIN(1, 19),
 910 };
 911 static const unsigned int avb0_avtp_match_mux[] = {
 912         AVB0_AVTP_MATCH_MARK,
 913 };
 914 static const unsigned int avb0_avtp_pps_pins[] = {
 915         /* AVB0_AVTP_PPS */
 916         RCAR_GP_PIN(2, 6),
 917 };
 918 static const unsigned int avb0_avtp_pps_mux[] = {
 919         AVB0_AVTP_PPS_MARK,
 920 };
 921 static const unsigned int avb0_avtp_capture_pins[] = {
 922         /* AVB0_AVTP_CAPTURE */
 923         RCAR_GP_PIN(1, 20),
 924 };
 925 static const unsigned int avb0_avtp_capture_mux[] = {
 926         AVB0_AVTP_CAPTURE_MARK,
 927 };
 928
 929 /* - CANFD0 ----------------------------------------------------------------- */
 930 static const unsigned int canfd0_data_a_pins[] = {
 931         /* TX, RX */
 932         RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
 933 };
 934 static const unsigned int canfd0_data_a_mux[] = {
 935         CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
 936 };
 937 static const unsigned int canfd_clk_a_pins[] = {
 938         /* CLK */
 939         RCAR_GP_PIN(1, 25),
 940 };
 941 static const unsigned int canfd_clk_a_mux[] = {
 942         CANFD_CLK_A_MARK,
 943 };
 944 static const unsigned int canfd0_data_b_pins[] = {
 945         /* TX, RX */
 946         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 947 };
 948 static const unsigned int canfd0_data_b_mux[] = {
 949         CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
 950 };
 951 static const unsigned int canfd_clk_b_pins[] = {
 952         /* CLK */
 953         RCAR_GP_PIN(3, 8),
 954 };
 955 static const unsigned int canfd_clk_b_mux[] = {
 956         CANFD_CLK_B_MARK,
 957 };
 958
 959 /* - CANFD1 ----------------------------------------------------------------- */
 960 static const unsigned int canfd1_data_pins[] = {
 961         /* TX, RX */
 962         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
 963 };
 964 static const unsigned int canfd1_data_mux[] = {
 965         CANFD1_TX_MARK, CANFD1_RX_MARK,
 966 };
 967
 968 /* - DU --------------------------------------------------------------------- */
 969 static const unsigned int du_rgb666_pins[] = {
 970         /* R[7:0] */
 971         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
 972         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 973         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 974         /* G[7:0] */
 975         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 976         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
 977         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
 978         /* B[7:0] */
 979         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
 980         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
 981         RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
 982 };
 983 static const unsigned int du_rgb666_mux[] = {
 984         DU_DR7_MARK, DU_DR6_MARK,
 985         DU_DR5_MARK, DU_DR4_MARK,
 986         DU_DR3_MARK, DU_DR2_MARK,
 987         DU_DG7_MARK, DU_DG6_MARK,
 988         DU_DG5_MARK, DU_DG4_MARK,
 989         DU_DG3_MARK, DU_DG2_MARK,
 990         DU_DB7_MARK, DU_DB6_MARK,
 991         DU_DB5_MARK, DU_DB4_MARK,
 992         DU_DB3_MARK, DU_DB2_MARK,
 993 };
 994 static const unsigned int du_clk_out_0_pins[] = {
 995         /* CLKOUT0 */
 996         RCAR_GP_PIN(0, 18),
 997 };
 998 static const unsigned int du_clk_out_0_mux[] = {
 999         DU_DOTCLKOUT_MARK,
1000 };
1001 static const unsigned int du_clk_out_1_pins[] = {
1002         /* CLKOUT1 */
1003         RCAR_GP_PIN(0, 18),             /* @@ */
1004 };
1005 static const unsigned int du_clk_out_1_mux[] = {
1006         DU_DOTCLKOUT_MARK,
1007 };
1008 static const unsigned int du_sync_pins[] = {
1009         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1010         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1011 };
1012 static const unsigned int du_sync_mux[] = {
1013         DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1014 };
1015 static const unsigned int du_oddf_pins[] = {
1016         /* EXDISP/EXODDF/EXCDE */
1017         RCAR_GP_PIN(0, 21),
1018 };
1019 static const unsigned int du_oddf_mux[] = {
1020         DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1021 };
1022 static const unsigned int du_cde_pins[] = {
1023         /* CDE */
1024         RCAR_GP_PIN(1, 22),
1025 };
1026 static const unsigned int du_cde_mux[] = {
1027         DU_CDE_MARK,
1028 };
1029 static const unsigned int du_disp_pins[] = {
1030         /* DISP */
1031         RCAR_GP_PIN(1, 21),
1032 };
1033 static const unsigned int du_disp_mux[] = {
1034         DU_DISP_MARK,
1035 };
1036
1037 /* - HSCIF0 ----------------------------------------------------------------- */
1038 static const unsigned int hscif0_data_pins[] = {
1039         /* HRX0, HTX0 */
1040         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
1041 };
1042 static const unsigned int hscif0_data_mux[] = {
1043         HRX0_MARK, HTX0_MARK,
1044 };
1045 static const unsigned int hscif0_clk_pins[] = {
1046         /* HSCK0 */
1047         RCAR_GP_PIN(0, 0),
1048 };
1049 static const unsigned int hscif0_clk_mux[] = {
1050         HSCK0_MARK,
1051 };
1052 static const unsigned int hscif0_ctrl_pins[] = {
1053         /* HRTS0#, HCTS0# */
1054         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1055 };
1056 static const unsigned int hscif0_ctrl_mux[] = {
1057         HRTS0_N_MARK, HCTS0_N_MARK,
1058 };
1059
1060 /* - HSCIF1 ----------------------------------------------------------------- */
1061 static const unsigned int hscif1_data_pins[] = {
1062         /* HRX1, HTX1 */
1063         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1064 };
1065 static const unsigned int hscif1_data_mux[] = {
1066         HRX1_MARK, HTX1_MARK,
1067 };
1068 static const unsigned int hscif1_clk_pins[] = {
1069         /* HSCK1 */
1070         RCAR_GP_PIN(2, 7),
1071 };
1072 static const unsigned int hscif1_clk_mux[] = {
1073         HSCK1_MARK,
1074 };
1075 static const unsigned int hscif1_ctrl_pins[] = {
1076         /* HRTS1#, HCTS1# */
1077         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1078 };
1079 static const unsigned int hscif1_ctrl_mux[] = {
1080         HRTS1_N_MARK, HCTS1_N_MARK,
1081 };
1082
1083 /* - HSCIF2 ----------------------------------------------------------------- */
1084 static const unsigned int hscif2_data_pins[] = {
1085         /* HRX2, HTX2 */
1086         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1087 };
1088 static const unsigned int hscif2_data_mux[] = {
1089         HRX2_MARK, HTX2_MARK,
1090 };
1091 static const unsigned int hscif2_clk_pins[] = {
1092         /* HSCK2 */
1093         RCAR_GP_PIN(2, 12),
1094 };
1095 static const unsigned int hscif2_clk_mux[] = {
1096         HSCK2_MARK,
1097 };
1098 static const unsigned int hscif2_ctrl_pins[] = {
1099         /* HRTS2#, HCTS2# */
1100         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1101 };
1102 static const unsigned int hscif2_ctrl_mux[] = {
1103         HRTS2_N_MARK, HCTS2_N_MARK,
1104 };
1105
1106 /* - HSCIF3 ----------------------------------------------------------------- */
1107 static const unsigned int hscif3_data_pins[] = {
1108         /* HRX3, HTX3 */
1109         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1110 };
1111 static const unsigned int hscif3_data_mux[] = {
1112         HRX3_MARK, HTX3_MARK,
1113 };
1114 static const unsigned int hscif3_clk_pins[] = {
1115         /* HSCK3 */
1116         RCAR_GP_PIN(2, 0),
1117 };
1118 static const unsigned int hscif3_clk_mux[] = {
1119         HSCK3_MARK,
1120 };
1121 static const unsigned int hscif3_ctrl_pins[] = {
1122         /* HRTS3#, HCTS3# */
1123         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1124 };
1125 static const unsigned int hscif3_ctrl_mux[] = {
1126         HRTS3_N_MARK, HCTS3_N_MARK,
1127 };
1128
1129 /* - SCIF Clock ------------------------------------------------------------- */
1130 static const unsigned int scif_clk_a_pins[] = {
1131         /* SCIF_CLK */
1132         RCAR_GP_PIN(0, 18),
1133 };
1134 static const unsigned int scif_clk_a_mux[] = {
1135         SCIF_CLK_A_MARK,
1136 };
1137 static const unsigned int scif_clk_b_pins[] = {
1138         /* SCIF_CLK */
1139         RCAR_GP_PIN(1, 25),
1140 };
1141 static const unsigned int scif_clk_b_mux[] = {
1142         SCIF_CLK_B_MARK,
1143 };
1144
1145 /* - I2C -------------------------------------------------------------------- */
1146 static const unsigned int i2c0_pins[] = {
1147         /* SDA0, SCL0 */
1148         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1149 };
1150 static const unsigned int i2c0_mux[] = {
1151         SDA0_MARK, SCL0_MARK,
1152 };
1153 static const unsigned int i2c1_pins[] = {
1154         /* SDA1, SCL1 */
1155         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1156 };
1157 static const unsigned int i2c1_mux[] = {
1158         SDA1_MARK, SCL1_MARK,
1159 };
1160 static const unsigned int i2c2_pins[] = {
1161         /* SDA2, SCL2 */
1162         RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1163 };
1164 static const unsigned int i2c2_mux[] = {
1165         SDA2_MARK, SCL2_MARK,
1166 };
1167 static const unsigned int i2c3_pins[] = {
1168         /* SDA3_A, SCL3_A */
1169         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1170 };
1171 static const unsigned int i2c3_mux[] = {
1172         SDA3_A_MARK, SCL3_A_MARK,
1173 };
1174 static const unsigned int i2c4_pins[] = {
1175         /* SDA4, SCL4 */
1176         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1177 };
1178 static const unsigned int i2c4_mux[] = {
1179         SDA4_MARK, SCL4_MARK,
1180 };
1181
1182 /* - INTC-EX ---------------------------------------------------------------- */
1183 static const unsigned int intc_ex_irq0_pins[] = {
1184         /* IRQ0 */
1185         RCAR_GP_PIN(1, 0),
1186 };
1187 static const unsigned int intc_ex_irq0_mux[] = {
1188         IRQ0_MARK,
1189 };
1190 static const unsigned int intc_ex_irq1_pins[] = {
1191         /* IRQ1 */
1192         RCAR_GP_PIN(0, 11),
1193 };
1194 static const unsigned int intc_ex_irq1_mux[] = {
1195         IRQ1_MARK,
1196 };
1197 static const unsigned int intc_ex_irq2_pins[] = {
1198         /* IRQ2 */
1199         RCAR_GP_PIN(0, 12),
1200 };
1201 static const unsigned int intc_ex_irq2_mux[] = {
1202         IRQ2_MARK,
1203 };
1204 static const unsigned int intc_ex_irq3_pins[] = {
1205         /* IRQ3 */
1206         RCAR_GP_PIN(0, 19),
1207 };
1208 static const unsigned int intc_ex_irq3_mux[] = {
1209         IRQ3_MARK,
1210 };
1211 static const unsigned int intc_ex_irq4_pins[] = {
1212         /* IRQ4 */
1213         RCAR_GP_PIN(3, 15),
1214 };
1215 static const unsigned int intc_ex_irq4_mux[] = {
1216         IRQ4_MARK,
1217 };
1218 static const unsigned int intc_ex_irq5_pins[] = {
1219         /* IRQ5 */
1220         RCAR_GP_PIN(3, 16),
1221 };
1222 static const unsigned int intc_ex_irq5_mux[] = {
1223         IRQ5_MARK,
1224 };
1225
1226 /* - MSIOF0 ----------------------------------------------------------------- */
1227 static const unsigned int msiof0_clk_pins[] = {
1228         /* SCK */
1229         RCAR_GP_PIN(4, 2),
1230 };
1231 static const unsigned int msiof0_clk_mux[] = {
1232         MSIOF0_SCK_MARK,
1233 };
1234 static const unsigned int msiof0_sync_pins[] = {
1235         /* SYNC */
1236         RCAR_GP_PIN(4, 3),
1237 };
1238 static const unsigned int msiof0_sync_mux[] = {
1239         MSIOF0_SYNC_MARK,
1240 };
1241 static const unsigned int msiof0_ss1_pins[] = {
1242         /* SS1 */
1243         RCAR_GP_PIN(4, 4),
1244 };
1245 static const unsigned int msiof0_ss1_mux[] = {
1246         MSIOF0_SS1_MARK,
1247 };
1248 static const unsigned int msiof0_ss2_pins[] = {
1249         /* SS2 */
1250         RCAR_GP_PIN(4, 5),
1251 };
1252 static const unsigned int msiof0_ss2_mux[] = {
1253         MSIOF0_SS2_MARK,
1254 };
1255 static const unsigned int msiof0_txd_pins[] = {
1256         /* TXD */
1257         RCAR_GP_PIN(4, 1),
1258 };
1259 static const unsigned int msiof0_txd_mux[] = {
1260         MSIOF0_TXD_MARK,
1261 };
1262 static const unsigned int msiof0_rxd_pins[] = {
1263         /* RXD */
1264         RCAR_GP_PIN(4, 0),
1265 };
1266 static const unsigned int msiof0_rxd_mux[] = {
1267         MSIOF0_RXD_MARK,
1268 };
1269
1270 /* - MSIOF1 ----------------------------------------------------------------- */
1271 static const unsigned int msiof1_clk_pins[] = {
1272         /* SCK */
1273         RCAR_GP_PIN(3, 2),
1274 };
1275 static const unsigned int msiof1_clk_mux[] = {
1276         MSIOF1_SCK_MARK,
1277 };
1278 static const unsigned int msiof1_sync_pins[] = {
1279         /* SYNC */
1280         RCAR_GP_PIN(3, 3),
1281 };
1282 static const unsigned int msiof1_sync_mux[] = {
1283         MSIOF1_SYNC_MARK,
1284 };
1285 static const unsigned int msiof1_ss1_pins[] = {
1286         /* SS1 */
1287         RCAR_GP_PIN(3, 4),
1288 };
1289 static const unsigned int msiof1_ss1_mux[] = {
1290         MSIOF1_SS1_MARK,
1291 };
1292 static const unsigned int msiof1_ss2_pins[] = {
1293         /* SS2 */
1294         RCAR_GP_PIN(3, 5),
1295 };
1296 static const unsigned int msiof1_ss2_mux[] = {
1297         MSIOF1_SS2_MARK,
1298 };
1299 static const unsigned int msiof1_txd_pins[] = {
1300         /* TXD */
1301         RCAR_GP_PIN(3, 1),
1302 };
1303 static const unsigned int msiof1_txd_mux[] = {
1304         MSIOF1_TXD_MARK,
1305 };
1306 static const unsigned int msiof1_rxd_pins[] = {
1307         /* RXD */
1308         RCAR_GP_PIN(3, 0),
1309 };
1310 static const unsigned int msiof1_rxd_mux[] = {
1311         MSIOF1_RXD_MARK,
1312 };
1313
1314 /* - MSIOF2 ----------------------------------------------------------------- */
1315 static const unsigned int msiof2_clk_pins[] = {
1316         /* SCK */
1317         RCAR_GP_PIN(2, 0),
1318 };
1319 static const unsigned int msiof2_clk_mux[] = {
1320         MSIOF2_SCK_MARK,
1321 };
1322 static const unsigned int msiof2_sync_pins[] = {
1323         /* SYNC */
1324         RCAR_GP_PIN(2, 3),
1325 };
1326 static const unsigned int msiof2_sync_mux[] = {
1327         MSIOF2_SYNC_MARK,
1328 };
1329 static const unsigned int msiof2_ss1_pins[] = {
1330         /* SS1 */
1331         RCAR_GP_PIN(2, 4),
1332 };
1333 static const unsigned int msiof2_ss1_mux[] = {
1334         MSIOF2_SS1_MARK,
1335 };
1336 static const unsigned int msiof2_ss2_pins[] = {
1337         /* SS2 */
1338         RCAR_GP_PIN(2, 5),
1339 };
1340 static const unsigned int msiof2_ss2_mux[] = {
1341         MSIOF2_SS2_MARK,
1342 };
1343 static const unsigned int msiof2_txd_pins[] = {
1344         /* TXD */
1345         RCAR_GP_PIN(2, 2),
1346 };
1347 static const unsigned int msiof2_txd_mux[] = {
1348         MSIOF2_TXD_MARK,
1349 };
1350 static const unsigned int msiof2_rxd_pins[] = {
1351         /* RXD */
1352         RCAR_GP_PIN(2, 1),
1353 };
1354 static const unsigned int msiof2_rxd_mux[] = {
1355         MSIOF2_RXD_MARK,
1356 };
1357
1358 /* - MSIOF3 ----------------------------------------------------------------- */
1359 static const unsigned int msiof3_clk_pins[] = {
1360         /* SCK */
1361         RCAR_GP_PIN(0, 20),
1362 };
1363 static const unsigned int msiof3_clk_mux[] = {
1364         MSIOF3_SCK_MARK,
1365 };
1366 static const unsigned int msiof3_sync_pins[] = {
1367         /* SYNC */
1368         RCAR_GP_PIN(0, 21),
1369 };
1370 static const unsigned int msiof3_sync_mux[] = {
1371         MSIOF3_SYNC_MARK,
1372 };
1373 static const unsigned int msiof3_ss1_pins[] = {
1374         /* SS1 */
1375         RCAR_GP_PIN(0, 6),
1376 };
1377 static const unsigned int msiof3_ss1_mux[] = {
1378         MSIOF3_SS1_MARK,
1379 };
1380 static const unsigned int msiof3_ss2_pins[] = {
1381         /* SS2 */
1382         RCAR_GP_PIN(0, 7),
1383 };
1384 static const unsigned int msiof3_ss2_mux[] = {
1385         MSIOF3_SS2_MARK,
1386 };
1387 static const unsigned int msiof3_txd_pins[] = {
1388         /* TXD */
1389         RCAR_GP_PIN(0, 5),
1390 };
1391 static const unsigned int msiof3_txd_mux[] = {
1392         MSIOF3_TXD_MARK,
1393 };
1394 static const unsigned int msiof3_rxd_pins[] = {
1395         /* RXD */
1396         RCAR_GP_PIN(0, 4),
1397 };
1398 static const unsigned int msiof3_rxd_mux[] = {
1399         MSIOF3_RXD_MARK,
1400 };
1401
1402 /* - PWM0 ------------------------------------------------------------------- */
1403 static const unsigned int pwm0_a_pins[] = {
1404         /* PWM0 */
1405         RCAR_GP_PIN(2, 12),
1406 };
1407 static const unsigned int pwm0_a_mux[] = {
1408         PWM0_A_MARK,
1409 };
1410 static const unsigned int pwm0_b_pins[] = {
1411         /* PWM0 */
1412         RCAR_GP_PIN(1, 21),
1413 };
1414 static const unsigned int pwm0_b_mux[] = {
1415         PWM0_B_MARK,
1416 };
1417
1418 /* - PWM1 ------------------------------------------------------------------- */
1419 static const unsigned int pwm1_a_pins[] = {
1420         /* PWM1 */
1421         RCAR_GP_PIN(2, 13),
1422 };
1423 static const unsigned int pwm1_a_mux[] = {
1424         PWM1_A_MARK,
1425 };
1426 static const unsigned int pwm1_b_pins[] = {
1427         /* PWM1 */
1428         RCAR_GP_PIN(1, 22),
1429 };
1430 static const unsigned int pwm1_b_mux[] = {
1431         PWM1_B_MARK,
1432 };
1433
1434 /* - PWM2 ------------------------------------------------------------------- */
1435 static const unsigned int pwm2_a_pins[] = {
1436         /* PWM2 */
1437         RCAR_GP_PIN(2, 14),
1438 };
1439 static const unsigned int pwm2_a_mux[] = {
1440         PWM2_A_MARK,
1441 };
1442 static const unsigned int pwm2_b_pins[] = {
1443         /* PWM2 */
1444         RCAR_GP_PIN(1, 23),
1445 };
1446 static const unsigned int pwm2_b_mux[] = {
1447         PWM2_B_MARK,
1448 };
1449
1450 /* - PWM3 ------------------------------------------------------------------- */
1451 static const unsigned int pwm3_a_pins[] = {
1452         /* PWM3 */
1453         RCAR_GP_PIN(2, 15),
1454 };
1455 static const unsigned int pwm3_a_mux[] = {
1456         PWM3_A_MARK,
1457 };
1458 static const unsigned int pwm3_b_pins[] = {
1459         /* PWM3 */
1460         RCAR_GP_PIN(1, 24),
1461 };
1462 static const unsigned int pwm3_b_mux[] = {
1463         PWM3_B_MARK,
1464 };
1465
1466 /* - PWM4 ------------------------------------------------------------------- */
1467 static const unsigned int pwm4_a_pins[] = {
1468         /* PWM4 */
1469         RCAR_GP_PIN(2, 16),
1470 };
1471 static const unsigned int pwm4_a_mux[] = {
1472         PWM4_A_MARK,
1473 };
1474 static const unsigned int pwm4_b_pins[] = {
1475         /* PWM4 */
1476         RCAR_GP_PIN(1, 25),
1477 };
1478 static const unsigned int pwm4_b_mux[] = {
1479         PWM4_B_MARK,
1480 };
1481
1482 /* - SCIF0 ------------------------------------------------------------------ */
1483 static const unsigned int scif0_data_pins[] = {
1484         /* RX, TX */
1485         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1486 };
1487 static const unsigned int scif0_data_mux[] = {
1488         RX0_MARK, TX0_MARK,
1489 };
1490 static const unsigned int scif0_clk_pins[] = {
1491         /* SCK */
1492         RCAR_GP_PIN(4, 1),
1493 };
1494 static const unsigned int scif0_clk_mux[] = {
1495         SCK0_MARK,
1496 };
1497
1498 static const unsigned int scif0_ctrl_pins[] = {
1499         /* RTS, CTS */
1500         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1501 };
1502 static const unsigned int scif0_ctrl_mux[] = {
1503         RTS0_N_TANS_MARK, CTS0_N_MARK,
1504 };
1505
1506 /* - SCIF1 ------------------------------------------------------------------ */
1507 static const unsigned int scif1_data_a_pins[] = {
1508         /* RX, TX */
1509         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1510 };
1511 static const unsigned int scif1_data_a_mux[] = {
1512         RX1_A_MARK, TX1_A_MARK,
1513 };
1514 static const unsigned int scif1_clk_pins[] = {
1515         /* SCK */
1516         RCAR_GP_PIN(2, 5),
1517 };
1518 static const unsigned int scif1_clk_mux[] = {
1519         SCK1_MARK,
1520 };
1521 static const unsigned int scif1_ctrl_pins[] = {
1522         /* RTS, CTS */
1523         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1524 };
1525 static const unsigned int scif1_ctrl_mux[] = {
1526         RTS1_N_TANS_MARK, CTS1_N_MARK,
1527 };
1528 static const unsigned int scif1_data_b_pins[] = {
1529         /* RX, TX */
1530         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1531 };
1532 static const unsigned int scif1_data_b_mux[] = {
1533         RX1_B_MARK, TX1_B_MARK,
1534 };
1535
1536 /* - SCIF3 ------------------------------------------------------------------ */
1537 static const unsigned int scif3_data_pins[] = {
1538         /* RX, TX */
1539         RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1540 };
1541 static const unsigned int scif3_data_mux[] = {
1542         RX3_MARK, TX3_MARK,
1543 };
1544 static const unsigned int scif3_clk_pins[] = {
1545         /* SCK */
1546         RCAR_GP_PIN(2, 0),
1547 };
1548 static const unsigned int scif3_clk_mux[] = {
1549         SCK3_MARK,
1550 };
1551 static const unsigned int scif3_ctrl_pins[] = {
1552         /* RTS, CTS */
1553         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1554 };
1555 static const unsigned int scif3_ctrl_mux[] = {
1556         RTS3_N_TANS_MARK, CTS3_N_MARK,
1557 };
1558
1559 /* - SCIF4 ------------------------------------------------------------------ */
1560 static const unsigned int scif4_data_pins[] = {
1561         /* RX, TX */
1562         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1563 };
1564 static const unsigned int scif4_data_mux[] = {
1565         RX4_MARK, TX4_MARK,
1566 };
1567 static const unsigned int scif4_clk_pins[] = {
1568         /* SCK */
1569         RCAR_GP_PIN(3, 9),
1570 };
1571 static const unsigned int scif4_clk_mux[] = {
1572         SCK4_MARK,
1573 };
1574 static const unsigned int scif4_ctrl_pins[] = {
1575         /* RTS, CTS */
1576         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1577 };
1578 static const unsigned int scif4_ctrl_mux[] = {
1579         RTS4_N_TANS_MARK, CTS4_N_MARK,
1580 };
1581
1582 /* - MMC -------------------------------------------------------------------- */
1583 static const unsigned int mmc_data1_pins[] = {
1584         /* D0 */
1585         RCAR_GP_PIN(3, 6),
1586 };
1587 static const unsigned int mmc_data1_mux[] = {
1588         MMC_D0_MARK,
1589 };
1590 static const unsigned int mmc_data4_pins[] = {
1591         /* D[0:3] */
1592         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1593         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1594 };
1595 static const unsigned int mmc_data4_mux[] = {
1596         MMC_D0_MARK, MMC_D1_MARK,
1597         MMC_D2_MARK, MMC_D3_MARK,
1598 };
1599 static const unsigned int mmc_data8_pins[] = {
1600         /* D[0:7] */
1601         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1602         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1603         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1604         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1605 };
1606 static const unsigned int mmc_data8_mux[] = {
1607         MMC_D0_MARK, MMC_D1_MARK,
1608         MMC_D2_MARK, MMC_D3_MARK,
1609         MMC_D4_MARK, MMC_D5_MARK,
1610         MMC_D6_MARK, MMC_D7_MARK,
1611 };
1612 static const unsigned int mmc_ctrl_pins[] = {
1613         /* CLK, CMD */
1614         RCAR_GP_PIN(3,10), RCAR_GP_PIN(3, 5),
1615 };
1616 static const unsigned int mmc_ctrl_mux[] = {
1617         MMC_CLK_MARK, MMC_CMD_MARK,
1618 };
1619 static const unsigned int mmc_cd_pins[] = {
1620         /* CD */
1621         RCAR_GP_PIN(3, 16),
1622 };
1623 static const unsigned int mmc_cd_mux[] = {
1624         MMC_CD_MARK,
1625 };
1626 static const unsigned int mmc_wp_pins[] = {
1627         /* WP */
1628         RCAR_GP_PIN(3, 15),
1629 };
1630 static const unsigned int mmc_wp_mux[] = {
1631         MMC_WP_MARK,
1632 };
1633
1634 /* - TMU -------------------------------------------------------------------- */
1635 static const unsigned int tmu_tclk1_a_pins[] = {
1636         /* TCLK1 */
1637         RCAR_GP_PIN(4, 4),
1638 };
1639 static const unsigned int tmu_tclk1_a_mux[] = {
1640         TCLK1_A_MARK,
1641 };
1642 static const unsigned int tmu_tclk1_b_pins[] = {
1643         /* TCLK1 */
1644         RCAR_GP_PIN(1, 23),
1645 };
1646 static const unsigned int tmu_tclk1_b_mux[] = {
1647         TCLK1_B_MARK,
1648 };
1649 static const unsigned int tmu_tclk2_a_pins[] = {
1650         /* TCLK2 */
1651         RCAR_GP_PIN(4, 5),
1652 };
1653 static const unsigned int tmu_tclk2_a_mux[] = {
1654         TCLK2_A_MARK,
1655 };
1656 static const unsigned int tmu_tclk2_b_pins[] = {
1657         /* TCLK2 */
1658         RCAR_GP_PIN(1, 24),
1659 };
1660 static const unsigned int tmu_tclk2_b_mux[] = {
1661         TCLK2_B_MARK,
1662 };
1663
1664 /* - VIN0 ------------------------------------------------------------------- */
1665 static const unsigned int vin0_data8_pins[] = {
1666         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1667         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1668         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1669         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1670 };
1671 static const unsigned int vin0_data8_mux[] = {
1672         VI0_DATA0_MARK, VI0_DATA1_MARK,
1673         VI0_DATA2_MARK, VI0_DATA3_MARK,
1674         VI0_DATA4_MARK, VI0_DATA5_MARK,
1675         VI0_DATA6_MARK, VI0_DATA7_MARK,
1676 };
1677 static const unsigned int vin0_data10_pins[] = {
1678         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1679         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1680         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1681         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1682         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1683 };
1684 static const unsigned int vin0_data10_mux[] = {
1685         VI0_DATA0_MARK, VI0_DATA1_MARK,
1686         VI0_DATA2_MARK, VI0_DATA3_MARK,
1687         VI0_DATA4_MARK, VI0_DATA5_MARK,
1688         VI0_DATA6_MARK, VI0_DATA7_MARK,
1689         VI0_DATA8_MARK,  VI0_DATA9_MARK,
1690 };
1691 static const unsigned int vin0_data12_pins[] = {
1692         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1693         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1694         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1695         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1696         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1697         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1698 };
1699 static const unsigned int vin0_data12_mux[] = {
1700         VI0_DATA0_MARK, VI0_DATA1_MARK,
1701         VI0_DATA2_MARK, VI0_DATA3_MARK,
1702         VI0_DATA4_MARK, VI0_DATA5_MARK,
1703         VI0_DATA6_MARK, VI0_DATA7_MARK,
1704         VI0_DATA8_MARK,  VI0_DATA9_MARK,
1705         VI0_DATA10_MARK, VI0_DATA11_MARK,
1706 };
1707 static const unsigned int vin0_sync_pins[] = {
1708         /* VSYNC_N, HSYNC_N */
1709         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1710 };
1711 static const unsigned int vin0_sync_mux[] = {
1712         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1713 };
1714 static const unsigned int vin0_field_pins[] = {
1715         /* FIELD */
1716         RCAR_GP_PIN(2, 16),
1717 };
1718 static const unsigned int vin0_field_mux[] = {
1719         VI0_FIELD_MARK,
1720 };
1721 static const unsigned int vin0_clkenb_pins[] = {
1722         /* CLKENB */
1723         RCAR_GP_PIN(2, 1),
1724 };
1725 static const unsigned int vin0_clkenb_mux[] = {
1726         VI0_CLKENB_MARK,
1727 };
1728 static const unsigned int vin0_clk_pins[] = {
1729         /* CLK */
1730         RCAR_GP_PIN(2, 0),
1731 };
1732 static const unsigned int vin0_clk_mux[] = {
1733         VI0_CLK_MARK,
1734 };
1735 /* - VIN1 ------------------------------------------------------------------- */
1736 static const unsigned int vin1_data8_pins[] = {
1737         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1738         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1739         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1740         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1741 };
1742 static const unsigned int vin1_data8_mux[] = {
1743         VI1_DATA0_MARK, VI1_DATA1_MARK,
1744         VI1_DATA2_MARK, VI1_DATA3_MARK,
1745         VI1_DATA4_MARK, VI1_DATA5_MARK,
1746         VI1_DATA6_MARK, VI1_DATA7_MARK,
1747 };
1748 static const unsigned int vin1_data10_pins[] = {
1749         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1750         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1751         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1752         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1753         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1754 };
1755 static const unsigned int vin1_data10_mux[] = {
1756         VI1_DATA0_MARK, VI1_DATA1_MARK,
1757         VI1_DATA2_MARK, VI1_DATA3_MARK,
1758         VI1_DATA4_MARK, VI1_DATA5_MARK,
1759         VI1_DATA6_MARK, VI1_DATA7_MARK,
1760         VI1_DATA8_MARK,  VI1_DATA9_MARK,
1761 };
1762 static const unsigned int vin1_data12_pins[] = {
1763         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1764         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1765         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1766         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1767         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1768         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1769 };
1770 static const unsigned int vin1_data12_mux[] = {
1771         VI1_DATA0_MARK, VI1_DATA1_MARK,
1772         VI1_DATA2_MARK, VI1_DATA3_MARK,
1773         VI1_DATA4_MARK, VI1_DATA5_MARK,
1774         VI1_DATA6_MARK, VI1_DATA7_MARK,
1775         VI1_DATA8_MARK,  VI1_DATA9_MARK,
1776         VI1_DATA10_MARK, VI1_DATA11_MARK,
1777 };
1778 static const unsigned int vin1_sync_pins[] = {
1779         /* VSYNC_N, HSYNC_N */
1780          RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1781 };
1782 static const unsigned int vin1_sync_mux[] = {
1783         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1784 };
1785 static const unsigned int vin1_field_pins[] = {
1786         /* FIELD */
1787         RCAR_GP_PIN(3, 16),
1788 };
1789 static const unsigned int vin1_field_mux[] = {
1790         VI1_FIELD_MARK,
1791 };
1792 static const unsigned int vin1_clkenb_pins[] = {
1793         /* CLKENB */
1794         RCAR_GP_PIN(3, 1),
1795 };
1796 static const unsigned int vin1_clkenb_mux[] = {
1797         VI1_CLKENB_MARK,
1798 };
1799 static const unsigned int vin1_clk_pins[] = {
1800         /* CLK */
1801         RCAR_GP_PIN(3, 0),
1802 };
1803 static const unsigned int vin1_clk_mux[] = {
1804         VI1_CLK_MARK,
1805 };
1806
1807 static const struct sh_pfc_pin_group pinmux_groups[] = {
1808         SH_PFC_PIN_GROUP(avb0_rx_ctrl),
1809         SH_PFC_PIN_GROUP(avb0_rxc),
1810         SH_PFC_PIN_GROUP(avb0_rd0),
1811         SH_PFC_PIN_GROUP(avb0_rd1),
1812         SH_PFC_PIN_GROUP(avb0_rd2),
1813         SH_PFC_PIN_GROUP(avb0_rd3),
1814         SH_PFC_PIN_GROUP(avb0_rd4),
1815         SH_PFC_PIN_GROUP(avb0_tx_ctrl),
1816         SH_PFC_PIN_GROUP(avb0_txc),
1817         SH_PFC_PIN_GROUP(avb0_td0),
1818         SH_PFC_PIN_GROUP(avb0_td1),
1819         SH_PFC_PIN_GROUP(avb0_td2),
1820         SH_PFC_PIN_GROUP(avb0_td3),
1821         SH_PFC_PIN_GROUP(avb0_td4),
1822         SH_PFC_PIN_GROUP(avb0_txcrefclk),
1823         SH_PFC_PIN_GROUP(avb0_mdio),
1824         SH_PFC_PIN_GROUP(avb0_mdc),
1825         SH_PFC_PIN_GROUP(avb0_magic),
1826         SH_PFC_PIN_GROUP(avb0_phy_int),
1827         SH_PFC_PIN_GROUP(avb0_link),
1828         SH_PFC_PIN_GROUP(avb0_avtp_match),
1829         SH_PFC_PIN_GROUP(avb0_avtp_pps),
1830         SH_PFC_PIN_GROUP(avb0_avtp_capture),
1831         SH_PFC_PIN_GROUP(canfd0_data_a),
1832         SH_PFC_PIN_GROUP(canfd_clk_a),
1833         SH_PFC_PIN_GROUP(canfd0_data_b),
1834         SH_PFC_PIN_GROUP(canfd_clk_b),
1835         SH_PFC_PIN_GROUP(canfd1_data),
1836         SH_PFC_PIN_GROUP(du_rgb666),
1837         SH_PFC_PIN_GROUP(du_clk_out_0),
1838         SH_PFC_PIN_GROUP(du_clk_out_1),
1839         SH_PFC_PIN_GROUP(du_sync),
1840         SH_PFC_PIN_GROUP(du_oddf),
1841         SH_PFC_PIN_GROUP(du_cde),
1842         SH_PFC_PIN_GROUP(du_disp),
1843         SH_PFC_PIN_GROUP(hscif0_data),
1844         SH_PFC_PIN_GROUP(hscif0_clk),
1845         SH_PFC_PIN_GROUP(hscif0_ctrl),
1846         SH_PFC_PIN_GROUP(hscif1_data),
1847         SH_PFC_PIN_GROUP(hscif1_clk),
1848         SH_PFC_PIN_GROUP(hscif1_ctrl),
1849         SH_PFC_PIN_GROUP(hscif2_data),
1850         SH_PFC_PIN_GROUP(hscif2_clk),
1851         SH_PFC_PIN_GROUP(hscif2_ctrl),
1852         SH_PFC_PIN_GROUP(hscif3_data),
1853         SH_PFC_PIN_GROUP(hscif3_clk),
1854         SH_PFC_PIN_GROUP(hscif3_ctrl),
1855         SH_PFC_PIN_GROUP(scif_clk_a),
1856         SH_PFC_PIN_GROUP(scif_clk_b),
1857         SH_PFC_PIN_GROUP(i2c0),
1858         SH_PFC_PIN_GROUP(i2c1),
1859         SH_PFC_PIN_GROUP(i2c2),
1860         SH_PFC_PIN_GROUP(i2c3),
1861         SH_PFC_PIN_GROUP(i2c4),
1862         SH_PFC_PIN_GROUP(intc_ex_irq0),
1863         SH_PFC_PIN_GROUP(intc_ex_irq1),
1864         SH_PFC_PIN_GROUP(intc_ex_irq2),
1865         SH_PFC_PIN_GROUP(intc_ex_irq3),
1866         SH_PFC_PIN_GROUP(intc_ex_irq4),
1867         SH_PFC_PIN_GROUP(intc_ex_irq5),
1868         SH_PFC_PIN_GROUP(msiof0_clk),
1869         SH_PFC_PIN_GROUP(msiof0_sync),
1870         SH_PFC_PIN_GROUP(msiof0_ss1),
1871         SH_PFC_PIN_GROUP(msiof0_ss2),
1872         SH_PFC_PIN_GROUP(msiof0_txd),
1873         SH_PFC_PIN_GROUP(msiof0_rxd),
1874         SH_PFC_PIN_GROUP(msiof1_clk),
1875         SH_PFC_PIN_GROUP(msiof1_sync),
1876         SH_PFC_PIN_GROUP(msiof1_ss1),
1877         SH_PFC_PIN_GROUP(msiof1_ss2),
1878         SH_PFC_PIN_GROUP(msiof1_txd),
1879         SH_PFC_PIN_GROUP(msiof1_rxd),
1880         SH_PFC_PIN_GROUP(msiof2_clk),
1881         SH_PFC_PIN_GROUP(msiof2_sync),
1882         SH_PFC_PIN_GROUP(msiof2_ss1),
1883         SH_PFC_PIN_GROUP(msiof2_ss2),
1884         SH_PFC_PIN_GROUP(msiof2_txd),
1885         SH_PFC_PIN_GROUP(msiof2_rxd),
1886         SH_PFC_PIN_GROUP(msiof3_clk),
1887         SH_PFC_PIN_GROUP(msiof3_sync),
1888         SH_PFC_PIN_GROUP(msiof3_ss1),
1889         SH_PFC_PIN_GROUP(msiof3_ss2),
1890         SH_PFC_PIN_GROUP(msiof3_txd),
1891         SH_PFC_PIN_GROUP(msiof3_rxd),
1892         SH_PFC_PIN_GROUP(pwm0_a),
1893         SH_PFC_PIN_GROUP(pwm0_b),
1894         SH_PFC_PIN_GROUP(pwm1_a),
1895         SH_PFC_PIN_GROUP(pwm1_b),
1896         SH_PFC_PIN_GROUP(pwm2_a),
1897         SH_PFC_PIN_GROUP(pwm2_b),
1898         SH_PFC_PIN_GROUP(pwm3_a),
1899         SH_PFC_PIN_GROUP(pwm3_b),
1900         SH_PFC_PIN_GROUP(pwm4_a),
1901         SH_PFC_PIN_GROUP(pwm4_b),
1902         SH_PFC_PIN_GROUP(scif0_data),
1903         SH_PFC_PIN_GROUP(scif0_clk),
1904         SH_PFC_PIN_GROUP(scif0_ctrl),
1905         SH_PFC_PIN_GROUP(scif1_data_a),
1906         SH_PFC_PIN_GROUP(scif1_clk),
1907         SH_PFC_PIN_GROUP(scif1_ctrl),
1908         SH_PFC_PIN_GROUP(scif1_data_b),
1909         SH_PFC_PIN_GROUP(scif3_data),
1910         SH_PFC_PIN_GROUP(scif3_clk),
1911         SH_PFC_PIN_GROUP(scif3_ctrl),
1912         SH_PFC_PIN_GROUP(scif4_data),
1913         SH_PFC_PIN_GROUP(scif4_clk),
1914         SH_PFC_PIN_GROUP(scif4_ctrl),
1915         SH_PFC_PIN_GROUP(mmc_data1),
1916         SH_PFC_PIN_GROUP(mmc_data4),
1917         SH_PFC_PIN_GROUP(mmc_data8),
1918         SH_PFC_PIN_GROUP(mmc_ctrl),
1919         SH_PFC_PIN_GROUP(mmc_cd),
1920         SH_PFC_PIN_GROUP(mmc_wp),
1921         SH_PFC_PIN_GROUP(tmu_tclk1_a),
1922         SH_PFC_PIN_GROUP(tmu_tclk1_b),
1923         SH_PFC_PIN_GROUP(tmu_tclk2_a),
1924         SH_PFC_PIN_GROUP(tmu_tclk2_b),
1925         SH_PFC_PIN_GROUP(vin0_data8),
1926         SH_PFC_PIN_GROUP(vin0_data10),
1927         SH_PFC_PIN_GROUP(vin0_data12),
1928         SH_PFC_PIN_GROUP(vin0_sync),
1929         SH_PFC_PIN_GROUP(vin0_field),
1930         SH_PFC_PIN_GROUP(vin0_clkenb),
1931         SH_PFC_PIN_GROUP(vin0_clk),
1932         SH_PFC_PIN_GROUP(vin1_data8),
1933         SH_PFC_PIN_GROUP(vin1_data10),
1934         SH_PFC_PIN_GROUP(vin1_data12),
1935         SH_PFC_PIN_GROUP(vin1_sync),
1936         SH_PFC_PIN_GROUP(vin1_field),
1937         SH_PFC_PIN_GROUP(vin1_clkenb),
1938         SH_PFC_PIN_GROUP(vin1_clk),
1939 };
1940
1941 static const char * const avb0_groups[] = {
1942         "avb0_rx_ctrl",
1943         "avb0_rxc",
1944         "avb0_rd1",
1945         "avb0_rd4",
1946         "avb0_tx_ctrl",
1947         "avb0_txc",
1948         "avb0_td1",
1949         "avb0_td4",
1950         "avb0_txcrefclk",
1951         "avb0_mdio",
1952         "avb0_mdc",
1953         "avb0_magic",
1954         "avb0_phy_int",
1955         "avb0_link",
1956         "avb0_avtp_match",
1957         "avb0_avtp_pps",
1958         "avb0_avtp_capture",
1959 };
1960
1961 static const char * const canfd0_groups[] = {
1962         "canfd0_data_a",
1963         "canfd_clk_a",
1964         "canfd0_data_b",
1965         "canfd_clk_b",
1966 };
1967
1968 static const char * const canfd1_groups[] = {
1969         "canfd1_data",
1970 };
1971
1972 static const char * const du_groups[] = {
1973         "du_rgb666",
1974         "du_clk_out_0",
1975         "du_clk_out_1",
1976         "du_sync",
1977         "du_oddf",
1978         "du_cde",
1979         "du_disp",
1980 };
1981
1982 static const char * const hscif0_groups[] = {
1983         "hscif0_data",
1984         "hscif0_clk",
1985         "hscif0_ctrl",
1986 };
1987
1988 static const char * const hscif1_groups[] = {
1989         "hscif1_data",
1990         "hscif1_clk",
1991         "hscif1_ctrl",
1992 };
1993
1994 static const char * const hscif2_groups[] = {
1995         "hscif2_data",
1996         "hscif2_clk",
1997         "hscif2_ctrl",
1998 };
1999
2000 static const char * const hscif3_groups[] = {
2001         "hscif3_data",
2002         "hscif3_clk",
2003         "hscif3_ctrl",
2004 };
2005
2006 static const char * const scif_clk_groups[] = {
2007         "scif_clk_a",
2008         "scif_clk_b",
2009 };
2010
2011 static const char * const i2c0_groups[] = {
2012         "i2c0",
2013 };
2014
2015 static const char * const i2c1_groups[] = {
2016         "i2c1",
2017 };
2018
2019 static const char * const i2c2_groups[] = {
2020         "i2c2",
2021 };
2022
2023 static const char * const i2c3_groups[] = {
2024         "i2c3",
2025 };
2026
2027 static const char * const i2c4_groups[] = {
2028         "i2c4",
2029 };
2030
2031 static const char * const intc_ex_groups[] = {
2032         "intc_ex_irq0",
2033         "intc_ex_irq1",
2034         "intc_ex_irq2",
2035         "intc_ex_irq3",
2036         "intc_ex_irq4",
2037         "intc_ex_irq5",
2038 };
2039
2040 static const char * const msiof0_groups[] = {
2041         "msiof0_clk",
2042         "msiof0_sync",
2043         "msiof0_ss1",
2044         "msiof0_ss2",
2045         "msiof0_txd",
2046         "msiof0_rxd",
2047 };
2048
2049 static const char * const msiof1_groups[] = {
2050         "msiof1_clk",
2051         "msiof1_sync",
2052         "msiof1_ss1",
2053         "msiof1_ss2",
2054         "msiof1_txd",
2055         "msiof1_rxd",
2056 };
2057
2058 static const char * const msiof2_groups[] = {
2059         "msiof2_clk",
2060         "msiof2_sync",
2061         "msiof2_ss1",
2062         "msiof2_ss2",
2063         "msiof2_txd",
2064         "msiof2_rxd",
2065 };
2066
2067 static const char * const msiof3_groups[] = {
2068         "msiof3_clk",
2069         "msiof3_sync",
2070         "msiof3_ss1",
2071         "msiof3_ss2",
2072         "msiof3_txd",
2073         "msiof3_rxd",
2074 };
2075
2076 static const char * const pwm0_groups[] = {
2077         "pwm0_a",
2078         "pwm0_b",
2079 };
2080
2081 static const char * const pwm1_groups[] = {
2082         "pwm1_a",
2083         "pwm1_b",
2084 };
2085
2086 static const char * const pwm2_groups[] = {
2087         "pwm2_a",
2088         "pwm2_b",
2089 };
2090
2091 static const char * const pwm3_groups[] = {
2092         "pwm3_a",
2093         "pwm3_b",
2094 };
2095
2096 static const char * const pwm4_groups[] = {
2097         "pwm4_a",
2098         "pwm4_b",
2099 };
2100
2101 static const char * const scif0_groups[] = {
2102         "scif0_data",
2103 //      "scif0_clk",
2104 //      "scif0_ctrl",
2105 };
2106
2107 static const char * const scif1_groups[] = {
2108         "scif1_data_a",
2109         "scif1_clk",
2110         "scif1_ctrl",
2111         "scif1_data_b",
2112 };
2113
2114 static const char * const scif3_groups[] = {
2115         "scif3_data",
2116         "scif3_clk",
2117         "scif3_ctrl",
2118 };
2119
2120 static const char * const scif4_groups[] = {
2121         "scif4_data",
2122         "scif4_clk",
2123         "scif4_ctrl",
2124 };
2125
2126 static const char * const mmc_groups[] = {
2127         "mmc_data1",
2128         "mmc_data4",
2129         "mmc_data8",
2130         "mmc_ctrl",
2131         "mmc_cd",
2132         "mmc_wp",
2133 };
2134
2135 static const char * const tmu_groups[] = {
2136         "tmu_tclk1_a",
2137         "tmu_tclk1_b",
2138         "tmu_tclk2_a",
2139         "tmu_tclk2_b",
2140 };
2141
2142 static const char * const vin0_groups[] = {
2143         "vin0_data8",
2144         "vin0_data10",
2145         "vin0_data12",
2146         "vin0_sync",
2147         "vin0_field",
2148         "vin0_clkenb",
2149         "vin0_clk",
2150 };
2151
2152 static const char * const vin1_groups[] = {
2153         "vin1_data8",
2154         "vin1_data10",
2155         "vin1_data12",
2156         "vin1_sync",
2157         "vin1_field",
2158         "vin1_clkenb",
2159         "vin1_clk",
2160 };
2161
2162 #define POCCTRL0        0x380
2163 #define POCCTRL1        0x384
2164 #define PIN2POCCTRL0_SHIFT(a) ({ \
2165         int _gp = (a) >> 5; \
2166         int _bit = (a) & 0x1f; \
2167         ((_gp == 3) && (_bit < 17)) ? _bit + 7 : -1; \
2168 })
2169
2170
2171 static const struct sh_pfc_function pinmux_functions[] = {
2172         SH_PFC_FUNCTION(avb0),
2173         SH_PFC_FUNCTION(canfd0),
2174         SH_PFC_FUNCTION(canfd1),
2175         SH_PFC_FUNCTION(du),
2176         SH_PFC_FUNCTION(hscif0),
2177         SH_PFC_FUNCTION(hscif1),
2178         SH_PFC_FUNCTION(hscif2),
2179         SH_PFC_FUNCTION(hscif3),
2180         SH_PFC_FUNCTION(scif_clk),
2181         SH_PFC_FUNCTION(i2c0),
2182         SH_PFC_FUNCTION(i2c1),
2183         SH_PFC_FUNCTION(i2c2),
2184         SH_PFC_FUNCTION(i2c3),
2185         SH_PFC_FUNCTION(i2c4),
2186         SH_PFC_FUNCTION(intc_ex),
2187         SH_PFC_FUNCTION(msiof0),
2188         SH_PFC_FUNCTION(msiof1),
2189         SH_PFC_FUNCTION(msiof2),
2190         SH_PFC_FUNCTION(msiof3),
2191         SH_PFC_FUNCTION(pwm0),
2192         SH_PFC_FUNCTION(pwm1),
2193         SH_PFC_FUNCTION(pwm2),
2194         SH_PFC_FUNCTION(pwm3),
2195         SH_PFC_FUNCTION(pwm4),
2196         SH_PFC_FUNCTION(scif0),
2197         SH_PFC_FUNCTION(scif1),
2198         SH_PFC_FUNCTION(scif3),
2199         SH_PFC_FUNCTION(scif4),
2200         SH_PFC_FUNCTION(mmc),
2201         SH_PFC_FUNCTION(tmu),
2202         SH_PFC_FUNCTION(vin0),
2203         SH_PFC_FUNCTION(vin1),
2204 };
2205
2206 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2207 #define F_(x, y)        FN_##y
2208 #define FM(x)           FN_##x
2209         { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2210                 0, 0,
2211                 0, 0,
2212                 0, 0,
2213                 0, 0,
2214                 0, 0,
2215                 0, 0,
2216                 0, 0,
2217                 0, 0,
2218                 0, 0,
2219                 0, 0,
2220                 GP_0_21_FN,     GPSR0_21,
2221                 GP_0_20_FN,     GPSR0_20,
2222                 GP_0_19_FN,     GPSR0_19,
2223                 GP_0_18_FN,     GPSR0_18,
2224                 GP_0_17_FN,     GPSR0_17,
2225                 GP_0_16_FN,     GPSR0_16,
2226                 GP_0_15_FN,     GPSR0_15,
2227                 GP_0_14_FN,     GPSR0_14,
2228                 GP_0_13_FN,     GPSR0_13,
2229                 GP_0_12_FN,     GPSR0_12,
2230                 GP_0_11_FN,     GPSR0_11,
2231                 GP_0_10_FN,     GPSR0_10,
2232                 GP_0_9_FN,      GPSR0_9,
2233                 GP_0_8_FN,      GPSR0_8,
2234                 GP_0_7_FN,      GPSR0_7,
2235                 GP_0_6_FN,      GPSR0_6,
2236                 GP_0_5_FN,      GPSR0_5,
2237                 GP_0_4_FN,      GPSR0_4,
2238                 GP_0_3_FN,      GPSR0_3,
2239                 GP_0_2_FN,      GPSR0_2,
2240                 GP_0_1_FN,      GPSR0_1,
2241                 GP_0_0_FN,      GPSR0_0, }
2242         },
2243         { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2244                 0, 0,
2245                 0, 0,
2246                 0, 0,
2247                 0, 0,
2248                 GP_1_27_FN,     GPSR1_27,
2249                 GP_1_26_FN,     GPSR1_26,
2250                 GP_1_25_FN,     GPSR1_25,
2251                 GP_1_24_FN,     GPSR1_24,
2252                 GP_1_23_FN,     GPSR1_23,
2253                 GP_1_22_FN,     GPSR1_22,
2254                 GP_1_21_FN,     GPSR1_21,
2255                 GP_1_20_FN,     GPSR1_20,
2256                 GP_1_19_FN,     GPSR1_19,
2257                 GP_1_18_FN,     GPSR1_18,
2258                 GP_1_17_FN,     GPSR1_17,
2259                 GP_1_16_FN,     GPSR1_16,
2260                 GP_1_15_FN,     GPSR1_15,
2261                 GP_1_14_FN,     GPSR1_14,
2262                 GP_1_13_FN,     GPSR1_13,
2263                 GP_1_12_FN,     GPSR1_12,
2264                 GP_1_11_FN,     GPSR1_11,
2265                 GP_1_10_FN,     GPSR1_10,
2266                 GP_1_9_FN,      GPSR1_9,
2267                 GP_1_8_FN,      GPSR1_8,
2268                 GP_1_7_FN,      GPSR1_7,
2269                 GP_1_6_FN,      GPSR1_6,
2270                 GP_1_5_FN,      GPSR1_5,
2271                 GP_1_4_FN,      GPSR1_4,
2272                 GP_1_3_FN,      GPSR1_3,
2273                 GP_1_2_FN,      GPSR1_2,
2274                 GP_1_1_FN,      GPSR1_1,
2275                 GP_1_0_FN,      GPSR1_0, }
2276         },
2277         { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2278                 0, 0,
2279                 0, 0,
2280                 0, 0,
2281                 0, 0,
2282                 0, 0,
2283                 0, 0,
2284                 0, 0,
2285                 0, 0,
2286                 0, 0,
2287                 0, 0,
2288                 0, 0,
2289                 0, 0,
2290                 0, 0,
2291                 0, 0,
2292                 0, 0,
2293                 GP_2_16_FN,     GPSR2_16,
2294                 GP_2_15_FN,     GPSR2_15,
2295                 GP_2_14_FN,     GPSR2_14,
2296                 GP_2_13_FN,     GPSR2_13,
2297                 GP_2_12_FN,     GPSR2_12,
2298                 GP_2_11_FN,     GPSR2_11,
2299                 GP_2_10_FN,     GPSR2_10,
2300                 GP_2_9_FN,      GPSR2_9,
2301                 GP_2_8_FN,      GPSR2_8,
2302                 GP_2_7_FN,      GPSR2_7,
2303                 GP_2_6_FN,      GPSR2_6,
2304                 GP_2_5_FN,      GPSR2_5,
2305                 GP_2_4_FN,      GPSR2_4,
2306                 GP_2_3_FN,      GPSR2_3,
2307                 GP_2_2_FN,      GPSR2_2,
2308                 GP_2_1_FN,      GPSR2_1,
2309                 GP_2_0_FN,      GPSR2_0, }
2310         },
2311         { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2312                 0, 0,
2313                 0, 0,
2314                 0, 0,
2315                 0, 0,
2316                 0, 0,
2317                 0, 0,
2318                 0, 0,
2319                 0, 0,
2320                 0, 0,
2321                 0, 0,
2322                 0, 0,
2323                 0, 0,
2324                 0, 0,
2325                 0, 0,
2326                 0, 0,
2327                 GP_3_16_FN,     GPSR3_16,
2328                 GP_3_15_FN,     GPSR3_15,
2329                 GP_3_14_FN,     GPSR3_14,
2330                 GP_3_13_FN,     GPSR3_13,
2331                 GP_3_12_FN,     GPSR3_12,
2332                 GP_3_11_FN,     GPSR3_11,
2333                 GP_3_10_FN,     GPSR3_10,
2334                 GP_3_9_FN,      GPSR3_9,
2335                 GP_3_8_FN,      GPSR3_8,
2336                 GP_3_7_FN,      GPSR3_7,
2337                 GP_3_6_FN,      GPSR3_6,
2338                 GP_3_5_FN,      GPSR3_5,
2339                 GP_3_4_FN,      GPSR3_4,
2340                 GP_3_3_FN,      GPSR3_3,
2341                 GP_3_2_FN,      GPSR3_2,
2342                 GP_3_1_FN,      GPSR3_1,
2343                 GP_3_0_FN,      GPSR3_0, }
2344         },
2345         { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2346                 0, 0,
2347                 0, 0,
2348                 0, 0,
2349                 0, 0,
2350                 0, 0,
2351                 0, 0,
2352                 0, 0,
2353                 0, 0,
2354                 0, 0,
2355                 0, 0,
2356                 0, 0,
2357                 0, 0,
2358                 0, 0,
2359                 0, 0,
2360                 0, 0,
2361                 0, 0,
2362                 0, 0,
2363                 0, 0,
2364                 0, 0,
2365                 0, 0,
2366                 0, 0,
2367                 0, 0,
2368                 0, 0,
2369                 0, 0,
2370                 0, 0,
2371                 0, 0,
2372                 GP_4_5_FN,      GPSR4_5,
2373                 GP_4_4_FN,      GPSR4_4,
2374                 GP_4_3_FN,      GPSR4_3,
2375                 GP_4_2_FN,      GPSR4_2,
2376                 GP_4_1_FN,      GPSR4_1,
2377                 GP_4_0_FN,      GPSR4_0, }
2378         },
2379         { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2380                 0, 0,
2381                 0, 0,
2382                 0, 0,
2383                 0, 0,
2384                 0, 0,
2385                 0, 0,
2386                 0, 0,
2387                 0, 0,
2388                 0, 0,
2389                 0, 0,
2390                 0, 0,
2391                 0, 0,
2392                 0, 0,
2393                 0, 0,
2394                 0, 0,
2395                 0, 0,
2396                 0, 0,
2397                 GP_5_14_FN,     GPSR5_14,
2398                 GP_5_13_FN,     GPSR5_13,
2399                 GP_5_12_FN,     GPSR5_12,
2400                 GP_5_11_FN,     GPSR5_11,
2401                 GP_5_10_FN,     GPSR5_10,
2402                 GP_5_9_FN,      GPSR5_9,
2403                 GP_5_8_FN,      GPSR5_8,
2404                 GP_5_7_FN,      GPSR5_7,
2405                 GP_5_6_FN,      GPSR5_6,
2406                 GP_5_5_FN,      GPSR5_5,
2407                 GP_5_4_FN,      GPSR5_4,
2408                 GP_5_3_FN,      GPSR5_3,
2409                 GP_5_2_FN,      GPSR5_2,
2410                 GP_5_1_FN,      GPSR5_1,
2411                 GP_5_0_FN,      GPSR5_0, }
2412         },
2413 #undef F_
2414 #undef FM
2415
2416 #define F_(x, y)        x,
2417 #define FM(x)           FN_##x,
2418         { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2419                 IP0_31_28
2420                 IP0_27_24
2421                 IP0_23_20
2422                 IP0_19_16
2423                 IP0_15_12
2424                 IP0_11_8
2425                 IP0_7_4
2426                 IP0_3_0 }
2427         },
2428         { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2429                 IP1_31_28
2430                 IP1_27_24
2431                 IP1_23_20
2432                 IP1_19_16
2433                 IP1_15_12
2434                 IP1_11_8
2435                 IP1_7_4
2436                 IP1_3_0 }
2437         },
2438         { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2439                 IP2_31_28
2440                 IP2_27_24
2441                 IP2_23_20
2442                 IP2_19_16
2443                 IP2_15_12
2444                 IP2_11_8
2445                 IP2_7_4
2446                 IP2_3_0 }
2447         },
2448         { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2449                 IP3_31_28
2450                 IP3_27_24
2451                 IP3_23_20
2452                 IP3_19_16
2453                 IP3_15_12
2454                 IP3_11_8
2455                 IP3_7_4
2456                 IP3_3_0 }
2457         },
2458         { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2459                 IP4_31_28
2460                 IP4_27_24
2461                 IP4_23_20
2462                 IP4_19_16
2463                 IP4_15_12
2464                 IP4_11_8
2465                 IP4_7_4
2466                 IP4_3_0 }
2467         },
2468         { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2469                 IP5_31_28
2470                 IP5_27_24
2471                 IP5_23_20
2472                 IP5_19_16
2473                 IP5_15_12
2474                 IP5_11_8
2475                 IP5_7_4
2476                 IP5_3_0 }
2477         },
2478         { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2479                 IP6_31_28
2480                 IP6_27_24
2481                 IP6_23_20
2482                 IP6_19_16
2483                 IP6_15_12
2484                 IP6_11_8
2485                 IP6_7_4
2486                 IP6_3_0 }
2487         },
2488         { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2489                 IP7_31_28
2490                 IP7_27_24
2491                 IP7_23_20
2492                 IP7_19_16
2493                 IP7_15_12
2494                 IP7_11_8
2495                 IP7_7_4
2496                 IP7_3_0 }
2497         },
2498         { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2499                 IP8_31_28
2500                 IP8_27_24
2501                 IP8_23_20
2502                 IP8_19_16
2503                 IP8_15_12
2504                 IP8_11_8
2505                 IP8_7_4
2506                 IP8_3_0 }
2507         },
2508 #undef F_
2509 #undef FM
2510
2511 #define F_(x, y)        x,
2512 #define FM(x)           FN_##x,
2513         { PINMUX_CFG_REG("MOD_SEL0", 0xe6060500, 32, 1) {
2514                 /* RESERVED 31..12 */
2515                 0, 0,
2516                 0, 0,
2517                 0, 0,
2518                 0, 0,
2519                 0, 0,
2520                 0, 0,
2521                 0, 0,
2522                 0, 0,
2523                 0, 0,
2524                 0, 0,
2525                 0, 0,
2526                 0, 0,
2527                 0, 0,
2528                 0, 0,
2529                 0, 0,
2530                 0, 0,
2531                 0, 0,
2532                 0, 0,
2533                 0, 0,
2534                 0, 0,
2535                 MOD_SEL0_11
2536                 MOD_SEL0_10
2537                 MOD_SEL0_9
2538                 MOD_SEL0_8
2539                 MOD_SEL0_7
2540                 MOD_SEL0_6
2541                 MOD_SEL0_5
2542                 MOD_SEL0_4
2543                 MOD_SEL0_3
2544                 MOD_SEL0_2
2545                 MOD_SEL0_1
2546                 MOD_SEL0_0 }
2547         },
2548         { },
2549 };
2550
2551 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2552 {
2553         int bit = -EINVAL;
2554
2555         *pocctrl = 0xe6060384;
2556
2557         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2558                 bit = (pin & 0x1f) + 7;
2559
2560         return bit;
2561 }
2562
2563 static const struct sh_pfc_soc_operations pinmux_ops = {
2564         .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2565 };
2566
2567 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2568         .name = "r8a77970_pfc",
2569         .ops = &pinmux_ops,
2570         .unlock_reg = 0xe6060000, /* PMMR */
2571
2572         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2573
2574         .pins = pinmux_pins,
2575         .nr_pins = ARRAY_SIZE(pinmux_pins),
2576         .groups = pinmux_groups,
2577         .nr_groups = ARRAY_SIZE(pinmux_groups),
2578         .functions = pinmux_functions,
2579         .nr_functions = ARRAY_SIZE(pinmux_functions),
2580
2581         .cfg_regs = pinmux_config_regs,
2582
2583         .pinmux_data = pinmux_data,
2584         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2585 };