2 * Pin Control driver for SuperH Pin Function Controller.
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
8 * Copyright (C) 2017 Marek Vasut
10 * SPDX-License-Identifier: GPL-2.0
13 #define DRV_NAME "sh-pfc"
18 #include <dm/pinctrl.h>
20 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR;
38 struct sh_pfc_pin_config {
42 struct sh_pfc_pinctrl {
45 struct sh_pfc_pin_config *configs;
47 const char *func_prop_name;
48 const char *groups_prop_name;
49 const char *pins_prop_name;
52 struct sh_pfc_pin_range {
57 struct sh_pfc_pinctrl_priv {
59 struct sh_pfc_pinctrl pmx;
62 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
67 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
68 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
70 if (pin <= range->end)
71 return pin >= range->start
72 ? offset + pin - range->start : -1;
74 offset += range->end - range->start + 1;
80 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
82 if (enum_id < r->begin)
91 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
95 return readb(mapped_reg);
97 return readw(mapped_reg);
99 return readl(mapped_reg);
106 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
111 writeb(data, mapped_reg);
114 writew(data, mapped_reg);
117 writel(data, mapped_reg);
124 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
126 return sh_pfc_read_raw_reg(pfc->regs + reg, width);
129 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
131 void __iomem *unlock_reg =
132 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
134 if (pfc->info->unlock_reg)
135 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
137 sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
140 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
141 const struct pinmux_cfg_reg *crp,
143 void __iomem **mapped_regp, u32 *maskp,
148 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
150 if (crp->field_width) {
151 *maskp = (1 << crp->field_width) - 1;
152 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
154 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
155 *posp = crp->reg_width;
156 for (k = 0; k <= in_pos; k++)
157 *posp -= crp->var_field_width[k];
161 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
162 const struct pinmux_cfg_reg *crp,
163 unsigned int field, u32 value)
165 void __iomem *mapped_reg;
166 void __iomem *unlock_reg =
167 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
171 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
173 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
174 "r_width = %u, f_width = %u\n",
175 crp->reg, value, field, crp->reg_width, crp->field_width);
177 mask = ~(mask << pos);
178 value = value << pos;
180 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
184 if (pfc->info->unlock_reg)
185 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
187 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
190 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
191 const struct pinmux_cfg_reg **crp,
192 unsigned int *fieldp, u32 *valuep)
197 const struct pinmux_cfg_reg *config_reg =
198 pfc->info->cfg_regs + k;
199 unsigned int r_width = config_reg->reg_width;
200 unsigned int f_width = config_reg->field_width;
201 unsigned int curr_width;
202 unsigned int bit_pos;
203 unsigned int pos = 0;
209 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
214 curr_width = f_width;
216 curr_width = config_reg->var_field_width[m];
218 ncomb = 1 << curr_width;
219 for (n = 0; n < ncomb; n++) {
220 if (config_reg->enum_ids[pos + n] == enum_id) {
236 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
239 const u16 *data = pfc->info->pinmux_data;
243 *enum_idp = data[pos + 1];
247 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
248 if (data[k] == mark) {
249 *enum_idp = data[k + 1];
254 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
259 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
261 const struct pinmux_range *range;
264 switch (pinmux_type) {
265 case PINMUX_TYPE_GPIO:
266 case PINMUX_TYPE_FUNCTION:
270 case PINMUX_TYPE_OUTPUT:
271 range = &pfc->info->output;
274 case PINMUX_TYPE_INPUT:
275 range = &pfc->info->input;
282 /* Iterate over all the configuration fields we need to update. */
284 const struct pinmux_cfg_reg *cr;
291 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
298 /* Check if the configuration field selects a function. If it
299 * doesn't, skip the field if it's not applicable to the
300 * requested pinmux type.
302 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
304 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
305 /* Functions are allowed to modify all
309 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
310 /* Input/output types can only modify fields
311 * that correspond to their respective ranges.
313 in_range = sh_pfc_enum_in_range(enum_id, range);
316 * special case pass through for fixed
317 * input-only or output-only pins without
318 * function enum register association.
320 if (in_range && enum_id == range->force)
323 /* GPIOs are only allowed to modify function fields. */
329 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
333 sh_pfc_write_config_reg(pfc, cr, field, value);
339 const struct sh_pfc_bias_info *
340 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
341 unsigned int num, unsigned int pin)
345 for (i = 0; i < num; i++)
346 if (info[i].pin == pin)
349 printf("Pin %u is not in bias info list\n", pin);
354 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
356 struct sh_pfc_pin_range *range;
357 unsigned int nr_ranges;
360 if (pfc->info->pins[0].pin == (u16)-1) {
361 /* Pin number -1 denotes that the SoC doesn't report pin numbers
362 * in its pin arrays yet. Consider the pin numbers range as
363 * continuous and allocate a single range.
366 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
367 if (pfc->ranges == NULL)
370 pfc->ranges->start = 0;
371 pfc->ranges->end = pfc->info->nr_pins - 1;
372 pfc->nr_gpio_pins = pfc->info->nr_pins;
377 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
378 * be sorted by pin numbers, and pins without a GPIO port must come
381 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
382 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
386 pfc->nr_ranges = nr_ranges;
387 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
388 if (pfc->ranges == NULL)
392 range->start = pfc->info->pins[0].pin;
394 for (i = 1; i < pfc->info->nr_pins; ++i) {
395 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
398 range->end = pfc->info->pins[i-1].pin;
399 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
400 pfc->nr_gpio_pins = range->end + 1;
403 range->start = pfc->info->pins[i].pin;
406 range->end = pfc->info->pins[i-1].pin;
407 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
408 pfc->nr_gpio_pins = range->end + 1;
413 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
415 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
417 return priv->pfc.info->nr_pins;
420 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
423 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
425 return priv->pfc.info->pins[selector].name;
428 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
430 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
432 return priv->pfc.info->nr_groups;
435 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
438 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
440 return priv->pfc.info->groups[selector].name;
443 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
445 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
447 return priv->pfc.info->nr_functions;
450 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
453 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
455 return priv->pfc.info->functions[selector].name;
458 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
460 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
461 struct sh_pfc_pinctrl *pmx = &priv->pmx;
462 struct sh_pfc *pfc = &priv->pfc;
463 struct sh_pfc_pin_config *cfg;
464 const struct sh_pfc_pin *pin = NULL;
467 for (i = 1; i < pfc->info->nr_pins; i++) {
468 if (priv->pfc.info->pins[i].pin != pin_selector)
471 pin = &priv->pfc.info->pins[i];
478 idx = sh_pfc_get_pin_index(pfc, pin->pin);
479 cfg = &pmx->configs[idx];
481 if (cfg->type != PINMUX_TYPE_NONE)
484 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
487 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
488 unsigned func_selector)
490 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
491 struct sh_pfc_pinctrl *pmx = &priv->pmx;
492 struct sh_pfc *pfc = &priv->pfc;
493 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
494 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
495 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
497 if (cfg->type != PINMUX_TYPE_NONE)
500 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
503 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
504 unsigned func_selector)
506 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
507 struct sh_pfc_pinctrl *pmx = &priv->pmx;
508 struct sh_pfc *pfc = &priv->pfc;
509 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
513 for (i = 0; i < grp->nr_pins; ++i) {
514 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
515 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
517 if (cfg->type != PINMUX_TYPE_NONE) {
523 for (i = 0; i < grp->nr_pins; ++i) {
524 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
532 #if CONFIG_IS_ENABLED(PINCONF)
533 static const struct pinconf_param sh_pfc_pinconf_params[] = {
534 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
535 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
536 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
537 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
538 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
541 static void __iomem *
542 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
543 unsigned int *offset, unsigned int *size)
545 const struct pinmux_drive_reg_field *field;
546 const struct pinmux_drive_reg *reg;
549 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
550 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
551 field = ®->fields[i];
553 if (field->size && field->pin == pin) {
554 *offset = field->offset;
557 return (void __iomem *)(uintptr_t)reg->reg;
565 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
566 unsigned int pin, u16 strength)
572 void __iomem *unlock_reg =
573 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
576 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
580 step = size == 2 ? 6 : 3;
582 if (strength < step || strength > 24)
585 /* Convert the value from mA based on a full drive strength value of
586 * 24mA. We can make the full value configurable later if needed.
588 strength = strength / step - 1;
590 val = sh_pfc_read_raw_reg(reg, 32);
591 val &= ~GENMASK(offset + size - 1, offset);
592 val |= strength << offset;
595 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
597 sh_pfc_write_raw_reg(reg, 32, val);
602 /* Check whether the requested parameter is supported for a pin. */
603 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
606 int idx = sh_pfc_get_pin_index(pfc, _pin);
607 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
610 case PIN_CONFIG_BIAS_DISABLE:
611 return pin->configs &
612 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
614 case PIN_CONFIG_BIAS_PULL_UP:
615 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
617 case PIN_CONFIG_BIAS_PULL_DOWN:
618 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
620 case PIN_CONFIG_DRIVE_STRENGTH:
621 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
623 case PIN_CONFIG_POWER_SOURCE:
624 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
631 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
632 unsigned int param, unsigned int arg)
634 struct sh_pfc *pfc = pmx->pfc;
635 void __iomem *pocctrl;
636 void __iomem *unlock_reg =
637 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
641 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
645 case PIN_CONFIG_BIAS_PULL_UP:
646 case PIN_CONFIG_BIAS_PULL_DOWN:
647 case PIN_CONFIG_BIAS_DISABLE:
648 if (!pfc->info->ops || !pfc->info->ops->set_bias)
651 pfc->info->ops->set_bias(pfc, _pin, param);
655 case PIN_CONFIG_DRIVE_STRENGTH:
656 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
662 case PIN_CONFIG_POWER_SOURCE:
663 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
666 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
668 printf("invalid pin %#x", _pin);
672 if (arg != 1800 && arg != 3300)
675 pocctrl = (void __iomem *)(uintptr_t)addr;
677 val = sh_pfc_read_raw_reg(pocctrl, 32);
684 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
686 sh_pfc_write_raw_reg(pocctrl, 32, val);
697 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
698 unsigned int pin_selector,
699 unsigned int param, unsigned int arg)
701 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
702 struct sh_pfc_pinctrl *pmx = &priv->pmx;
703 struct sh_pfc *pfc = &priv->pfc;
704 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
706 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
711 static int sh_pfc_pinconf_group_set(struct udevice *dev,
712 unsigned int group_selector,
713 unsigned int param, unsigned int arg)
715 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
716 struct sh_pfc_pinctrl *pmx = &priv->pmx;
717 struct sh_pfc *pfc = &priv->pfc;
718 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
721 for (i = 0; i < grp->nr_pins; i++)
722 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
728 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
729 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
730 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
731 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
732 .get_group_name = sh_pfc_pinctrl_get_group_name,
733 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
734 .get_function_name = sh_pfc_pinctrl_get_function_name,
736 #if CONFIG_IS_ENABLED(PINCONF)
737 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
738 .pinconf_params = sh_pfc_pinconf_params,
739 .pinconf_set = sh_pfc_pinconf_pin_set,
740 .pinconf_group_set = sh_pfc_pinconf_group_set,
742 .pinmux_set = sh_pfc_pinctrl_pin_set,
743 .pinmux_group_set = sh_pfc_pinctrl_group_set,
744 .set_state = pinctrl_generic_set_state,
747 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
751 /* Allocate and initialize the pins and configs arrays. */
752 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
754 if (unlikely(!pmx->configs))
757 for (i = 0; i < pfc->info->nr_pins; ++i) {
758 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
759 cfg->type = PINMUX_TYPE_NONE;
766 static int sh_pfc_pinctrl_probe(struct udevice *dev)
768 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
769 enum sh_pfc_model model = dev_get_driver_data(dev);
772 base = devfdt_get_addr(dev);
773 if (base == FDT_ADDR_T_NONE)
776 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
780 #ifdef CONFIG_PINCTRL_PFC_R8A7790
781 if (model == SH_PFC_R8A7790)
782 priv->pfc.info = &r8a7790_pinmux_info;
784 #ifdef CONFIG_PINCTRL_PFC_R8A7791
785 if (model == SH_PFC_R8A7791)
786 priv->pfc.info = &r8a7791_pinmux_info;
788 #ifdef CONFIG_PINCTRL_PFC_R8A7792
789 if (model == SH_PFC_R8A7792)
790 priv->pfc.info = &r8a7792_pinmux_info;
792 #ifdef CONFIG_PINCTRL_PFC_R8A7793
793 if (model == SH_PFC_R8A7793)
794 priv->pfc.info = &r8a7793_pinmux_info;
796 #ifdef CONFIG_PINCTRL_PFC_R8A7794
797 if (model == SH_PFC_R8A7794)
798 priv->pfc.info = &r8a7794_pinmux_info;
800 #ifdef CONFIG_PINCTRL_PFC_R8A7795
801 if (model == SH_PFC_R8A7795)
802 priv->pfc.info = &r8a7795_pinmux_info;
804 #ifdef CONFIG_PINCTRL_PFC_R8A7796
805 if (model == SH_PFC_R8A7796)
806 priv->pfc.info = &r8a7796_pinmux_info;
808 #ifdef CONFIG_PINCTRL_PFC_R8A77970
809 if (model == SH_PFC_R8A77970)
810 priv->pfc.info = &r8a77970_pinmux_info;
812 #ifdef CONFIG_PINCTRL_PFC_R8A77995
813 if (model == SH_PFC_R8A77995)
814 priv->pfc.info = &r8a77995_pinmux_info;
817 priv->pmx.pfc = &priv->pfc;
818 sh_pfc_init_ranges(&priv->pfc);
819 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
824 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
825 #ifdef CONFIG_PINCTRL_PFC_R8A7790
827 .compatible = "renesas,pfc-r8a7790",
828 .data = SH_PFC_R8A7790,
831 #ifdef CONFIG_PINCTRL_PFC_R8A7791
833 .compatible = "renesas,pfc-r8a7791",
834 .data = SH_PFC_R8A7791,
837 #ifdef CONFIG_PINCTRL_PFC_R8A7792
839 .compatible = "renesas,pfc-r8a7792",
840 .data = SH_PFC_R8A7792,
843 #ifdef CONFIG_PINCTRL_PFC_R8A7793
845 .compatible = "renesas,pfc-r8a7793",
846 .data = SH_PFC_R8A7793,
849 #ifdef CONFIG_PINCTRL_PFC_R8A7794
851 .compatible = "renesas,pfc-r8a7794",
852 .data = SH_PFC_R8A7794,
855 #ifdef CONFIG_PINCTRL_PFC_R8A7795
857 .compatible = "renesas,pfc-r8a7795",
858 .data = SH_PFC_R8A7795,
861 #ifdef CONFIG_PINCTRL_PFC_R8A7796
863 .compatible = "renesas,pfc-r8a7796",
864 .data = SH_PFC_R8A7796,
866 .compatible = "renesas,pfc-r8a77965",
867 .data = SH_PFC_R8A7796,
870 #ifdef CONFIG_PINCTRL_PFC_R8A77970
872 .compatible = "renesas,pfc-r8a77970",
873 .data = SH_PFC_R8A77970,
876 #ifdef CONFIG_PINCTRL_PFC_R8A77995
878 .compatible = "renesas,pfc-r8a77995",
879 .data = SH_PFC_R8A77995,
885 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
886 .name = "sh_pfc_pinctrl",
887 .id = UCLASS_PINCTRL,
888 .of_match = sh_pfc_pinctrl_ids,
889 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
890 .ops = &sh_pfc_pinctrl_ops,
891 .probe = sh_pfc_pinctrl_probe,