git.sur5r.net Git - u-boot/blob - drivers/pinctrl/renesas/pfc.c

   1 /*
   2  * Pin Control driver for SuperH Pin Function Controller.
   3  *
   4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  * Copyright (C) 2009 - 2012 Paul Mundt
   8  * Copyright (C) 2017 Marek Vasut
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0
  11  */
  12
  13 #define DRV_NAME "sh-pfc"
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/io.h>
  20 #include <linux/sizes.h>
  21
  22 #include "sh_pfc.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sh_pfc_model {
  27         SH_PFC_R8A7795 = 0,
  28         SH_PFC_R8A7796,
  29 };
  30
  31 struct sh_pfc_pin_config {
  32         u32 type;
  33 };
  34
  35 struct sh_pfc_pinctrl {
  36         struct sh_pfc *pfc;
  37
  38         struct sh_pfc_pin_config *configs;
  39
  40         const char *func_prop_name;
  41         const char *groups_prop_name;
  42         const char *pins_prop_name;
  43 };
  44
  45 struct sh_pfc_pin_range {
  46         u16 start;
  47         u16 end;
  48 };
  49
  50 struct sh_pfc_pinctrl_priv {
  51         struct sh_pfc                   pfc;
  52         struct sh_pfc_pinctrl           pmx;
  53 };
  54
  55 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  56 {
  57         unsigned int offset;
  58         unsigned int i;
  59
  60         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  61                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  62
  63                 if (pin <= range->end)
  64                         return pin >= range->start
  65                              ? offset + pin - range->start : -1;
  66
  67                 offset += range->end - range->start + 1;
  68         }
  69
  70         return -EINVAL;
  71 }
  72
  73 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  74 {
  75         if (enum_id < r->begin)
  76                 return 0;
  77
  78         if (enum_id > r->end)
  79                 return 0;
  80
  81         return 1;
  82 }
  83
  84 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  85 {
  86         switch (reg_width) {
  87         case 8:
  88                 return readb(mapped_reg);
  89         case 16:
  90                 return readw(mapped_reg);
  91         case 32:
  92                 return readl(mapped_reg);
  93         }
  94
  95         BUG();
  96         return 0;
  97 }
  98
  99 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 100                           u32 data)
 101 {
 102         switch (reg_width) {
 103         case 8:
 104                 writeb(data, mapped_reg);
 105                 return;
 106         case 16:
 107                 writew(data, mapped_reg);
 108                 return;
 109         case 32:
 110                 writel(data, mapped_reg);
 111                 return;
 112         }
 113
 114         BUG();
 115 }
 116
 117 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
 118 {
 119         return sh_pfc_read_raw_reg(pfc->regs + reg, width);
 120 }
 121
 122 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
 123 {
 124         void __iomem *unlock_reg =
 125                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 126
 127         if (pfc->info->unlock_reg)
 128                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 129
 130         sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
 131 }
 132
 133 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 134                                      const struct pinmux_cfg_reg *crp,
 135                                      unsigned int in_pos,
 136                                      void __iomem **mapped_regp, u32 *maskp,
 137                                      unsigned int *posp)
 138 {
 139         unsigned int k;
 140
 141         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 142
 143         if (crp->field_width) {
 144                 *maskp = (1 << crp->field_width) - 1;
 145                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 146         } else {
 147                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 148                 *posp = crp->reg_width;
 149                 for (k = 0; k <= in_pos; k++)
 150                         *posp -= crp->var_field_width[k];
 151         }
 152 }
 153
 154 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 155                                     const struct pinmux_cfg_reg *crp,
 156                                     unsigned int field, u32 value)
 157 {
 158         void __iomem *mapped_reg;
 159         void __iomem *unlock_reg =
 160                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 161         unsigned int pos;
 162         u32 mask, data;
 163
 164         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 165
 166         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 167                 "r_width = %u, f_width = %u\n",
 168                 crp->reg, value, field, crp->reg_width, crp->field_width);
 169
 170         mask = ~(mask << pos);
 171         value = value << pos;
 172
 173         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 174         data &= mask;
 175         data |= value;
 176
 177         if (pfc->info->unlock_reg)
 178                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 179
 180         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 181 }
 182
 183 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 184                                  const struct pinmux_cfg_reg **crp,
 185                                  unsigned int *fieldp, u32 *valuep)
 186 {
 187         unsigned int k = 0;
 188
 189         while (1) {
 190                 const struct pinmux_cfg_reg *config_reg =
 191                         pfc->info->cfg_regs + k;
 192                 unsigned int r_width = config_reg->reg_width;
 193                 unsigned int f_width = config_reg->field_width;
 194                 unsigned int curr_width;
 195                 unsigned int bit_pos;
 196                 unsigned int pos = 0;
 197                 unsigned int m = 0;
 198
 199                 if (!r_width)
 200                         break;
 201
 202                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 203                         u32 ncomb;
 204                         u32 n;
 205
 206                         if (f_width)
 207                                 curr_width = f_width;
 208                         else
 209                                 curr_width = config_reg->var_field_width[m];
 210
 211                         ncomb = 1 << curr_width;
 212                         for (n = 0; n < ncomb; n++) {
 213                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 214                                         *crp = config_reg;
 215                                         *fieldp = m;
 216                                         *valuep = n;
 217                                         return 0;
 218                                 }
 219                         }
 220                         pos += ncomb;
 221                         m++;
 222                 }
 223                 k++;
 224         }
 225
 226         return -EINVAL;
 227 }
 228
 229 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 230                               u16 *enum_idp)
 231 {
 232         const u16 *data = pfc->info->pinmux_data;
 233         unsigned int k;
 234
 235         if (pos) {
 236                 *enum_idp = data[pos + 1];
 237                 return pos + 1;
 238         }
 239
 240         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 241                 if (data[k] == mark) {
 242                         *enum_idp = data[k + 1];
 243                         return k + 1;
 244                 }
 245         }
 246
 247         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 248                 mark);
 249         return -EINVAL;
 250 }
 251
 252 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 253 {
 254         const struct pinmux_range *range;
 255         int pos = 0;
 256
 257         switch (pinmux_type) {
 258         case PINMUX_TYPE_GPIO:
 259         case PINMUX_TYPE_FUNCTION:
 260                 range = NULL;
 261                 break;
 262
 263         case PINMUX_TYPE_OUTPUT:
 264                 range = &pfc->info->output;
 265                 break;
 266
 267         case PINMUX_TYPE_INPUT:
 268                 range = &pfc->info->input;
 269                 break;
 270
 271         default:
 272                 return -EINVAL;
 273         }
 274
 275         /* Iterate over all the configuration fields we need to update. */
 276         while (1) {
 277                 const struct pinmux_cfg_reg *cr;
 278                 unsigned int field;
 279                 u16 enum_id;
 280                 u32 value;
 281                 int in_range;
 282                 int ret;
 283
 284                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 285                 if (pos < 0)
 286                         return pos;
 287
 288                 if (!enum_id)
 289                         break;
 290
 291                 /* Check if the configuration field selects a function. If it
 292                  * doesn't, skip the field if it's not applicable to the
 293                  * requested pinmux type.
 294                  */
 295                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 296                 if (!in_range) {
 297                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 298                                 /* Functions are allowed to modify all
 299                                  * fields.
 300                                  */
 301                                 in_range = 1;
 302                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 303                                 /* Input/output types can only modify fields
 304                                  * that correspond to their respective ranges.
 305                                  */
 306                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 307
 308                                 /*
 309                                  * special case pass through for fixed
 310                                  * input-only or output-only pins without
 311                                  * function enum register association.
 312                                  */
 313                                 if (in_range && enum_id == range->force)
 314                                         continue;
 315                         }
 316                         /* GPIOs are only allowed to modify function fields. */
 317                 }
 318
 319                 if (!in_range)
 320                         continue;
 321
 322                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 323                 if (ret < 0)
 324                         return ret;
 325
 326                 sh_pfc_write_config_reg(pfc, cr, field, value);
 327         }
 328
 329         return 0;
 330 }
 331
 332 const struct sh_pfc_bias_info *
 333 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
 334                         unsigned int num, unsigned int pin)
 335 {
 336         unsigned int i;
 337
 338         for (i = 0; i < num; i++)
 339                 if (info[i].pin == pin)
 340                         return &info[i];
 341
 342         printf("Pin %u is not in bias info list\n", pin);
 343
 344         return NULL;
 345 }
 346
 347 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 348 {
 349         struct sh_pfc_pin_range *range;
 350         unsigned int nr_ranges;
 351         unsigned int i;
 352
 353         if (pfc->info->pins[0].pin == (u16)-1) {
 354                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 355                  * in its pin arrays yet. Consider the pin numbers range as
 356                  * continuous and allocate a single range.
 357                  */
 358                 pfc->nr_ranges = 1;
 359                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 360                 if (pfc->ranges == NULL)
 361                         return -ENOMEM;
 362
 363                 pfc->ranges->start = 0;
 364                 pfc->ranges->end = pfc->info->nr_pins - 1;
 365                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 366
 367                 return 0;
 368         }
 369
 370         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 371          * be sorted by pin numbers, and pins without a GPIO port must come
 372          * last.
 373          */
 374         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 375                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 376                         nr_ranges++;
 377         }
 378
 379         pfc->nr_ranges = nr_ranges;
 380         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 381         if (pfc->ranges == NULL)
 382                 return -ENOMEM;
 383
 384         range = pfc->ranges;
 385         range->start = pfc->info->pins[0].pin;
 386
 387         for (i = 1; i < pfc->info->nr_pins; ++i) {
 388                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 389                         continue;
 390
 391                 range->end = pfc->info->pins[i-1].pin;
 392                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 393                         pfc->nr_gpio_pins = range->end + 1;
 394
 395                 range++;
 396                 range->start = pfc->info->pins[i].pin;
 397         }
 398
 399         range->end = pfc->info->pins[i-1].pin;
 400         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 401                 pfc->nr_gpio_pins = range->end + 1;
 402
 403         return 0;
 404 }
 405
 406 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 407 {
 408         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 409
 410         return priv->pfc.info->nr_pins;
 411 }
 412
 413 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 414                                                   unsigned selector)
 415 {
 416         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 417
 418         return priv->pfc.info->pins[selector].name;
 419 }
 420
 421 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 422 {
 423         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 424
 425         return priv->pfc.info->nr_groups;
 426 }
 427
 428 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 429                                                   unsigned selector)
 430 {
 431         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 432
 433         return priv->pfc.info->groups[selector].name;
 434 }
 435
 436 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 437 {
 438         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 439
 440         return priv->pfc.info->nr_functions;
 441 }
 442
 443 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 444                                                   unsigned selector)
 445 {
 446         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 447
 448         return priv->pfc.info->functions[selector].name;
 449 }
 450
 451 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
 452 {
 453         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 454         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 455         struct sh_pfc *pfc = &priv->pfc;
 456         struct sh_pfc_pin_config *cfg;
 457         const struct sh_pfc_pin *pin = NULL;
 458         int i, idx;
 459
 460         for (i = 1; i < pfc->info->nr_pins; i++) {
 461                 if (priv->pfc.info->pins[i].pin != pin_selector)
 462                         continue;
 463
 464                 pin = &priv->pfc.info->pins[i];
 465                 break;
 466         }
 467
 468         if (!pin)
 469                 return -EINVAL;
 470
 471         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 472         cfg = &pmx->configs[idx];
 473
 474         if (cfg->type != PINMUX_TYPE_NONE)
 475                 return -EBUSY;
 476
 477         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 478 }
 479
 480 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 481                                   unsigned func_selector)
 482 {
 483         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 484         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 485         struct sh_pfc *pfc = &priv->pfc;
 486         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 487         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 488         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 489
 490         if (cfg->type != PINMUX_TYPE_NONE)
 491                 return -EBUSY;
 492
 493         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 494 }
 495
 496 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 497                                      unsigned func_selector)
 498 {
 499         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 500         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 501         struct sh_pfc *pfc = &priv->pfc;
 502         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 503         unsigned int i;
 504         int ret = 0;
 505
 506         for (i = 0; i < grp->nr_pins; ++i) {
 507                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 508                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 509
 510                 if (cfg->type != PINMUX_TYPE_NONE) {
 511                         ret = -EBUSY;
 512                         goto done;
 513                 }
 514         }
 515
 516         for (i = 0; i < grp->nr_pins; ++i) {
 517                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 518                 if (ret < 0)
 519                         break;
 520         }
 521
 522 done:
 523         return ret;
 524 }
 525 #if CONFIG_IS_ENABLED(PINCONF)
 526 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 527         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 528         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 529         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 530         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 531         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 532 };
 533
 534 static void __iomem *
 535 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 536                                        unsigned int *offset, unsigned int *size)
 537 {
 538         const struct pinmux_drive_reg_field *field;
 539         const struct pinmux_drive_reg *reg;
 540         unsigned int i;
 541
 542         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 543                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 544                         field = &reg->fields[i];
 545
 546                         if (field->size && field->pin == pin) {
 547                                 *offset = field->offset;
 548                                 *size = field->size;
 549
 550                                 return (void __iomem *)(uintptr_t)reg->reg;
 551                         }
 552                 }
 553         }
 554
 555         return NULL;
 556 }
 557
 558 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 559                                              unsigned int pin, u16 strength)
 560 {
 561         unsigned int offset;
 562         unsigned int size;
 563         unsigned int step;
 564         void __iomem *reg;
 565         void __iomem *unlock_reg =
 566                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 567         u32 val;
 568
 569         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 570         if (!reg)
 571                 return -EINVAL;
 572
 573         step = size == 2 ? 6 : 3;
 574
 575         if (strength < step || strength > 24)
 576                 return -EINVAL;
 577
 578         /* Convert the value from mA based on a full drive strength value of
 579          * 24mA. We can make the full value configurable later if needed.
 580          */
 581         strength = strength / step - 1;
 582
 583         val = sh_pfc_read_raw_reg(reg, 32);
 584         val &= ~GENMASK(offset + size - 1, offset);
 585         val |= strength << offset;
 586
 587         if (unlock_reg)
 588                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 589
 590         sh_pfc_write_raw_reg(reg, 32, val);
 591
 592         return 0;
 593 }
 594
 595 /* Check whether the requested parameter is supported for a pin. */
 596 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 597                                     unsigned int param)
 598 {
 599         int idx = sh_pfc_get_pin_index(pfc, _pin);
 600         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 601
 602         switch (param) {
 603         case PIN_CONFIG_BIAS_DISABLE:
 604                 return pin->configs &
 605                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 606
 607         case PIN_CONFIG_BIAS_PULL_UP:
 608                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 609
 610         case PIN_CONFIG_BIAS_PULL_DOWN:
 611                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 612
 613         case PIN_CONFIG_DRIVE_STRENGTH:
 614                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 615
 616         case PIN_CONFIG_POWER_SOURCE:
 617                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 618
 619         default:
 620                 return false;
 621         }
 622 }
 623
 624 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 625                               unsigned int param, unsigned int arg)
 626 {
 627         struct sh_pfc *pfc = pmx->pfc;
 628         void __iomem *pocctrl;
 629         void __iomem *unlock_reg =
 630                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 631         u32 addr, val;
 632         int bit, ret;
 633
 634         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 635                 return -ENOTSUPP;
 636
 637         switch (param) {
 638         case PIN_CONFIG_BIAS_PULL_UP:
 639         case PIN_CONFIG_BIAS_PULL_DOWN:
 640         case PIN_CONFIG_BIAS_DISABLE:
 641                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 642                         return -ENOTSUPP;
 643
 644                 pfc->info->ops->set_bias(pfc, _pin, param);
 645
 646                 break;
 647
 648         case PIN_CONFIG_DRIVE_STRENGTH:
 649                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 650                 if (ret < 0)
 651                         return ret;
 652
 653                 break;
 654
 655         case PIN_CONFIG_POWER_SOURCE:
 656                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 657                         return -ENOTSUPP;
 658
 659                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 660                 if (bit < 0) {
 661                         printf("invalid pin %#x", _pin);
 662                         return bit;
 663                 }
 664
 665                 if (arg != 1800 && arg != 3300)
 666                         return -EINVAL;
 667
 668                 pocctrl = (void __iomem *)(uintptr_t)addr;
 669
 670                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 671                 if (arg == 3300)
 672                         val |= BIT(bit);
 673                 else
 674                         val &= ~BIT(bit);
 675
 676                 if (unlock_reg)
 677                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 678
 679                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 680
 681                 break;
 682
 683         default:
 684                 return -ENOTSUPP;
 685         }
 686
 687         return 0;
 688 }
 689
 690 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 691                                   unsigned int pin_selector,
 692                                   unsigned int param, unsigned int arg)
 693 {
 694         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 695         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 696         struct sh_pfc *pfc = &priv->pfc;
 697         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 698
 699         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 700
 701         return 0;
 702 }
 703
 704 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 705                                       unsigned int group_selector,
 706                                       unsigned int param, unsigned int arg)
 707 {
 708         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 709         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 710         struct sh_pfc *pfc = &priv->pfc;
 711         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 712         unsigned int i;
 713
 714         for (i = 0; i < grp->nr_pins; i++)
 715                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 716
 717         return 0;
 718 }
 719 #endif
 720
 721 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 722         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 723         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 724         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 725         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 726         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 727         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 728
 729 #if CONFIG_IS_ENABLED(PINCONF)
 730         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 731         .pinconf_params         = sh_pfc_pinconf_params,
 732         .pinconf_set            = sh_pfc_pinconf_pin_set,
 733         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 734 #endif
 735         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 736         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 737         .set_state              = pinctrl_generic_set_state,
 738 };
 739
 740 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 741 {
 742         unsigned int i;
 743
 744         /* Allocate and initialize the pins and configs arrays. */
 745         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 746                                     GFP_KERNEL);
 747         if (unlikely(!pmx->configs))
 748                 return -ENOMEM;
 749
 750         for (i = 0; i < pfc->info->nr_pins; ++i) {
 751                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 752                 cfg->type = PINMUX_TYPE_NONE;
 753         }
 754
 755         return 0;
 756 }
 757
 758
 759 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 760 {
 761         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 762         enum sh_pfc_model model = dev_get_driver_data(dev);
 763         fdt_addr_t base;
 764
 765         base = devfdt_get_addr(dev);
 766         if (base == FDT_ADDR_T_NONE)
 767                 return -EINVAL;
 768
 769         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 770         if (!priv->pfc.regs)
 771                 return -ENOMEM;
 772
 773 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 774         if (model == SH_PFC_R8A7795)
 775                 priv->pfc.info = &r8a7795_pinmux_info;
 776 #endif
 777 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 778         if (model == SH_PFC_R8A7796)
 779                 priv->pfc.info = &r8a7796_pinmux_info;
 780 #endif
 781
 782         priv->pmx.pfc = &priv->pfc;
 783         sh_pfc_init_ranges(&priv->pfc);
 784         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 785
 786         return 0;
 787 }
 788
 789 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 790 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 791         {
 792                 .compatible = "renesas,pfc-r8a7795",
 793                 .data = SH_PFC_R8A7795,
 794         },
 795 #endif
 796 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 797         {
 798                 .compatible = "renesas,pfc-r8a7796",
 799                 .data = SH_PFC_R8A7796,
 800         },
 801 #endif
 802         { },
 803 };
 804
 805 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 806         .name           = "sh_pfc_pinctrl",
 807         .id             = UCLASS_PINCTRL,
 808         .of_match       = sh_pfc_pinctrl_ids,
 809         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 810         .ops            = &sh_pfc_pinctrl_ops,
 811         .probe          = sh_pfc_pinctrl_probe,
 812 };