2 * Pin Control driver for SuperH Pin Function Controller.
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
8 * Copyright (C) 2017 Marek Vasut
10 * SPDX-License-Identifier: GPL-2.0
13 #define DRV_NAME "sh-pfc"
18 #include <dm/pinctrl.h>
20 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR;
33 struct sh_pfc_pin_config {
37 struct sh_pfc_pinctrl {
40 struct sh_pfc_pin_config *configs;
42 const char *func_prop_name;
43 const char *groups_prop_name;
44 const char *pins_prop_name;
47 struct sh_pfc_pin_range {
52 struct sh_pfc_pinctrl_priv {
54 struct sh_pfc_pinctrl pmx;
57 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
62 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
63 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
65 if (pin <= range->end)
66 return pin >= range->start
67 ? offset + pin - range->start : -1;
69 offset += range->end - range->start + 1;
75 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
77 if (enum_id < r->begin)
86 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
90 return readb(mapped_reg);
92 return readw(mapped_reg);
94 return readl(mapped_reg);
101 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
106 writeb(data, mapped_reg);
109 writew(data, mapped_reg);
112 writel(data, mapped_reg);
119 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
121 return sh_pfc_read_raw_reg(pfc->regs + reg, width);
124 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
126 void __iomem *unlock_reg =
127 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
129 if (pfc->info->unlock_reg)
130 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
132 sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
135 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
136 const struct pinmux_cfg_reg *crp,
138 void __iomem **mapped_regp, u32 *maskp,
143 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
145 if (crp->field_width) {
146 *maskp = (1 << crp->field_width) - 1;
147 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
149 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
150 *posp = crp->reg_width;
151 for (k = 0; k <= in_pos; k++)
152 *posp -= crp->var_field_width[k];
156 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
157 const struct pinmux_cfg_reg *crp,
158 unsigned int field, u32 value)
160 void __iomem *mapped_reg;
161 void __iomem *unlock_reg =
162 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
166 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
168 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
169 "r_width = %u, f_width = %u\n",
170 crp->reg, value, field, crp->reg_width, crp->field_width);
172 mask = ~(mask << pos);
173 value = value << pos;
175 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
179 if (pfc->info->unlock_reg)
180 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
182 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
185 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
186 const struct pinmux_cfg_reg **crp,
187 unsigned int *fieldp, u32 *valuep)
192 const struct pinmux_cfg_reg *config_reg =
193 pfc->info->cfg_regs + k;
194 unsigned int r_width = config_reg->reg_width;
195 unsigned int f_width = config_reg->field_width;
196 unsigned int curr_width;
197 unsigned int bit_pos;
198 unsigned int pos = 0;
204 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
209 curr_width = f_width;
211 curr_width = config_reg->var_field_width[m];
213 ncomb = 1 << curr_width;
214 for (n = 0; n < ncomb; n++) {
215 if (config_reg->enum_ids[pos + n] == enum_id) {
231 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
234 const u16 *data = pfc->info->pinmux_data;
238 *enum_idp = data[pos + 1];
242 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
243 if (data[k] == mark) {
244 *enum_idp = data[k + 1];
249 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
254 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
256 const struct pinmux_range *range;
259 switch (pinmux_type) {
260 case PINMUX_TYPE_GPIO:
261 case PINMUX_TYPE_FUNCTION:
265 case PINMUX_TYPE_OUTPUT:
266 range = &pfc->info->output;
269 case PINMUX_TYPE_INPUT:
270 range = &pfc->info->input;
277 /* Iterate over all the configuration fields we need to update. */
279 const struct pinmux_cfg_reg *cr;
286 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
293 /* Check if the configuration field selects a function. If it
294 * doesn't, skip the field if it's not applicable to the
295 * requested pinmux type.
297 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
299 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
300 /* Functions are allowed to modify all
304 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
305 /* Input/output types can only modify fields
306 * that correspond to their respective ranges.
308 in_range = sh_pfc_enum_in_range(enum_id, range);
311 * special case pass through for fixed
312 * input-only or output-only pins without
313 * function enum register association.
315 if (in_range && enum_id == range->force)
318 /* GPIOs are only allowed to modify function fields. */
324 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
328 sh_pfc_write_config_reg(pfc, cr, field, value);
334 const struct sh_pfc_bias_info *
335 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
336 unsigned int num, unsigned int pin)
340 for (i = 0; i < num; i++)
341 if (info[i].pin == pin)
344 printf("Pin %u is not in bias info list\n", pin);
349 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
351 struct sh_pfc_pin_range *range;
352 unsigned int nr_ranges;
355 if (pfc->info->pins[0].pin == (u16)-1) {
356 /* Pin number -1 denotes that the SoC doesn't report pin numbers
357 * in its pin arrays yet. Consider the pin numbers range as
358 * continuous and allocate a single range.
361 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
362 if (pfc->ranges == NULL)
365 pfc->ranges->start = 0;
366 pfc->ranges->end = pfc->info->nr_pins - 1;
367 pfc->nr_gpio_pins = pfc->info->nr_pins;
372 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
373 * be sorted by pin numbers, and pins without a GPIO port must come
376 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
377 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
381 pfc->nr_ranges = nr_ranges;
382 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
383 if (pfc->ranges == NULL)
387 range->start = pfc->info->pins[0].pin;
389 for (i = 1; i < pfc->info->nr_pins; ++i) {
390 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
393 range->end = pfc->info->pins[i-1].pin;
394 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
395 pfc->nr_gpio_pins = range->end + 1;
398 range->start = pfc->info->pins[i].pin;
401 range->end = pfc->info->pins[i-1].pin;
402 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
403 pfc->nr_gpio_pins = range->end + 1;
408 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
410 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
412 return priv->pfc.info->nr_pins;
415 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
418 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
420 return priv->pfc.info->pins[selector].name;
423 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
425 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
427 return priv->pfc.info->nr_groups;
430 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
433 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
435 return priv->pfc.info->groups[selector].name;
438 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
440 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
442 return priv->pfc.info->nr_functions;
445 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
448 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
450 return priv->pfc.info->functions[selector].name;
453 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
455 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
456 struct sh_pfc_pinctrl *pmx = &priv->pmx;
457 struct sh_pfc *pfc = &priv->pfc;
458 struct sh_pfc_pin_config *cfg;
459 const struct sh_pfc_pin *pin = NULL;
462 for (i = 1; i < pfc->info->nr_pins; i++) {
463 if (priv->pfc.info->pins[i].pin != pin_selector)
466 pin = &priv->pfc.info->pins[i];
473 idx = sh_pfc_get_pin_index(pfc, pin->pin);
474 cfg = &pmx->configs[idx];
476 if (cfg->type != PINMUX_TYPE_NONE)
479 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
482 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
483 unsigned func_selector)
485 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
486 struct sh_pfc_pinctrl *pmx = &priv->pmx;
487 struct sh_pfc *pfc = &priv->pfc;
488 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
489 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
490 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
492 if (cfg->type != PINMUX_TYPE_NONE)
495 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
498 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
499 unsigned func_selector)
501 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
502 struct sh_pfc_pinctrl *pmx = &priv->pmx;
503 struct sh_pfc *pfc = &priv->pfc;
504 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
508 for (i = 0; i < grp->nr_pins; ++i) {
509 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
510 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
512 if (cfg->type != PINMUX_TYPE_NONE) {
518 for (i = 0; i < grp->nr_pins; ++i) {
519 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
527 #if CONFIG_IS_ENABLED(PINCONF)
528 static const struct pinconf_param sh_pfc_pinconf_params[] = {
529 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
530 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
531 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
532 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
533 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
536 static void __iomem *
537 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
538 unsigned int *offset, unsigned int *size)
540 const struct pinmux_drive_reg_field *field;
541 const struct pinmux_drive_reg *reg;
544 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
545 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
546 field = ®->fields[i];
548 if (field->size && field->pin == pin) {
549 *offset = field->offset;
552 return (void __iomem *)(uintptr_t)reg->reg;
560 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
561 unsigned int pin, u16 strength)
567 void __iomem *unlock_reg =
568 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
571 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
575 step = size == 2 ? 6 : 3;
577 if (strength < step || strength > 24)
580 /* Convert the value from mA based on a full drive strength value of
581 * 24mA. We can make the full value configurable later if needed.
583 strength = strength / step - 1;
585 val = sh_pfc_read_raw_reg(reg, 32);
586 val &= ~GENMASK(offset + size - 1, offset);
587 val |= strength << offset;
590 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
592 sh_pfc_write_raw_reg(reg, 32, val);
597 /* Check whether the requested parameter is supported for a pin. */
598 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
601 int idx = sh_pfc_get_pin_index(pfc, _pin);
602 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
605 case PIN_CONFIG_BIAS_DISABLE:
606 return pin->configs &
607 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
609 case PIN_CONFIG_BIAS_PULL_UP:
610 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
612 case PIN_CONFIG_BIAS_PULL_DOWN:
613 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
615 case PIN_CONFIG_DRIVE_STRENGTH:
616 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
618 case PIN_CONFIG_POWER_SOURCE:
619 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
626 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
627 unsigned int param, unsigned int arg)
629 struct sh_pfc *pfc = pmx->pfc;
630 void __iomem *pocctrl;
631 void __iomem *unlock_reg =
632 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
636 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
640 case PIN_CONFIG_BIAS_PULL_UP:
641 case PIN_CONFIG_BIAS_PULL_DOWN:
642 case PIN_CONFIG_BIAS_DISABLE:
643 if (!pfc->info->ops || !pfc->info->ops->set_bias)
646 pfc->info->ops->set_bias(pfc, _pin, param);
650 case PIN_CONFIG_DRIVE_STRENGTH:
651 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
657 case PIN_CONFIG_POWER_SOURCE:
658 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
661 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
663 printf("invalid pin %#x", _pin);
667 if (arg != 1800 && arg != 3300)
670 pocctrl = (void __iomem *)(uintptr_t)addr;
672 val = sh_pfc_read_raw_reg(pocctrl, 32);
679 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
681 sh_pfc_write_raw_reg(pocctrl, 32, val);
692 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
693 unsigned int pin_selector,
694 unsigned int param, unsigned int arg)
696 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
697 struct sh_pfc_pinctrl *pmx = &priv->pmx;
698 struct sh_pfc *pfc = &priv->pfc;
699 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
701 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
706 static int sh_pfc_pinconf_group_set(struct udevice *dev,
707 unsigned int group_selector,
708 unsigned int param, unsigned int arg)
710 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
711 struct sh_pfc_pinctrl *pmx = &priv->pmx;
712 struct sh_pfc *pfc = &priv->pfc;
713 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
716 for (i = 0; i < grp->nr_pins; i++)
717 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
723 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
724 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
725 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
726 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
727 .get_group_name = sh_pfc_pinctrl_get_group_name,
728 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
729 .get_function_name = sh_pfc_pinctrl_get_function_name,
731 #if CONFIG_IS_ENABLED(PINCONF)
732 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
733 .pinconf_params = sh_pfc_pinconf_params,
734 .pinconf_set = sh_pfc_pinconf_pin_set,
735 .pinconf_group_set = sh_pfc_pinconf_group_set,
737 .pinmux_set = sh_pfc_pinctrl_pin_set,
738 .pinmux_group_set = sh_pfc_pinctrl_group_set,
739 .set_state = pinctrl_generic_set_state,
742 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
746 /* Allocate and initialize the pins and configs arrays. */
747 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
749 if (unlikely(!pmx->configs))
752 for (i = 0; i < pfc->info->nr_pins; ++i) {
753 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
754 cfg->type = PINMUX_TYPE_NONE;
761 static int sh_pfc_pinctrl_probe(struct udevice *dev)
763 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
764 enum sh_pfc_model model = dev_get_driver_data(dev);
767 base = devfdt_get_addr(dev);
768 if (base == FDT_ADDR_T_NONE)
771 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
775 #ifdef CONFIG_PINCTRL_PFC_R8A7795
776 if (model == SH_PFC_R8A7795)
777 priv->pfc.info = &r8a7795_pinmux_info;
779 #ifdef CONFIG_PINCTRL_PFC_R8A7796
780 if (model == SH_PFC_R8A7796)
781 priv->pfc.info = &r8a7796_pinmux_info;
783 #ifdef CONFIG_PINCTRL_PFC_R8A77970
784 if (model == SH_PFC_R8A77970)
785 priv->pfc.info = &r8a77970_pinmux_info;
787 #ifdef CONFIG_PINCTRL_PFC_R8A77995
788 if (model == SH_PFC_R8A77995)
789 priv->pfc.info = &r8a77995_pinmux_info;
792 priv->pmx.pfc = &priv->pfc;
793 sh_pfc_init_ranges(&priv->pfc);
794 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
799 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
800 #ifdef CONFIG_PINCTRL_PFC_R8A7795
802 .compatible = "renesas,pfc-r8a7795",
803 .data = SH_PFC_R8A7795,
806 #ifdef CONFIG_PINCTRL_PFC_R8A7796
808 .compatible = "renesas,pfc-r8a7796",
809 .data = SH_PFC_R8A7796,
812 #ifdef CONFIG_PINCTRL_PFC_R8A77970
814 .compatible = "renesas,pfc-r8a77970",
815 .data = SH_PFC_R8A77970,
818 #ifdef CONFIG_PINCTRL_PFC_R8A77995
820 .compatible = "renesas,pfc-r8a77995",
821 .data = SH_PFC_R8A77995,
827 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
828 .name = "sh_pfc_pinctrl",
829 .id = UCLASS_PINCTRL,
830 .of_match = sh_pfc_pinctrl_ids,
831 .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
832 .ops = &sh_pfc_pinctrl_ops,
833 .probe = sh_pfc_pinctrl_probe,