2 * SuperH Pin Function Controller Support
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/stringify.h>
24 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
25 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
26 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
27 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
28 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
29 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
30 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
39 #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
44 .nr_pins = ARRAY_SIZE(n##_pins), \
46 #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
48 struct sh_pfc_pin_group {
50 const unsigned int *pins;
51 const unsigned int *mux;
56 * Using union vin_data saves memory occupied by the VIN data pins.
57 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
60 #define VIN_DATA_PIN_GROUP(n, s) \
63 .pins = n##_pins.data##s, \
64 .mux = n##_mux.data##s, \
65 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
69 unsigned int data24[24];
70 unsigned int data20[20];
71 unsigned int data16[16];
72 unsigned int data12[12];
73 unsigned int data10[10];
74 unsigned int data8[8];
75 unsigned int data4[4];
78 #define SH_PFC_FUNCTION(n) \
81 .groups = n##_groups, \
82 .nr_groups = ARRAY_SIZE(n##_groups), \
85 struct sh_pfc_function {
87 const char * const *groups;
88 unsigned int nr_groups;
96 struct pinmux_cfg_reg {
98 u8 reg_width, field_width;
100 const u8 *var_field_width;
104 * Describe a config register consisting of several fields of the same width
105 * - name: Register name (unused, for documentation purposes only)
106 * - r: Physical register address
107 * - r_width: Width of the register (in bits)
108 * - f_width: Width of the fixed-width register fields (in bits)
109 * This macro must be followed by initialization data: For each register field
110 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
111 * one for each possible combination of the register field bit values.
113 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
114 .reg = r, .reg_width = r_width, .field_width = f_width, \
115 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
118 * Describe a config register consisting of several fields of different widths
119 * - name: Register name (unused, for documentation purposes only)
120 * - r: Physical register address
121 * - r_width: Width of the register (in bits)
122 * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
123 * From left to right (i.e. MSB to LSB)
124 * This macro must be followed by initialization data: For each register field
125 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
126 * one for each possible combination of the register field bit values.
128 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
129 .reg = r, .reg_width = r_width, \
130 .var_field_width = (const u8 [r_width]) \
131 { var_fw0, var_fwn, 0 }, \
132 .enum_ids = (const u16 [])
134 struct pinmux_drive_reg_field {
140 struct pinmux_drive_reg {
142 const struct pinmux_drive_reg_field fields[8];
145 #define PINMUX_DRIVE_REG(name, r) \
149 struct pinmux_bias_reg {
150 u32 puen; /* Pull-enable or pull-up control register */
151 u32 pud; /* Pull-up/down control register (optional) */
155 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
160 struct pinmux_ioctrl_reg {
164 struct pinmux_data_reg {
171 * Describe a data register
172 * - name: Register name (unused, for documentation purposes only)
173 * - r: Physical register address
174 * - r_width: Width of the register (in bits)
175 * This macro must be followed by initialization data: For each register bit
176 * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
178 #define PINMUX_DATA_REG(name, r, r_width) \
179 .reg = r, .reg_width = r_width, \
180 .enum_ids = (const u16 [r_width]) \
187 * Describe the mapping from GPIOs to a single IRQ
188 * - ids...: List of GPIOs that are mapped to the same IRQ
190 #define PINMUX_IRQ(ids...) \
191 { .gpios = (const short []) { ids, -1 } }
193 struct pinmux_range {
199 struct sh_pfc_window {
205 struct sh_pfc_pin_range;
209 const struct sh_pfc_soc_info *info;
213 struct sh_pfc_pin_range *ranges;
214 unsigned int nr_ranges;
216 unsigned int nr_gpio_pins;
218 struct sh_pfc_chip *gpio;
221 struct sh_pfc_soc_operations {
222 int (*init)(struct sh_pfc *pfc);
223 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
224 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
226 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
229 struct sh_pfc_soc_info {
231 const struct sh_pfc_soc_operations *ops;
233 struct pinmux_range input;
234 struct pinmux_range output;
235 struct pinmux_range function;
237 const struct sh_pfc_pin *pins;
238 unsigned int nr_pins;
239 const struct sh_pfc_pin_group *groups;
240 unsigned int nr_groups;
241 const struct sh_pfc_function *functions;
242 unsigned int nr_functions;
244 const struct pinmux_cfg_reg *cfg_regs;
245 const struct pinmux_drive_reg *drive_regs;
246 const struct pinmux_bias_reg *bias_regs;
247 const struct pinmux_ioctrl_reg *ioctrl_regs;
248 const struct pinmux_data_reg *data_regs;
250 const u16 *pinmux_data;
251 unsigned int pinmux_data_size;
253 const struct pinmux_irq *gpio_irq;
254 unsigned int gpio_irq_size;
259 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
260 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
261 const struct pinmux_bias_reg *
262 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
264 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
266 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
267 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
268 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
269 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
270 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
271 extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
272 extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
273 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
274 extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
275 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
276 /* -----------------------------------------------------------------------------
277 * Helper macros to create pin and port lists
281 * sh_pfc_soc_info pinmux_data array macros
285 * Describe generic pinmux data
286 * - data_or_mark: *_DATA or *_MARK enum ID
287 * - ids...: List of enum IDs to associate with data_or_mark
289 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
292 * Describe a pinmux configuration without GPIO function that needs
293 * configuration in a Peripheral Function Select Register (IPSR)
294 * - ipsr: IPSR field (unused, for documentation purposes only)
295 * - fn: Function name, referring to a field in the IPSR
297 #define PINMUX_IPSR_NOGP(ipsr, fn) \
298 PINMUX_DATA(fn##_MARK, FN_##fn)
301 * Describe a pinmux configuration with GPIO function that needs configuration
302 * in both a Peripheral Function Select Register (IPSR) and in a
303 * GPIO/Peripheral Function Select Register (GPSR)
305 * - fn: Function name, also referring to the IPSR field
307 #define PINMUX_IPSR_GPSR(ipsr, fn) \
308 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
311 * Describe a pinmux configuration without GPIO function that needs
312 * configuration in a Peripheral Function Select Register (IPSR), and where the
313 * pinmux function has a representation in a Module Select Register (MOD_SEL).
314 * - ipsr: IPSR field (unused, for documentation purposes only)
315 * - fn: Function name, also referring to the IPSR field
316 * - msel: Module selector
318 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
319 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
322 * Describe a pinmux configuration with GPIO function where the pinmux function
323 * has no representation in a Peripheral Function Select Register (IPSR), but
324 * instead solely depends on a group selection.
326 * - fn: Function name, also referring to the GPSR field
327 * - gsel: Group selector
329 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
330 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
333 * Describe a pinmux configuration with GPIO function that needs configuration
334 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
335 * Function Select Register (GPSR), and where the pinmux function has a
336 * representation in a Module Select Register (MOD_SEL).
338 * - fn: Function name, also referring to the IPSR field
339 * - msel: Module selector
341 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
342 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
345 * Describe a pinmux configuration for a single-function pin with GPIO
347 * - fn: Function name
349 #define PINMUX_SINGLE(fn) \
350 PINMUX_DATA(fn##_MARK, FN_##fn)
353 * GP port style (32 ports banks)
356 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
357 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
358 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
360 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
361 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
362 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
363 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
364 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
365 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
367 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
368 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
369 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
370 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
371 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
373 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
374 PORT_GP_CFG_6(bank, fn, sfx, cfg), \
375 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
376 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
377 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
379 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
380 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
381 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
382 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
384 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
385 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
386 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
387 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
389 #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
390 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
391 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
392 #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
394 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
395 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
396 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
397 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
398 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
400 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
401 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
402 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
403 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
404 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
406 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
407 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
408 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
409 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
411 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
412 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
413 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
414 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
416 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
417 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
418 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
419 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
421 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
422 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
423 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
424 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
426 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
427 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
428 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
429 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
430 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
432 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
433 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
434 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
435 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
437 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
438 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
439 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
440 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
442 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
443 PORT_GP_CFG_22(bank, fn, sfx, cfg), \
444 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
445 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
447 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
448 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
449 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
450 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
452 #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
453 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
454 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
455 #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
457 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
458 PORT_GP_CFG_25(bank, fn, sfx, cfg), \
459 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
460 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
462 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
463 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
464 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
465 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
466 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
468 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
469 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
470 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
471 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
473 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
474 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
475 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
476 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
478 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
479 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
480 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
481 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
482 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
484 #define PORT_GP_32_REV(bank, fn, sfx) \
485 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
486 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
487 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
488 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
489 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
490 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
491 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
492 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
493 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
494 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
495 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
496 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
497 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
498 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
499 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
500 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
502 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
503 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
504 #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
506 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
507 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
509 .pin = (bank * 32) + _pin, \
510 .name = __stringify(_name), \
511 .enum_id = _name##_DATA, \
514 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
516 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
517 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
518 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
521 * PORT style (linear pin space)
524 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
526 #define PORT_10(pn, fn, pfx, sfx) \
527 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
528 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
529 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
530 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
531 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
533 #define PORT_90(pn, fn, pfx, sfx) \
534 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
535 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
536 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
537 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
538 PORT_10(pn+90, fn, pfx##9, sfx)
540 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
541 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
542 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
544 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
545 #define PINMUX_GPIO(_pin) \
548 .name = __stringify(GPIO_##_pin), \
549 .enum_id = _pin##_DATA, \
552 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
553 #define SH_PFC_PIN_CFG(_pin, cfgs) \
556 .name = __stringify(PORT##_pin), \
557 .enum_id = PORT##_pin##_DATA, \
561 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
562 #define SH_PFC_PIN_NAMED(row, col, _name) \
564 .pin = PIN_NUMBER(row, col), \
565 .name = __stringify(PIN_##_name), \
566 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
569 /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
570 #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
572 .pin = PIN_NUMBER(row, col), \
573 .name = __stringify(PIN_##_name), \
574 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
577 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
578 * PORT_name_OUT, PORT_name_IN marks
580 #define _PORT_DATA(pn, pfx, sfx) \
581 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
582 PORT##pfx##_OUT, PORT##pfx##_IN)
583 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
585 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
586 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
587 [gpio - (base)] = { \
588 .name = __stringify(gpio), \
589 .enum_id = data_or_mark, \
591 #define GPIO_FN(str) \
592 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
595 * PORTnCR helper macro for SH-Mobile/R-Mobile
597 #define PORTCR(nr, reg) \
599 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
600 /* PULMD[1:0], handled by .set_bias() */ \
603 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
604 /* SEC, not supported */ \
607 PORT##nr##_FN0, PORT##nr##_FN1, \
608 PORT##nr##_FN2, PORT##nr##_FN3, \
609 PORT##nr##_FN4, PORT##nr##_FN5, \
610 PORT##nr##_FN6, PORT##nr##_FN7 \
615 * GPIO number helper macro for R-Car
617 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
619 #endif /* __SH_PFC_H */