git.sur5r.net Git - u-boot/blob - drivers/pinctrl/rockchip/pinctrl_rk3036.c

   1 /*
   2  * Pinctrl driver for Rockchip 3036 SoCs
   3  * (C) Copyright 2015 Rockchip Electronics Co., Ltd
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/grf_rk3036.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/periph.h>
  17 #include <dm/pinctrl.h>
  18 #include <dm/root.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct rk3036_pinctrl_priv {
  23         struct rk3036_grf *grf;
  24 };
  25
  26 static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id)
  27 {
  28         switch (pwm_id) {
  29         case PERIPH_ID_PWM0:
  30                 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK << GPIO0D2_SHIFT,
  31                              GPIO0D2_PWM0 << GPIO0D2_SHIFT);
  32                 break;
  33         case PERIPH_ID_PWM1:
  34                 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK << GPIO0A0_SHIFT,
  35                              GPIO0A0_PWM1 << GPIO0A0_SHIFT);
  36                 break;
  37         case PERIPH_ID_PWM2:
  38                 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK << GPIO0A1_SHIFT,
  39                              GPIO0A1_PWM2 << GPIO0A1_SHIFT);
  40                 break;
  41         case PERIPH_ID_PWM3:
  42                 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK << GPIO0D3_SHIFT,
  43                              GPIO0D3_PWM3 << GPIO0D3_SHIFT);
  44                 break;
  45         default:
  46                 debug("pwm id = %d iomux error!\n", pwm_id);
  47                 break;
  48         }
  49 }
  50
  51 static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id)
  52 {
  53         switch (i2c_id) {
  54         case PERIPH_ID_I2C0:
  55                 rk_clrsetreg(&grf->gpio0a_iomux,
  56                              GPIO0A1_MASK << GPIO0A1_SHIFT |
  57                              GPIO0A0_MASK << GPIO0A0_SHIFT,
  58                              GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
  59                              GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
  60
  61                 break;
  62         case PERIPH_ID_I2C1:
  63                 rk_clrsetreg(&grf->gpio0a_iomux,
  64                              GPIO0A3_MASK << GPIO0A3_SHIFT |
  65                              GPIO0A2_MASK << GPIO0A2_SHIFT,
  66                              GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
  67                              GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
  68                 break;
  69         case PERIPH_ID_I2C2:
  70                 rk_clrsetreg(&grf->gpio2c_iomux,
  71                              GPIO2C5_MASK << GPIO2C5_SHIFT |
  72                              GPIO2C4_MASK << GPIO2C4_SHIFT,
  73                              GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
  74                              GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
  75
  76                 break;
  77         }
  78 }
  79
  80 static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs)
  81 {
  82         switch (cs) {
  83         case 0:
  84                 rk_clrsetreg(&grf->gpio1d_iomux,
  85                              GPIO1D6_MASK << GPIO1D6_SHIFT,
  86                              GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
  87                 break;
  88         case 1:
  89                 rk_clrsetreg(&grf->gpio1d_iomux,
  90                              GPIO1D7_MASK << GPIO1D7_SHIFT,
  91                              GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
  92                 break;
  93         }
  94         rk_clrsetreg(&grf->gpio1d_iomux,
  95                      GPIO1D5_MASK << GPIO1D5_SHIFT |
  96                      GPIO1D4_MASK << GPIO1D4_SHIFT,
  97                      GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
  98                      GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
  99
 100         rk_clrsetreg(&grf->gpio2a_iomux,
 101                      GPIO2A0_MASK << GPIO2A0_SHIFT,
 102                      GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
 103 }
 104
 105 static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
 106 {
 107         switch (uart_id) {
 108         case PERIPH_ID_UART0:
 109                 rk_clrsetreg(&grf->gpio0c_iomux,
 110                              GPIO0C3_MASK << GPIO0C3_SHIFT |
 111                              GPIO0C2_MASK << GPIO0C2_SHIFT |
 112                              GPIO0C1_MASK << GPIO0C1_SHIFT |
 113                              GPIO0C0_MASK << GPIO0C0_SHIFT,
 114                              GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
 115                              GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
 116                              GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
 117                              GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT);
 118                 break;
 119         case PERIPH_ID_UART1:
 120                 rk_clrsetreg(&grf->gpio2c_iomux,
 121                              GPIO2C7_MASK << GPIO2C7_SHIFT |
 122                              GPIO2C6_MASK << GPIO2C6_SHIFT,
 123                              GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
 124                              GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
 125                 break;
 126         case PERIPH_ID_UART2:
 127                 rk_clrsetreg(&grf->gpio1c_iomux,
 128                              GPIO1C3_MASK << GPIO1C3_SHIFT |
 129                              GPIO1C2_MASK << GPIO1C2_SHIFT,
 130                              GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
 131                              GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
 132                 break;
 133         }
 134 }
 135
 136 static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id)
 137 {
 138         switch (mmc_id) {
 139         case PERIPH_ID_EMMC:
 140                 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
 141                              GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
 142                              GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
 143                              GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
 144                              GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
 145                              GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
 146                              GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
 147                              GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
 148                              GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
 149                 rk_clrsetreg(&grf->gpio2a_iomux,
 150                              GPIO2A4_MASK << GPIO2A4_SHIFT |
 151                              GPIO2A1_MASK << GPIO2A1_SHIFT,
 152                              GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
 153                              GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
 154                 break;
 155         case PERIPH_ID_SDCARD:
 156                 rk_clrsetreg(&grf->gpio1c_iomux, 0xffff,
 157                              GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
 158                              GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
 159                              GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
 160                              GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
 161                              GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
 162                              GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
 163                 break;
 164         }
 165 }
 166
 167 static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags)
 168 {
 169         struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
 170
 171         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 172         switch (func) {
 173         case PERIPH_ID_PWM0:
 174         case PERIPH_ID_PWM1:
 175         case PERIPH_ID_PWM2:
 176         case PERIPH_ID_PWM3:
 177                 pinctrl_rk3036_pwm_config(priv->grf, func);
 178                 break;
 179         case PERIPH_ID_I2C0:
 180         case PERIPH_ID_I2C1:
 181         case PERIPH_ID_I2C2:
 182                 pinctrl_rk3036_i2c_config(priv->grf, func);
 183                 break;
 184         case PERIPH_ID_SPI0:
 185                 pinctrl_rk3036_spi_config(priv->grf, flags);
 186                 break;
 187         case PERIPH_ID_UART0:
 188         case PERIPH_ID_UART1:
 189         case PERIPH_ID_UART2:
 190                 pinctrl_rk3036_uart_config(priv->grf, func);
 191                 break;
 192         case PERIPH_ID_SDMMC0:
 193         case PERIPH_ID_SDMMC1:
 194                 pinctrl_rk3036_sdmmc_config(priv->grf, func);
 195                 break;
 196         default:
 197                 return -EINVAL;
 198         }
 199
 200         return 0;
 201 }
 202
 203 static int rk3036_pinctrl_get_periph_id(struct udevice *dev,
 204                                         struct udevice *periph)
 205 {
 206         u32 cell[3];
 207         int ret;
 208
 209         ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
 210                                    "interrupts", cell, ARRAY_SIZE(cell));
 211         if (ret < 0)
 212                 return -EINVAL;
 213
 214         switch (cell[1]) {
 215         case 14:
 216                 return PERIPH_ID_SDCARD;
 217         case 16:
 218                 return PERIPH_ID_EMMC;
 219         case 20:
 220                 return PERIPH_ID_UART0;
 221         case 21:
 222                 return PERIPH_ID_UART1;
 223         case 22:
 224                 return PERIPH_ID_UART2;
 225         case 23:
 226                 return PERIPH_ID_SPI0;
 227         case 24:
 228                 return PERIPH_ID_I2C0;
 229         case 25:
 230                 return PERIPH_ID_I2C1;
 231         case 26:
 232                 return PERIPH_ID_I2C2;
 233         case 30:
 234                 return PERIPH_ID_PWM0;
 235         }
 236         return -ENOENT;
 237 }
 238
 239 static int rk3036_pinctrl_set_state_simple(struct udevice *dev,
 240                                            struct udevice *periph)
 241 {
 242         int func;
 243
 244         func = rk3036_pinctrl_get_periph_id(dev, periph);
 245         if (func < 0)
 246                 return func;
 247         return rk3036_pinctrl_request(dev, func, 0);
 248 }
 249
 250 static struct pinctrl_ops rk3036_pinctrl_ops = {
 251         .set_state_simple       = rk3036_pinctrl_set_state_simple,
 252         .request        = rk3036_pinctrl_request,
 253         .get_periph_id  = rk3036_pinctrl_get_periph_id,
 254 };
 255
 256 static int rk3036_pinctrl_bind(struct udevice *dev)
 257 {
 258         /* scan child GPIO banks */
 259         return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
 260 }
 261
 262 static int rk3036_pinctrl_probe(struct udevice *dev)
 263 {
 264         struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
 265
 266         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 267         debug("%s: grf=%p\n", __func__, priv->grf);
 268         return 0;
 269 }
 270
 271 static const struct udevice_id rk3036_pinctrl_ids[] = {
 272         { .compatible = "rockchip,rk3036-pinctrl" },
 273         { }
 274 };
 275
 276 U_BOOT_DRIVER(pinctrl_rk3036) = {
 277         .name           = "pinctrl_rk3036",
 278         .id             = UCLASS_PINCTRL,
 279         .of_match       = rk3036_pinctrl_ids,
 280         .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
 281         .ops            = &rk3036_pinctrl_ops,
 282         .bind           = rk3036_pinctrl_bind,
 283         .probe          = rk3036_pinctrl_probe,
 284 };