2 * Pinctrl driver for Rockchip 3036 SoCs
3 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/grf_rk3036.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/periph.h>
17 #include <dm/pinctrl.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 /* GRF_GPIO0A_IOMUX */
24 GPIO0A3_MASK = 1 << GPIO0A3_SHIFT,
29 GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
34 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
40 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
46 /* GRF_GPIO0B_IOMUX */
49 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
55 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
61 GPIO0B4_MASK = 3 << GPIO0B4_SHIFT,
67 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
73 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
85 /* GRF_GPIO0C_IOMUX */
88 GPIO0C4_MASK = 1 << GPIO0C4_SHIFT,
93 GPIO0C3_MASK = 1 << GPIO0C3_SHIFT,
98 GPIO0C2_MASK = 1 << GPIO0C2_SHIFT,
103 GPIO0C1_MASK = 1 << GPIO0C1_SHIFT,
109 GPIO0C0_MASK = 1 << GPIO0C0_SHIFT,
114 /* GRF_GPIO0D_IOMUX */
117 GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
122 GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
127 GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
132 /* GRF_GPIO1A_IOMUX */
135 GPIO1A5_MASK = 1 << GPIO1A5_SHIFT,
140 GPIO1A4_MASK = 1 << GPIO1A4_SHIFT,
145 GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
150 GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
156 GPIO1A1_MASK = 1 << GPIO1A1_SHIFT,
161 GPIO1A0_MASK = 1 << GPIO1A0_SHIFT,
167 /* GRF_GPIO1B_IOMUX */
170 GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
175 GPIO1B3_MASK = 1 << GPIO1B3_SHIFT,
180 GPIO1B2_MASK = 1 << GPIO1B2_SHIFT,
185 GPIO1B1_MASK = 1 << GPIO1B1_SHIFT,
190 GPIO1B0_MASK = 1 << GPIO1B0_SHIFT,
195 /* GRF_GPIO1C_IOMUX */
198 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
204 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
210 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
216 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
222 GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
227 GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
232 /* GRF_GPIO1D_IOMUX */
235 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
242 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
249 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
256 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
263 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
270 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
277 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
284 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
291 /* GRF_GPIO2A_IOMUX */
294 GPIO2A7_MASK = 1 << GPIO2A7_SHIFT,
299 GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
304 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
311 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
317 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
323 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
329 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
335 /* GRF_GPIO2B_IOMUX */
338 GPIO2B7_MASK = 1 << GPIO2B7_SHIFT,
343 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
349 GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
354 GPIO2B4_MASK = 1 << GPIO2B4_SHIFT,
359 GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
364 /* GRF_GPIO2C_IOMUX */
367 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
370 GPIO2C7_TESTCLK_OUT1,
373 GPIO2C6_MASK = 1 << GPIO2C6_SHIFT,
378 GPIO2C5_MASK = 1 << GPIO2C5_SHIFT,
383 GPIO2C4_MASK = 1 << GPIO2C4_SHIFT,
388 GPIO2C3_MASK = 1 << GPIO2C3_SHIFT,
393 GPIO2C2_MASK = 1 << GPIO2C2_SHIFT,
398 GPIO2C1_MASK = 1 << GPIO2C1_SHIFT,
403 GPIO2C0_MASK = 1 << GPIO2C0_SHIFT,
408 /* GRF_GPIO2D_IOMUX */
411 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
416 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
421 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
426 GPIO2D1_MASK = 1 << GPIO2D1_SHIFT,
431 struct rk3036_pinctrl_priv {
432 struct rk3036_grf *grf;
435 static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id)
439 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
440 GPIO0D2_PWM0 << GPIO0D2_SHIFT);
443 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK,
444 GPIO0A0_PWM1 << GPIO0A0_SHIFT);
447 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK,
448 GPIO0A1_PWM2 << GPIO0A1_SHIFT);
451 rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK,
452 GPIO0D3_PWM3 << GPIO0D3_SHIFT);
455 debug("pwm id = %d iomux error!\n", pwm_id);
460 static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id)
464 rk_clrsetreg(&grf->gpio0a_iomux,
465 GPIO0A1_MASK | GPIO0A0_MASK,
466 GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
467 GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
471 rk_clrsetreg(&grf->gpio0a_iomux,
472 GPIO0A3_MASK | GPIO0A2_MASK,
473 GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
474 GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
477 rk_clrsetreg(&grf->gpio2c_iomux,
478 GPIO2C5_MASK | GPIO2C4_MASK,
479 GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
480 GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
486 static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs)
490 rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK,
491 GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
494 rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK,
495 GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
498 rk_clrsetreg(&grf->gpio1d_iomux,
499 GPIO1D5_MASK | GPIO1D4_MASK,
500 GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
501 GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
503 rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK,
504 GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
507 static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
510 case PERIPH_ID_UART0:
511 rk_clrsetreg(&grf->gpio0c_iomux,
512 GPIO0C3_MASK | GPIO0C2_MASK |
513 GPIO0C1_MASK | GPIO0C0_MASK,
514 GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
515 GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
516 GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
517 GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT);
519 case PERIPH_ID_UART1:
520 rk_clrsetreg(&grf->gpio2c_iomux,
521 GPIO2C7_MASK | GPIO2C6_MASK,
522 GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
523 GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
525 case PERIPH_ID_UART2:
526 rk_clrsetreg(&grf->gpio1c_iomux,
527 GPIO1C3_MASK | GPIO1C2_MASK,
528 GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
529 GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
534 static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id)
538 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
539 GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
540 GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
541 GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
542 GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
543 GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
544 GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
545 GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
546 GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
547 rk_clrsetreg(&grf->gpio2a_iomux,
548 GPIO2A4_MASK | GPIO2A1_MASK,
549 GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
550 GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
552 case PERIPH_ID_SDCARD:
553 rk_clrsetreg(&grf->gpio1c_iomux, 0xffff,
554 GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
555 GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
556 GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
557 GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
558 GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
559 GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
564 static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags)
566 struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
568 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
574 pinctrl_rk3036_pwm_config(priv->grf, func);
579 pinctrl_rk3036_i2c_config(priv->grf, func);
582 pinctrl_rk3036_spi_config(priv->grf, flags);
584 case PERIPH_ID_UART0:
585 case PERIPH_ID_UART1:
586 case PERIPH_ID_UART2:
587 pinctrl_rk3036_uart_config(priv->grf, func);
589 case PERIPH_ID_SDMMC0:
590 case PERIPH_ID_SDMMC1:
591 pinctrl_rk3036_sdmmc_config(priv->grf, func);
600 static int rk3036_pinctrl_get_periph_id(struct udevice *dev,
601 struct udevice *periph)
606 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
612 return PERIPH_ID_SDCARD;
614 return PERIPH_ID_EMMC;
616 return PERIPH_ID_UART0;
618 return PERIPH_ID_UART1;
620 return PERIPH_ID_UART2;
622 return PERIPH_ID_SPI0;
624 return PERIPH_ID_I2C0;
626 return PERIPH_ID_I2C1;
628 return PERIPH_ID_I2C2;
630 return PERIPH_ID_PWM0;
635 static int rk3036_pinctrl_set_state_simple(struct udevice *dev,
636 struct udevice *periph)
640 func = rk3036_pinctrl_get_periph_id(dev, periph);
643 return rk3036_pinctrl_request(dev, func, 0);
646 static struct pinctrl_ops rk3036_pinctrl_ops = {
647 .set_state_simple = rk3036_pinctrl_set_state_simple,
648 .request = rk3036_pinctrl_request,
649 .get_periph_id = rk3036_pinctrl_get_periph_id,
652 static int rk3036_pinctrl_probe(struct udevice *dev)
654 struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
656 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
657 debug("%s: grf=%p\n", __func__, priv->grf);
661 static const struct udevice_id rk3036_pinctrl_ids[] = {
662 { .compatible = "rockchip,rk3036-pinctrl" },
666 U_BOOT_DRIVER(pinctrl_rk3036) = {
667 .name = "pinctrl_rk3036",
668 .id = UCLASS_PINCTRL,
669 .of_match = rk3036_pinctrl_ids,
670 .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
671 .ops = &rk3036_pinctrl_ops,
672 .bind = dm_scan_fdt_dev,
673 .probe = rk3036_pinctrl_probe,