1 // SPDX-License-Identifier: GPL-2.0+
3 * Pinctrl driver for Rockchip RK3188 SoCs
4 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/grf_rk3188.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/periph.h>
16 #include <asm/arch/pmu_rk3188.h>
17 #include <dm/pinctrl.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* GRF_GPIO0D_IOMUX */
48 GPIO0D3_EMMC_RSTN_OUT,
68 /* GRF_GPIO1A_IOMUX */
115 /* GRF_GPIO1B_IOMUX */
165 /* GRF_GPIO1D_IOMUX */
208 /* GRF_GPIO3A_IOMUX */
213 GPIO3A7_SDMMC0_DATA3,
218 GPIO3A6_SDMMC0_DATA2,
223 GPIO3A5_SDMMC0_DATA1,
228 GPIO3A4_SDMMC0_DATA0,
238 GPIO3A2_SDMMC0_CLKOUT,
243 GPIO3A1_SDMMC0_PWREN,
251 /* GRF_GPIO3B_IOMUX */
290 GPIO3B1_SDMMC0_WRITE_PRT,
295 GPIO3B0_SDMMC_DETECT_N,
298 /* GRF_GPIO3C_IOMUX */
303 GPIO3C7_SDMMC1_WRITE_PRT,
304 GPIO3C7_RMII_CRS_DVALID,
310 GPIO3C6_SDMMC1_DECTN,
317 GPIO3C5_SDMMC1_CLKOUT,
324 GPIO3C4_SDMMC1_DATA3,
331 GPIO3C3_SDMMC1_DATA2,
338 GPIO3C2_SDMMC1_DATA1,
345 GPIO3C1_SDMMC1_DATA0,
357 /* GRF_GPIO3D_IOMUX */
364 GPIO3D6_HOST_DRV_VBUS,
371 GPIO3D5_OTG_DRV_VBUS,
387 GPIO3D2_SDMMC1_INT_N,
392 GPIO3D1_SDMMC1_BACKEND_PWR,
398 GPIO3D0_SDMMC1_PWR_EN,
402 struct rk3188_pinctrl_priv {
403 struct rk3188_grf *grf;
404 struct rk3188_pmu *pmu;
409 * Encode variants of iomux registers into a type variable
411 #define IOMUX_GPIO_ONLY BIT(0)
414 * @type: iomux variant using IOMUX_* constants
415 * @offset: if initialized to -1 it will be autocalculated, by specifying
416 * an initial offset value the relevant source offset can be reset
417 * to a new value for autocalculating the following iomux registers.
419 struct rockchip_iomux {
425 * @reg: register offset of the gpio bank
426 * @nr_pins: number of pins in this bank
427 * @bank_num: number of the bank, to account for holes
428 * @name: name of the bank
429 * @iomux: array describing the 4 iomux sources of the bank
431 struct rockchip_pin_bank {
436 struct rockchip_iomux iomux[4];
439 #define PIN_BANK(id, pins, label) \
452 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
458 { .type = iom0, .offset = -1 }, \
459 { .type = iom1, .offset = -1 }, \
460 { .type = iom2, .offset = -1 }, \
461 { .type = iom3, .offset = -1 }, \
465 #ifndef CONFIG_SPL_BUILD
466 static struct rockchip_pin_bank rk3188_pin_banks[] = {
467 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
468 PIN_BANK(1, 32, "gpio1"),
469 PIN_BANK(2, 32, "gpio2"),
470 PIN_BANK(3, 32, "gpio3"),
474 static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id)
478 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT,
479 GPIO3D3_PWM_0 << GPIO3D3_SHIFT);
482 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT,
483 GPIO3D4_PWM_1 << GPIO3D4_SHIFT);
486 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT,
487 GPIO3D5_PWM_2 << GPIO3D5_SHIFT);
490 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT,
491 GPIO3D6_PWM_3 << GPIO3D6_SHIFT);
494 debug("pwm id = %d iomux error!\n", pwm_id);
499 static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf,
500 struct rk3188_pmu *pmu, int i2c_id)
504 rk_clrsetreg(&grf->gpio1d_iomux,
505 GPIO1D1_MASK << GPIO1D1_SHIFT |
506 GPIO1D0_MASK << GPIO1D0_SHIFT,
507 GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT |
508 GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT);
509 /* enable new i2c controller */
510 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
511 1 << RKI2C0_SEL_SHIFT);
514 rk_clrsetreg(&grf->gpio1d_iomux,
515 GPIO1D3_MASK << GPIO1D3_SHIFT |
516 GPIO1D2_MASK << GPIO1D2_SHIFT,
517 GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT |
518 GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT);
519 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
520 1 << RKI2C1_SEL_SHIFT);
523 rk_clrsetreg(&grf->gpio1d_iomux,
524 GPIO1D5_MASK << GPIO1D5_SHIFT |
525 GPIO1D4_MASK << GPIO1D4_SHIFT,
526 GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT |
527 GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT);
528 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
529 1 << RKI2C2_SEL_SHIFT);
532 rk_clrsetreg(&grf->gpio3b_iomux,
533 GPIO3B7_MASK << GPIO3B7_SHIFT |
534 GPIO3B6_MASK << GPIO3B6_SHIFT,
535 GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT |
536 GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT);
537 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
538 1 << RKI2C3_SEL_SHIFT);
541 rk_clrsetreg(&grf->gpio1d_iomux,
542 GPIO1D7_MASK << GPIO1D7_SHIFT |
543 GPIO1D6_MASK << GPIO1D6_SHIFT,
544 GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT |
545 GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT);
546 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
547 1 << RKI2C4_SEL_SHIFT);
550 debug("i2c id = %d iomux error!\n", i2c_id);
555 static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf,
556 enum periph_id spi_id, int cs)
562 rk_clrsetreg(&grf->gpio1a_iomux,
563 GPIO1A7_MASK << GPIO1A7_SHIFT,
564 GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT);
567 rk_clrsetreg(&grf->gpio1b_iomux,
568 GPIO1B7_MASK << GPIO1B7_SHIFT,
569 GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT);
574 rk_clrsetreg(&grf->gpio1a_iomux,
575 GPIO1A4_MASK << GPIO1A4_SHIFT |
576 GPIO1A5_MASK << GPIO1A5_SHIFT |
577 GPIO1A6_MASK << GPIO1A6_SHIFT,
578 GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT |
579 GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT |
580 GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT);
585 rk_clrsetreg(&grf->gpio0d_iomux,
586 GPIO0D7_MASK << GPIO0D7_SHIFT,
587 GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT);
590 rk_clrsetreg(&grf->gpio1b_iomux,
591 GPIO1B6_MASK << GPIO1B6_SHIFT,
592 GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT);
597 rk_clrsetreg(&grf->gpio0d_iomux,
598 GPIO0D4_MASK << GPIO0D4_SHIFT |
599 GPIO0D5_MASK << GPIO0D5_SHIFT |
600 GPIO0D6_MASK << GPIO0D6_SHIFT,
601 GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT |
602 GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT |
603 GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT);
611 debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
615 static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id)
618 case PERIPH_ID_UART0:
619 rk_clrsetreg(&grf->gpio1a_iomux,
620 GPIO1A3_MASK << GPIO1A3_SHIFT |
621 GPIO1A2_MASK << GPIO1A2_SHIFT |
622 GPIO1A1_MASK << GPIO1A1_SHIFT |
623 GPIO1A0_MASK << GPIO1A0_SHIFT,
624 GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
625 GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
626 GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT |
627 GPIO1A0_UART0_SIN << GPIO1A0_SHIFT);
629 case PERIPH_ID_UART1:
630 rk_clrsetreg(&grf->gpio1a_iomux,
631 GPIO1A7_MASK << GPIO1A7_SHIFT |
632 GPIO1A6_MASK << GPIO1A6_SHIFT |
633 GPIO1A5_MASK << GPIO1A5_SHIFT |
634 GPIO1A4_MASK << GPIO1A4_SHIFT,
635 GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
636 GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
637 GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
638 GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
640 case PERIPH_ID_UART2:
641 rk_clrsetreg(&grf->gpio1b_iomux,
642 GPIO1B1_MASK << GPIO1B1_SHIFT |
643 GPIO1B0_MASK << GPIO1B0_SHIFT,
644 GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
645 GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
647 case PERIPH_ID_UART3:
648 rk_clrsetreg(&grf->gpio1b_iomux,
649 GPIO1B5_MASK << GPIO1B5_SHIFT |
650 GPIO1B4_MASK << GPIO1B4_SHIFT |
651 GPIO1B3_MASK << GPIO1B3_SHIFT |
652 GPIO1B2_MASK << GPIO1B2_SHIFT,
653 GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT |
654 GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT |
655 GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT |
656 GPIO1B2_UART3_SIN << GPIO1B2_SHIFT);
659 debug("uart id = %d iomux error!\n", uart_id);
664 static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id)
668 rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT,
669 1 << EMMC_FLASH_SEL_SHIFT);
670 rk_clrsetreg(&grf->gpio0d_iomux,
671 GPIO0D2_MASK << GPIO0D2_SHIFT |
672 GPIO0D0_MASK << GPIO0D0_SHIFT,
673 GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT |
674 GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT);
676 case PERIPH_ID_SDCARD:
677 rk_clrsetreg(&grf->gpio3b_iomux,
678 GPIO3B0_MASK << GPIO3B0_SHIFT,
679 GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT);
680 rk_clrsetreg(&grf->gpio3a_iomux,
681 GPIO3A7_MASK << GPIO3A7_SHIFT |
682 GPIO3A6_MASK << GPIO3A6_SHIFT |
683 GPIO3A5_MASK << GPIO3A5_SHIFT |
684 GPIO3A4_MASK << GPIO3A4_SHIFT |
685 GPIO3A3_MASK << GPIO3A3_SHIFT |
686 GPIO3A3_MASK << GPIO3A2_SHIFT,
687 GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT |
688 GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT |
689 GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT |
690 GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT |
691 GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT |
692 GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT);
695 debug("mmc id = %d iomux error!\n", mmc_id);
700 static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags)
702 struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
704 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
711 pinctrl_rk3188_pwm_config(priv->grf, func);
719 pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func);
724 pinctrl_rk3188_spi_config(priv->grf, func, flags);
726 case PERIPH_ID_UART0:
727 case PERIPH_ID_UART1:
728 case PERIPH_ID_UART2:
729 case PERIPH_ID_UART3:
730 case PERIPH_ID_UART4:
731 pinctrl_rk3188_uart_config(priv->grf, func);
734 case PERIPH_ID_SDMMC0:
735 case PERIPH_ID_SDMMC1:
736 pinctrl_rk3188_sdmmc_config(priv->grf, func);
745 static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
746 struct udevice *periph)
748 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
752 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
758 return PERIPH_ID_SPI0;
760 return PERIPH_ID_SPI1;
762 return PERIPH_ID_SPI2;
764 return PERIPH_ID_I2C0;
765 case 62: /* Note strange order */
766 return PERIPH_ID_I2C1;
768 return PERIPH_ID_I2C2;
770 return PERIPH_ID_I2C3;
772 return PERIPH_ID_I2C4;
774 return PERIPH_ID_I2C5;
781 static int rk3188_pinctrl_set_state_simple(struct udevice *dev,
782 struct udevice *periph)
786 func = rk3188_pinctrl_get_periph_id(dev, periph);
789 return rk3188_pinctrl_request(dev, func, 0);
792 #ifndef CONFIG_SPL_BUILD
793 int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv,
794 int banknum, int ind, u32 **addrp, uint *shiftp,
797 struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum];
801 for (muxnum = 0; muxnum < 4; muxnum++) {
802 struct rockchip_iomux *mux = &bank->iomux[muxnum];
809 addr = &priv->grf->gpio0c_iomux - 2;
815 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
824 static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
827 struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
833 ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
837 return (readl(addr) & mask) >> shift;
840 static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
841 int muxval, int flags)
843 struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
844 uint shift, ind = index;
849 debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
850 ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
854 rk_clrsetreg(addr, mask << shift, muxval << shift);
856 /* Handle pullup/pulldown */
860 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
862 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
867 if (banknum == 0 && index < 12) {
868 addr = &priv->pmu->gpio0_p[ind];
869 shift = (index & 7) * 2;
870 } else if (banknum == 0 && index >= 12) {
871 addr = &priv->grf->gpio0_p[ind - 1];
873 * The bits in the grf-registers have an inverse
874 * ordering with the lowest pin being in bits 15:14
875 * and the highest pin in bits 1:0 .
877 shift = (7 - (index & 7)) * 2;
879 addr = &priv->grf->gpio1_p[banknum - 1][ind];
880 shift = (7 - (index & 7)) * 2;
882 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
884 rk_clrsetreg(addr, 3 << shift, val << shift);
890 static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
892 const void *blob = gd->fdt_blob;
893 int pcfg_node, ret, flags, count, i;
896 debug("%s: %s %s\n", __func__, dev->name, config->name);
897 ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
898 "rockchip,pins", cell,
901 debug("%s: bad array %d\n", __func__, ret);
905 for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
906 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
909 flags = pinctrl_decode_pin_config(blob, pcfg_node);
913 ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
923 static struct pinctrl_ops rk3188_pinctrl_ops = {
924 #ifndef CONFIG_SPL_BUILD
925 .set_state = rk3188_pinctrl_set_state,
926 .get_gpio_mux = rk3188_pinctrl_get_gpio_mux,
928 .set_state_simple = rk3188_pinctrl_set_state_simple,
929 .request = rk3188_pinctrl_request,
930 .get_periph_id = rk3188_pinctrl_get_periph_id,
933 #ifndef CONFIG_SPL_BUILD
934 static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv,
935 struct rockchip_pin_bank *banks,
938 struct rockchip_pin_bank *bank;
939 uint reg, muxnum, banknum;
942 for (banknum = 0; banknum < count; banknum++) {
943 bank = &banks[banknum];
945 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
946 for (muxnum = 0; muxnum < 4; muxnum++) {
947 struct rockchip_iomux *mux = &bank->iomux[muxnum];
958 static int rk3188_pinctrl_probe(struct udevice *dev)
960 struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
963 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
964 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
965 debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
966 #ifndef CONFIG_SPL_BUILD
967 ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks,
968 ARRAY_SIZE(rk3188_pin_banks));
974 static const struct udevice_id rk3188_pinctrl_ids[] = {
975 { .compatible = "rockchip,rk3188-pinctrl" },
979 U_BOOT_DRIVER(pinctrl_rk3188) = {
980 .name = "rockchip_rk3188_pinctrl",
981 .id = UCLASS_PINCTRL,
982 .of_match = rk3188_pinctrl_ids,
983 .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv),
984 .ops = &rk3188_pinctrl_ops,
985 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
986 .bind = dm_scan_fdt_dev,
988 .probe = rk3188_pinctrl_probe,