1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
11 #include <asm/arch/clock.h>
12 #include <asm/arch/grf_rk322x.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <dm/pinctrl.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 /* GRF_GPIO0A_IOMUX */
22 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
28 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
34 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
40 GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
45 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
50 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
55 /* GRF_GPIO0B_IOMUX */
58 GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
63 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
69 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
75 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
81 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
92 /* GRF_GPIO0C_IOMUX */
95 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
100 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
106 /* GRF_GPIO0D_IOMUX */
109 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
115 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
120 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
125 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
130 /* GRF_GPIO1A_IOMUX */
138 /* GRF_GPIO1B_IOMUX */
141 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
146 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
151 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
157 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
163 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
169 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
175 /* GRF_GPIO1C_IOMUX */
178 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
181 GPIO1C7_EMMC_RSTNOUT,
184 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
190 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
196 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
202 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
208 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
214 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
219 GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
221 GPIO1C0_SDMMC_CLKOUT,
224 /* GRF_GPIO1D_IOMUX */
227 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
233 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
239 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
245 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
251 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
257 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
263 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
269 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
275 /* GRF_GPIO2A_IOMUX */
278 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
284 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
290 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
296 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
302 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
308 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
314 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
320 /* GRF_GPIO2B_IOMUX */
323 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
328 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
334 GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
339 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
344 GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
349 GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
354 GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
359 GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
362 GPIO2B0_MAC_SPEED_IOUT,
365 /* GRF_GPIO2C_IOMUX */
368 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
373 GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
378 GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
384 GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
390 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
395 GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
400 GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
405 GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
410 /* GRF_GPIO2D_IOMUX */
413 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
423 /* GRF_GPIO3C_IOMUX */
426 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
431 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
436 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
441 /* GRF_GPIO3D_IOMUX */
444 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
451 CON_IOMUX_GMACSEL_SHIFT = 15,
452 CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT,
453 CON_IOMUX_GMACSEL_1 = 1,
454 CON_IOMUX_UART1SEL_SHIFT = 11,
455 CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
456 CON_IOMUX_UART2SEL_SHIFT = 8,
457 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
458 CON_IOMUX_UART2SEL_2 = 0,
459 CON_IOMUX_UART2SEL_21,
460 CON_IOMUX_EMMCSEL_SHIFT = 7,
461 CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
462 CON_IOMUX_PWM3SEL_SHIFT = 3,
463 CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
464 CON_IOMUX_PWM2SEL_SHIFT = 2,
465 CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
466 CON_IOMUX_PWM1SEL_SHIFT = 1,
467 CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
468 CON_IOMUX_PWM0SEL_SHIFT = 0,
469 CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
474 GRF_GPIO2B0_E_SHIFT = 0,
475 GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
476 GRF_GPIO2B1_E_SHIFT = 2,
477 GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
478 GRF_GPIO2B3_E_SHIFT = 6,
479 GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
480 GRF_GPIO2B4_E_SHIFT = 8,
481 GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
482 GRF_GPIO2B5_E_SHIFT = 10,
483 GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
484 GRF_GPIO2B6_E_SHIFT = 12,
485 GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
490 GRF_GPIO2C0_E_SHIFT = 0,
491 GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
492 GRF_GPIO2C1_E_SHIFT = 2,
493 GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
494 GRF_GPIO2C2_E_SHIFT = 4,
495 GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
496 GRF_GPIO2C3_E_SHIFT = 6,
497 GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
498 GRF_GPIO2C4_E_SHIFT = 8,
499 GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
500 GRF_GPIO2C5_E_SHIFT = 10,
501 GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
502 GRF_GPIO2C6_E_SHIFT = 12,
503 GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
504 GRF_GPIO2C7_E_SHIFT = 14,
505 GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
510 GRF_GPIO2D1_E_SHIFT = 2,
511 GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
514 /* GPIO Bias drive strength settings */
522 struct rk322x_pinctrl_priv {
523 struct rk322x_grf *grf;
526 static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
528 u32 mux_con = readl(&grf->con_iomux);
532 if (mux_con & CON_IOMUX_PWM0SEL_MASK)
533 rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
534 GPIO3C5_PWM10 << GPIO3C5_SHIFT);
536 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
537 GPIO0D2_PWM0 << GPIO0D2_SHIFT);
540 if (mux_con & CON_IOMUX_PWM1SEL_MASK)
541 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
542 GPIO0D6_PWM11 << GPIO0D6_SHIFT);
544 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
545 GPIO0D3_PWM1 << GPIO0D3_SHIFT);
548 if (mux_con & CON_IOMUX_PWM2SEL_MASK)
549 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
550 GPIO1B4_PWM12 << GPIO1B4_SHIFT);
552 rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
553 GPIO0D4_PWM2 << GPIO0D4_SHIFT);
556 if (mux_con & CON_IOMUX_PWM3SEL_MASK)
557 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
558 GPIO1B3_PWM13 << GPIO1B3_SHIFT);
560 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
561 GPIO3D2_PWM3 << GPIO3D2_SHIFT);
564 debug("pwm id = %d iomux error!\n", pwm_id);
569 static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
573 rk_clrsetreg(&grf->gpio0a_iomux,
574 GPIO0A1_MASK | GPIO0A0_MASK,
575 GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
576 GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
580 rk_clrsetreg(&grf->gpio0a_iomux,
581 GPIO0A3_MASK | GPIO0A2_MASK,
582 GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
583 GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
586 rk_clrsetreg(&grf->gpio2c_iomux,
587 GPIO2C5_MASK | GPIO2C4_MASK,
588 GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
589 GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
592 rk_clrsetreg(&grf->gpio0a_iomux,
593 GPIO0A7_MASK | GPIO0A6_MASK,
594 GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
595 GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
601 static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
605 rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
606 GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
609 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
610 GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
613 rk_clrsetreg(&grf->gpio0b_iomux,
614 GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
615 GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
616 GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
617 GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
620 static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
622 u32 mux_con = readl(&grf->con_iomux);
625 case PERIPH_ID_UART1:
626 if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
627 rk_clrsetreg(&grf->gpio1b_iomux,
628 GPIO1B1_MASK | GPIO1B2_MASK,
629 GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
630 GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
632 case PERIPH_ID_UART2:
633 if (mux_con & CON_IOMUX_UART2SEL_MASK)
634 rk_clrsetreg(&grf->gpio1b_iomux,
635 GPIO1B1_MASK | GPIO1B2_MASK,
636 GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
637 GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
639 rk_clrsetreg(&grf->gpio1c_iomux,
640 GPIO1C3_MASK | GPIO1C2_MASK,
641 GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
642 GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
647 static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
651 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
652 GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
653 GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
654 GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
655 GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
656 GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
657 GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
658 GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
659 GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
660 rk_clrsetreg(&grf->gpio2a_iomux,
661 GPIO2A5_MASK | GPIO2A7_MASK,
662 GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
663 GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
664 rk_clrsetreg(&grf->gpio1c_iomux,
665 GPIO1C6_MASK | GPIO1C7_MASK,
666 GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
667 GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
669 case PERIPH_ID_SDCARD:
670 rk_clrsetreg(&grf->gpio1b_iomux,
671 GPIO1B6_MASK | GPIO1B7_MASK,
672 GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
673 GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
674 rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
675 GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
676 GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
677 GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
678 GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
679 GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
680 GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
685 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
686 static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
690 /* set rgmii pins mux */
691 rk_clrsetreg(&grf->gpio2b_iomux,
698 GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
699 GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
700 GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
701 GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
702 GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
703 GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
705 rk_clrsetreg(&grf->gpio2c_iomux,
714 GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
715 GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
716 GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
717 GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
718 GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
719 GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
720 GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
721 GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
723 rk_clrsetreg(&grf->gpio2d_iomux,
725 GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
728 * set rgmii tx pins to 12ma drive-strength,
729 * clean others with 2ma.
731 rk_clrsetreg(&grf->gpio2_e[1],
738 GPIO_BIAS_2MA << GRF_GPIO2B0_E_SHIFT |
739 GPIO_BIAS_12MA << GRF_GPIO2B1_E_SHIFT |
740 GPIO_BIAS_2MA << GRF_GPIO2B3_E_SHIFT |
741 GPIO_BIAS_2MA << GRF_GPIO2B4_E_SHIFT |
742 GPIO_BIAS_12MA << GRF_GPIO2B5_E_SHIFT |
743 GPIO_BIAS_2MA << GRF_GPIO2B6_E_SHIFT);
745 rk_clrsetreg(&grf->gpio2_e[2],
754 GPIO_BIAS_2MA << GRF_GPIO2C0_E_SHIFT |
755 GPIO_BIAS_2MA << GRF_GPIO2C1_E_SHIFT |
756 GPIO_BIAS_12MA << GRF_GPIO2C2_E_SHIFT |
757 GPIO_BIAS_12MA << GRF_GPIO2C3_E_SHIFT |
758 GPIO_BIAS_2MA << GRF_GPIO2C4_E_SHIFT |
759 GPIO_BIAS_2MA << GRF_GPIO2C5_E_SHIFT |
760 GPIO_BIAS_12MA << GRF_GPIO2C6_E_SHIFT |
761 GPIO_BIAS_12MA << GRF_GPIO2C7_E_SHIFT);
763 rk_clrsetreg(&grf->gpio2_e[3],
765 GPIO_BIAS_2MA << GRF_GPIO2D1_E_SHIFT);
768 debug("gmac id = %d iomux error!\n", gmac_id);
774 static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
776 struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
778 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
784 pinctrl_rk322x_pwm_config(priv->grf, func);
789 pinctrl_rk322x_i2c_config(priv->grf, func);
792 pinctrl_rk322x_spi_config(priv->grf, flags);
794 case PERIPH_ID_UART0:
795 case PERIPH_ID_UART1:
796 case PERIPH_ID_UART2:
797 pinctrl_rk322x_uart_config(priv->grf, func);
799 case PERIPH_ID_SDMMC0:
800 case PERIPH_ID_SDMMC1:
801 pinctrl_rk322x_sdmmc_config(priv->grf, func);
803 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
805 pinctrl_rk322x_gmac_config(priv->grf, func);
815 static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
816 struct udevice *periph)
821 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
822 "interrupts", cell, ARRAY_SIZE(cell));
828 return PERIPH_ID_SDCARD;
830 return PERIPH_ID_EMMC;
832 return PERIPH_ID_I2C0;
834 return PERIPH_ID_I2C1;
836 return PERIPH_ID_I2C2;
838 return PERIPH_ID_SPI0;
840 return PERIPH_ID_PWM0;
842 return PERIPH_ID_UART0;
844 return PERIPH_ID_UART1;
846 return PERIPH_ID_UART2;
847 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
849 return PERIPH_ID_GMAC;
855 static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
856 struct udevice *periph)
860 func = rk322x_pinctrl_get_periph_id(dev, periph);
863 return rk322x_pinctrl_request(dev, func, 0);
866 static struct pinctrl_ops rk322x_pinctrl_ops = {
867 .set_state_simple = rk322x_pinctrl_set_state_simple,
868 .request = rk322x_pinctrl_request,
869 .get_periph_id = rk322x_pinctrl_get_periph_id,
872 static int rk322x_pinctrl_probe(struct udevice *dev)
874 struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
876 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
877 debug("%s: grf=%p\n", __func__, priv->grf);
881 static const struct udevice_id rk322x_pinctrl_ids[] = {
882 { .compatible = "rockchip,rk3228-pinctrl" },
886 U_BOOT_DRIVER(pinctrl_rk3228) = {
887 .name = "pinctrl_rk3228",
888 .id = UCLASS_PINCTRL,
889 .of_match = rk322x_pinctrl_ids,
890 .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
891 .ops = &rk322x_pinctrl_ops,
892 .bind = dm_scan_fdt_dev,
893 .probe = rk322x_pinctrl_probe,