git.sur5r.net Git - u-boot/blob - drivers/pinctrl/rockchip/pinctrl_rk3368.c

   1 /*
   2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   3  * Author: Andy Yan <andy.yan@rock-chips.com>
   4  * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/grf_rk3368.h>
  17 #include <asm/arch/periph.h>
  18 #include <dm/pinctrl.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /* PMUGRF_GPIO0B_IOMUX */
  23 enum {
  24         GPIO0B5_SHIFT           = 10,
  25         GPIO0B5_MASK            = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT),
  26         GPIO0B5_GPIO            = 0,
  27         GPIO0B5_SPI2_CSN0       = (2 << GPIO0B5_SHIFT),
  28
  29         GPIO0B4_SHIFT           = 8,
  30         GPIO0B4_MASK            = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT),
  31         GPIO0B4_GPIO            = 0,
  32         GPIO0B4_SPI2_CLK        = (2 << GPIO0B4_SHIFT),
  33
  34         GPIO0B3_SHIFT           = 6,
  35         GPIO0B3_MASK            = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT),
  36         GPIO0B3_GPIO            = 0,
  37         GPIO0B3_SPI2_TXD        = (2 << GPIO0B3_SHIFT),
  38
  39         GPIO0B2_SHIFT           = 4,
  40         GPIO0B2_MASK            = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT),
  41         GPIO0B2_GPIO            = 0,
  42         GPIO0B2_SPI2_RXD        = (2 << GPIO0B2_SHIFT),
  43 };
  44
  45 /*GRF_GPIO0C_IOMUX*/
  46 enum {
  47         GPIO0C7_SHIFT           = 14,
  48         GPIO0C7_MASK            = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
  49         GPIO0C7_GPIO            = 0,
  50         GPIO0C7_LCDC_D19        = (1 << GPIO0C7_SHIFT),
  51         GPIO0C7_TRACE_D9        = (2 << GPIO0C7_SHIFT),
  52         GPIO0C7_UART1_RTSN      = (3 << GPIO0C7_SHIFT),
  53
  54         GPIO0C6_SHIFT           = 12,
  55         GPIO0C6_MASK            = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
  56         GPIO0C6_GPIO            = 0,
  57         GPIO0C6_LCDC_D18        = (1 << GPIO0C6_SHIFT),
  58         GPIO0C6_TRACE_D8        = (2 << GPIO0C6_SHIFT),
  59         GPIO0C6_UART1_CTSN      = (3 << GPIO0C6_SHIFT),
  60
  61         GPIO0C5_SHIFT           = 10,
  62         GPIO0C5_MASK            = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
  63         GPIO0C5_GPIO            = 0,
  64         GPIO0C5_LCDC_D17        = (1 << GPIO0C5_SHIFT),
  65         GPIO0C5_TRACE_D7        = (2 << GPIO0C5_SHIFT),
  66         GPIO0C5_UART1_SOUT      = (3 << GPIO0C5_SHIFT),
  67
  68         GPIO0C4_SHIFT           = 8,
  69         GPIO0C4_MASK            = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
  70         GPIO0C4_GPIO            = 0,
  71         GPIO0C4_LCDC_D16        = (1 << GPIO0C4_SHIFT),
  72         GPIO0C4_TRACE_D6        = (2 << GPIO0C4_SHIFT),
  73         GPIO0C4_UART1_SIN       = (3 << GPIO0C4_SHIFT),
  74
  75         GPIO0C3_SHIFT           = 6,
  76         GPIO0C3_MASK            = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
  77         GPIO0C3_GPIO            = 0,
  78         GPIO0C3_LCDC_D15        = (1 << GPIO0C3_SHIFT),
  79         GPIO0C3_TRACE_D5        = (2 << GPIO0C3_SHIFT),
  80         GPIO0C3_MCU_JTAG_TDO    = (3 << GPIO0C3_SHIFT),
  81
  82         GPIO0C2_SHIFT           = 4,
  83         GPIO0C2_MASK            = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
  84         GPIO0C2_GPIO            = 0,
  85         GPIO0C2_LCDC_D14        = (1 << GPIO0C2_SHIFT),
  86         GPIO0C2_TRACE_D4        = (2 << GPIO0C2_SHIFT),
  87         GPIO0C2_MCU_JTAG_TDI    = (3 << GPIO0C2_SHIFT),
  88
  89         GPIO0C1_SHIFT           = 2,
  90         GPIO0C1_MASK            = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
  91         GPIO0C1_GPIO            = 0,
  92         GPIO0C1_LCDC_D13        = (1 << GPIO0C1_SHIFT),
  93         GPIO0C1_TRACE_D3        = (2 << GPIO0C1_SHIFT),
  94         GPIO0C1_MCU_JTAG_TRTSN  = (3 << GPIO0C1_SHIFT),
  95
  96         GPIO0C0_SHIFT           = 0,
  97         GPIO0C0_MASK            = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
  98         GPIO0C0_GPIO            = 0,
  99         GPIO0C0_LCDC_D12        = (1 << GPIO0C0_SHIFT),
 100         GPIO0C0_TRACE_D2        = (2 << GPIO0C0_SHIFT),
 101         GPIO0C0_MCU_JTAG_TDO    = (3 << GPIO0C0_SHIFT),
 102 };
 103
 104 /*GRF_GPIO0D_IOMUX*/
 105 enum {
 106         GPIO0D7_SHIFT           = 14,
 107         GPIO0D7_MASK            = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
 108         GPIO0D7_GPIO            = 0,
 109         GPIO0D7_LCDC_DCLK       = (1 << GPIO0D7_SHIFT),
 110         GPIO0D7_TRACE_CTL       = (2 << GPIO0D7_SHIFT),
 111         GPIO0D7_PMU_DEBUG5      = (3 << GPIO0D7_SHIFT),
 112
 113         GPIO0D6_SHIFT           = 12,
 114         GPIO0D6_MASK            = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
 115         GPIO0D6_GPIO            = 0,
 116         GPIO0D6_LCDC_DEN        = (1 << GPIO0D6_SHIFT),
 117         GPIO0D6_TRACE_CLK       = (2 << GPIO0D6_SHIFT),
 118         GPIO0D6_PMU_DEBUG4      = (3 << GPIO0D6_SHIFT),
 119
 120         GPIO0D5_SHIFT           = 10,
 121         GPIO0D5_MASK            = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
 122         GPIO0D5_GPIO            = 0,
 123         GPIO0D5_LCDC_VSYNC      = (1 << GPIO0D5_SHIFT),
 124         GPIO0D5_TRACE_D15       = (2 << GPIO0D5_SHIFT),
 125         GPIO0D5_PMU_DEBUG3      = (3 << GPIO0D5_SHIFT),
 126
 127         GPIO0D4_SHIFT           = 8,
 128         GPIO0D4_MASK            = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
 129         GPIO0D4_GPIO            = 0,
 130         GPIO0D4_LCDC_HSYNC      = (1 << GPIO0D4_SHIFT),
 131         GPIO0D4_TRACE_D14       = (2 << GPIO0D4_SHIFT),
 132         GPIO0D4_PMU_DEBUG2      = (3 << GPIO0D4_SHIFT),
 133
 134         GPIO0D3_SHIFT           = 6,
 135         GPIO0D3_MASK            = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
 136         GPIO0D3_GPIO            = 0,
 137         GPIO0D3_LCDC_D23        = (1 << GPIO0D3_SHIFT),
 138         GPIO0D3_TRACE_D13       = (2 << GPIO0D3_SHIFT),
 139         GPIO0D3_UART4_SIN       = (3 << GPIO0D3_SHIFT),
 140
 141         GPIO0D2_SHIFT           = 4,
 142         GPIO0D2_MASK            = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
 143         GPIO0D2_GPIO            = 0,
 144         GPIO0D2_LCDC_D22        = (1 << GPIO0D2_SHIFT),
 145         GPIO0D2_TRACE_D12       = (2 << GPIO0D2_SHIFT),
 146         GPIO0D2_UART4_SOUT      = (3 << GPIO0D2_SHIFT),
 147
 148         GPIO0D1_SHIFT           = 2,
 149         GPIO0D1_MASK            = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
 150         GPIO0D1_GPIO            = 0,
 151         GPIO0D1_LCDC_D21        = (1 << GPIO0D1_SHIFT),
 152         GPIO0D1_TRACE_D11       = (2 << GPIO0D1_SHIFT),
 153         GPIO0D1_UART4_RTSN      = (3 << GPIO0D1_SHIFT),
 154
 155         GPIO0D0_SHIFT           = 0,
 156         GPIO0D0_MASK            = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
 157         GPIO0D0_GPIO            = 0,
 158         GPIO0D0_LCDC_D20        = (1 << GPIO0D0_SHIFT),
 159         GPIO0D0_TRACE_D10       = (2 << GPIO0D0_SHIFT),
 160         GPIO0D0_UART4_CTSN      = (3 << GPIO0D0_SHIFT),
 161 };
 162
 163 /*GRF_GPIO2A_IOMUX*/
 164 enum {
 165         GPIO2A7_SHIFT           = 14,
 166         GPIO2A7_MASK            = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
 167         GPIO2A7_GPIO            = 0,
 168         GPIO2A7_SDMMC0_D2       = (1 << GPIO2A7_SHIFT),
 169         GPIO2A7_JTAG_TCK        = (2 << GPIO2A7_SHIFT),
 170
 171         GPIO2A6_SHIFT           = 12,
 172         GPIO2A6_MASK            = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
 173         GPIO2A6_GPIO            = 0,
 174         GPIO2A6_SDMMC0_D1       = (1 << GPIO2A6_SHIFT),
 175         GPIO2A6_UART2_SIN       = (2 << GPIO2A6_SHIFT),
 176
 177         GPIO2A5_SHIFT           = 10,
 178         GPIO2A5_MASK            = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
 179         GPIO2A5_GPIO            = 0,
 180         GPIO2A5_SDMMC0_D0       = (1 << GPIO2A5_SHIFT),
 181         GPIO2A5_UART2_SOUT      = (2 << GPIO2A5_SHIFT),
 182
 183         GPIO2A4_SHIFT           = 8,
 184         GPIO2A4_MASK            = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
 185         GPIO2A4_GPIO            = 0,
 186         GPIO2A4_FLASH_DQS       = (1 << GPIO2A4_SHIFT),
 187         GPIO2A4_EMMC_CLKOUT     = (2 << GPIO2A4_SHIFT),
 188
 189         GPIO2A3_SHIFT           = 6,
 190         GPIO2A3_MASK            = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
 191         GPIO2A3_GPIO            = 0,
 192         GPIO2A3_FLASH_CSN3      = (1 << GPIO2A3_SHIFT),
 193         GPIO2A3_EMMC_RSTNOUT    = (2 << GPIO2A3_SHIFT),
 194
 195         GPIO2A2_SHIFT           = 4,
 196         GPIO2A2_MASK            = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
 197         GPIO2A2_GPIO            = 0,
 198         GPIO2A2_FLASH_CSN2      = (1 << GPIO2A2_SHIFT),
 199
 200         GPIO2A1_SHIFT           = 2,
 201         GPIO2A1_MASK            = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
 202         GPIO2A1_GPIO            = 0,
 203         GPIO2A1_FLASH_CSN1      = (1 << GPIO2A1_SHIFT),
 204
 205         GPIO2A0_SHIFT           = 0,
 206         GPIO2A0_MASK            = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
 207         GPIO2A0_GPIO            = 0,
 208         GPIO2A0_FLASH_CSN0      = (1 << GPIO2A0_SHIFT),
 209 };
 210
 211 /*GRF_GPIO2D_IOMUX*/
 212 enum {
 213         GPIO2D7_SHIFT           = 14,
 214         GPIO2D7_MASK            = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
 215         GPIO2D7_GPIO            = 0,
 216         GPIO2D7_SDIO0_D3        = (1 << GPIO2D7_SHIFT),
 217
 218         GPIO2D6_SHIFT           = 12,
 219         GPIO2D6_MASK            = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
 220         GPIO2D6_GPIO            = 0,
 221         GPIO2D6_SDIO0_D2        = (1 << GPIO2D6_SHIFT),
 222
 223         GPIO2D5_SHIFT           = 10,
 224         GPIO2D5_MASK            = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
 225         GPIO2D5_GPIO            = 0,
 226         GPIO2D5_SDIO0_D1        = (1 << GPIO2D5_SHIFT),
 227
 228         GPIO2D4_SHIFT           = 8,
 229         GPIO2D4_MASK            = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
 230         GPIO2D4_GPIO            = 0,
 231         GPIO2D4_SDIO0_D0        = (1 << GPIO2D4_SHIFT),
 232
 233         GPIO2D3_SHIFT           = 6,
 234         GPIO2D3_MASK            = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
 235         GPIO2D3_GPIO            = 0,
 236         GPIO2D3_UART0_RTS0      = (1 << GPIO2D3_SHIFT),
 237
 238         GPIO2D2_SHIFT           = 4,
 239         GPIO2D2_MASK            = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
 240         GPIO2D2_GPIO            = 0,
 241         GPIO2D2_UART0_CTS0      = (1 << GPIO2D2_SHIFT),
 242
 243         GPIO2D1_SHIFT           = 2,
 244         GPIO2D1_MASK            = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
 245         GPIO2D1_GPIO            = 0,
 246         GPIO2D1_UART0_SOUT      = (1 << GPIO2D1_SHIFT),
 247
 248         GPIO2D0_SHIFT           = 0,
 249         GPIO2D0_MASK            = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
 250         GPIO2D0_GPIO            = 0,
 251         GPIO2D0_UART0_SIN       = (1 << GPIO2D0_SHIFT),
 252 };
 253
 254 /* GRF_GPIO1B_IOMUX */
 255 enum {
 256         GPIO1B7_SHIFT           = 14,
 257         GPIO1B7_MASK            = GENMASK(GPIO1B7_SHIFT + 1, GPIO1B7_SHIFT),
 258         GPIO1B7_GPIO            = 0,
 259         GPIO1B7_SPI1_CSN0       = (2 << GPIO1B7_SHIFT),
 260
 261         GPIO1B6_SHIFT           = 12,
 262         GPIO1B6_MASK            = GENMASK(GPIO1B6_SHIFT + 1, GPIO1B6_SHIFT),
 263         GPIO1B6_GPIO            = 0,
 264         GPIO1B6_SPI1_CLK        = (2 << GPIO1B6_SHIFT),
 265 };
 266
 267 /* GRF_GPIO1C_IOMUX */
 268 enum {
 269         GPIO1C7_SHIFT           = 14,
 270         GPIO1C7_MASK            = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
 271         GPIO1C7_GPIO            = 0,
 272         GPIO1C7_EMMC_DATA5      = (2 << GPIO1C7_SHIFT),
 273         GPIO1C7_SPI0_TXD        = (3 << GPIO1C7_SHIFT),
 274
 275         GPIO1C6_SHIFT           = 12,
 276         GPIO1C6_MASK            = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
 277         GPIO1C6_GPIO            = 0,
 278         GPIO1C6_EMMC_DATA4      = (2 << GPIO1C6_SHIFT),
 279         GPIO1C6_SPI0_RXD        = (3 << GPIO1C6_SHIFT),
 280
 281         GPIO1C5_SHIFT           = 10,
 282         GPIO1C5_MASK            = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
 283         GPIO1C5_GPIO            = 0,
 284         GPIO1C5_EMMC_DATA3      = (2 << GPIO1C5_SHIFT),
 285
 286         GPIO1C4_SHIFT           = 8,
 287         GPIO1C4_MASK            = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
 288         GPIO1C4_GPIO            = 0,
 289         GPIO1C4_EMMC_DATA2      = (2 << GPIO1C4_SHIFT),
 290
 291         GPIO1C3_SHIFT           = 6,
 292         GPIO1C3_MASK            = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
 293         GPIO1C3_GPIO            = 0,
 294         GPIO1C3_EMMC_DATA1      = (2 << GPIO1C3_SHIFT),
 295
 296         GPIO1C2_SHIFT           = 4,
 297         GPIO1C2_MASK            = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
 298         GPIO1C2_GPIO            = 0,
 299         GPIO1C2_EMMC_DATA0      = (2 << GPIO1C2_SHIFT),
 300
 301         GPIO1C1_SHIFT           = 2,
 302         GPIO1C1_MASK            = GENMASK(GPIO1C1_SHIFT + 1, GPIO1C1_SHIFT),
 303         GPIO1C1_GPIO            = 0,
 304         GPIO1C1_SPI1_RXD        = (2 << GPIO1C1_SHIFT),
 305
 306         GPIO1C0_SHIFT           = 0,
 307         GPIO1C0_MASK            = GENMASK(GPIO1C0_SHIFT + 1, GPIO1C0_SHIFT),
 308         GPIO1C0_GPIO            = 0,
 309         GPIO1C0_SPI1_TXD        = (2 << GPIO1C0_SHIFT),
 310 };
 311
 312 /* GRF_GPIO1D_IOMUX*/
 313 enum {
 314         GPIO1D5_SHIFT           = 10,
 315         GPIO1D5_MASK            = GENMASK(GPIO1D5_SHIFT + 1, GPIO1D5_SHIFT),
 316         GPIO1D5_GPIO            = 0,
 317         GPIO1D5_SPI0_CLK        = (2 << GPIO1D5_SHIFT),
 318
 319         GPIO1D3_SHIFT           = 6,
 320         GPIO1D3_MASK            = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
 321         GPIO1D3_GPIO            = 0,
 322         GPIO1D3_EMMC_PWREN      = (2 << GPIO1D3_SHIFT),
 323
 324         GPIO1D2_SHIFT           = 4,
 325         GPIO1D2_MASK            = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
 326         GPIO1D2_GPIO            = 0,
 327         GPIO1D2_EMMC_CMD        = (2 << GPIO1D2_SHIFT),
 328
 329         GPIO1D1_SHIFT           = 2,
 330         GPIO1D1_MASK            = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
 331         GPIO1D1_GPIO            = 0,
 332         GPIO1D1_EMMC_DATA7      = (2 << GPIO1D1_SHIFT),
 333         GPIO1D1_SPI0_CSN1       = (3 << GPIO1D1_SHIFT),
 334
 335         GPIO1D0_SHIFT           = 0,
 336         GPIO1D0_MASK            = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
 337         GPIO1D0_GPIO            = 0,
 338         GPIO1D0_EMMC_DATA6      = (2 << GPIO1D0_SHIFT),
 339         GPIO1D0_SPI0_CSN0       = (3 << GPIO1D0_SHIFT),
 340 };
 341
 342
 343 /*GRF_GPIO3B_IOMUX*/
 344 enum {
 345         GPIO3B7_SHIFT           = 14,
 346         GPIO3B7_MASK            = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
 347         GPIO3B7_GPIO            = 0,
 348         GPIO3B7_MAC_RXD0        = (1 << GPIO3B7_SHIFT),
 349
 350         GPIO3B6_SHIFT           = 12,
 351         GPIO3B6_MASK            = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
 352         GPIO3B6_GPIO            = 0,
 353         GPIO3B6_MAC_TXD3        = (1 << GPIO3B6_SHIFT),
 354
 355         GPIO3B5_SHIFT           = 10,
 356         GPIO3B5_MASK            = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
 357         GPIO3B5_GPIO            = 0,
 358         GPIO3B5_MAC_TXEN        = (1 << GPIO3B5_SHIFT),
 359
 360         GPIO3B4_SHIFT           = 8,
 361         GPIO3B4_MASK            = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
 362         GPIO3B4_GPIO            = 0,
 363         GPIO3B4_MAC_COL         = (1 << GPIO3B4_SHIFT),
 364
 365         GPIO3B3_SHIFT           = 6,
 366         GPIO3B3_MASK            = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
 367         GPIO3B3_GPIO            = 0,
 368         GPIO3B3_MAC_CRS         = (1 << GPIO3B3_SHIFT),
 369
 370         GPIO3B2_SHIFT           = 4,
 371         GPIO3B2_MASK            = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
 372         GPIO3B2_GPIO            = 0,
 373         GPIO3B2_MAC_TXD2        = (1 << GPIO3B2_SHIFT),
 374
 375         GPIO3B1_SHIFT           = 2,
 376         GPIO3B1_MASK            = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
 377         GPIO3B1_GPIO            = 0,
 378         GPIO3B1_MAC_TXD1        = (1 << GPIO3B1_SHIFT),
 379
 380         GPIO3B0_SHIFT           = 0,
 381         GPIO3B0_MASK            = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
 382         GPIO3B0_GPIO            = 0,
 383         GPIO3B0_MAC_TXD0        = (1 << GPIO3B0_SHIFT),
 384         GPIO3B0_PWM0            = (2 << GPIO3B0_SHIFT),
 385 };
 386
 387 /*GRF_GPIO3C_IOMUX*/
 388 enum {
 389         GPIO3C6_SHIFT           = 12,
 390         GPIO3C6_MASK            = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
 391         GPIO3C6_GPIO            = 0,
 392         GPIO3C6_MAC_CLK         = (1 << GPIO3C6_SHIFT),
 393
 394         GPIO3C5_SHIFT           = 10,
 395         GPIO3C5_MASK            = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
 396         GPIO3C5_GPIO            = 0,
 397         GPIO3C5_MAC_RXEN        = (1 << GPIO3C5_SHIFT),
 398
 399         GPIO3C4_SHIFT           = 8,
 400         GPIO3C4_MASK            = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
 401         GPIO3C4_GPIO            = 0,
 402         GPIO3C4_MAC_RXDV        = (1 << GPIO3C4_SHIFT),
 403
 404         GPIO3C3_SHIFT           = 6,
 405         GPIO3C3_MASK            = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
 406         GPIO3C3_GPIO            = 0,
 407         GPIO3C3_MAC_MDC         = (1 << GPIO3C3_SHIFT),
 408
 409         GPIO3C2_SHIFT           = 4,
 410         GPIO3C2_MASK            = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
 411         GPIO3C2_GPIO            = 0,
 412         GPIO3C2_MAC_RXD3        = (1 << GPIO3C2_SHIFT),
 413
 414         GPIO3C1_SHIFT           = 2,
 415         GPIO3C1_MASK            = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
 416         GPIO3C1_GPIO            = 0,
 417         GPIO3C1_MAC_RXD2        = (1 << GPIO3C1_SHIFT),
 418
 419         GPIO3C0_SHIFT           = 0,
 420         GPIO3C0_MASK            = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
 421         GPIO3C0_GPIO            = 0,
 422         GPIO3C0_MAC_RXD1        = (1 << GPIO3C0_SHIFT),
 423 };
 424
 425 /*GRF_GPIO3D_IOMUX*/
 426 enum {
 427         GPIO3D4_SHIFT           = 8,
 428         GPIO3D4_MASK            = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
 429         GPIO3D4_GPIO            = 0,
 430         GPIO3D4_MAC_TXCLK       = (1 << GPIO3D4_SHIFT),
 431         GPIO3D4_SPI1_CNS1       = (2 << GPIO3D4_SHIFT),
 432
 433         GPIO3D1_SHIFT           = 2,
 434         GPIO3D1_MASK            = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
 435         GPIO3D1_GPIO            = 0,
 436         GPIO3D1_MAC_RXCLK       = (1 << GPIO3D1_SHIFT),
 437
 438         GPIO3D0_SHIFT           = 0,
 439         GPIO3D0_MASK            = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
 440         GPIO3D0_GPIO            = 0,
 441         GPIO3D0_MAC_MDIO        = (1 << GPIO3D0_SHIFT),
 442 };
 443
 444 struct rk3368_pinctrl_priv {
 445         struct rk3368_grf *grf;
 446         struct rk3368_pmu_grf *pmugrf;
 447 };
 448
 449 static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
 450                                        int uart_id)
 451 {
 452         struct rk3368_grf *grf = priv->grf;
 453         struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
 454
 455         switch (uart_id) {
 456         case PERIPH_ID_UART2:
 457                 rk_clrsetreg(&grf->gpio2a_iomux,
 458                              GPIO2A6_MASK | GPIO2A5_MASK,
 459                              GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
 460                 break;
 461         case PERIPH_ID_UART0:
 462                 break;
 463         case PERIPH_ID_UART1:
 464                 break;
 465         case PERIPH_ID_UART3:
 466                 break;
 467         case PERIPH_ID_UART4:
 468                 rk_clrsetreg(&pmugrf->gpio0d_iomux,
 469                              GPIO0D0_MASK | GPIO0D1_MASK |
 470                              GPIO0D2_MASK | GPIO0D3_MASK,
 471                              GPIO0D0_GPIO | GPIO0D1_GPIO |
 472                              GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
 473                 break;
 474         default:
 475                 debug("uart id = %d iomux error!\n", uart_id);
 476                 break;
 477         }
 478 }
 479
 480 static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv,
 481                                       int spi_id)
 482 {
 483         struct rk3368_grf *grf = priv->grf;
 484         struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
 485
 486         switch (spi_id) {
 487         case PERIPH_ID_SPI0:
 488                 /*
 489                  * eMMC can only be connected with 4 bits, when SPI0 is used.
 490                  * This is all-or-nothing, so we assume that if someone asks us
 491                  * to configure SPI0, that their eMMC interface is unused or
 492                  * configured appropriately.
 493                  */
 494                 rk_clrsetreg(&grf->gpio1d_iomux,
 495                              GPIO1D0_MASK | GPIO1D1_MASK |
 496                              GPIO1D5_MASK,
 497                              GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 |
 498                              GPIO1D5_SPI0_CLK);
 499                 rk_clrsetreg(&grf->gpio1c_iomux,
 500                              GPIO1C6_MASK | GPIO1C7_MASK,
 501                              GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD);
 502                 break;
 503         case PERIPH_ID_SPI1:
 504                 /*
 505                  * We don't implement support for configuring SPI1_CSN#1, as it
 506                  * conflicts with the GMAC (MAC TX clk-out).
 507                  */
 508                 rk_clrsetreg(&grf->gpio1b_iomux,
 509                              GPIO1B6_MASK | GPIO1B7_MASK,
 510                              GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0);
 511                 rk_clrsetreg(&grf->gpio1c_iomux,
 512                              GPIO1C0_MASK | GPIO1C1_MASK,
 513                              GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD);
 514                 break;
 515         case PERIPH_ID_SPI2:
 516                 rk_clrsetreg(&pmugrf->gpio0b_iomux,
 517                              GPIO0B2_MASK | GPIO0B3_MASK |
 518                              GPIO0B4_MASK | GPIO0B5_MASK,
 519                              GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD |
 520                              GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0);
 521                 break;
 522         default:
 523                 debug("%s: spi id = %d iomux error!\n", __func__, spi_id);
 524                 break;
 525         }
 526 }
 527
 528 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 529 static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
 530 {
 531         rk_clrsetreg(&grf->gpio3b_iomux,
 532                      GPIO3B0_MASK | GPIO3B1_MASK |
 533                      GPIO3B2_MASK | GPIO3B5_MASK |
 534                      GPIO3B6_MASK | GPIO3B7_MASK,
 535                      GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
 536                      GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
 537                      GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
 538         rk_clrsetreg(&grf->gpio3c_iomux,
 539                      GPIO3C0_MASK | GPIO3C1_MASK |
 540                      GPIO3C2_MASK | GPIO3C3_MASK |
 541                      GPIO3C4_MASK | GPIO3C5_MASK |
 542                      GPIO3C6_MASK,
 543                      GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
 544                      GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
 545                      GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
 546                      GPIO3C6_MAC_CLK);
 547         rk_clrsetreg(&grf->gpio3d_iomux,
 548                      GPIO3D0_MASK | GPIO3D1_MASK |
 549                      GPIO3D4_MASK,
 550                      GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
 551                      GPIO3D4_MAC_TXCLK);
 552 }
 553 #endif
 554
 555 static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
 556 {
 557         switch (mmc_id) {
 558         case PERIPH_ID_EMMC:
 559                 debug("mmc id = %d setting registers!\n", mmc_id);
 560                 rk_clrsetreg(&grf->gpio1c_iomux,
 561                              GPIO1C2_MASK | GPIO1C3_MASK |
 562                              GPIO1C4_MASK | GPIO1C5_MASK |
 563                              GPIO1C6_MASK | GPIO1C7_MASK,
 564                              GPIO1C2_EMMC_DATA0 |
 565                              GPIO1C3_EMMC_DATA1 |
 566                              GPIO1C4_EMMC_DATA2 |
 567                              GPIO1C5_EMMC_DATA3 |
 568                              GPIO1C6_EMMC_DATA4 |
 569                              GPIO1C7_EMMC_DATA5);
 570                 rk_clrsetreg(&grf->gpio1d_iomux,
 571                              GPIO1D0_MASK | GPIO1D1_MASK |
 572                              GPIO1D2_MASK | GPIO1D3_MASK,
 573                              GPIO1D0_EMMC_DATA6 |
 574                              GPIO1D1_EMMC_DATA7 |
 575                              GPIO1D2_EMMC_CMD |
 576                              GPIO1D3_EMMC_PWREN);
 577                 rk_clrsetreg(&grf->gpio2a_iomux,
 578                              GPIO2A3_MASK | GPIO2A4_MASK,
 579                              GPIO2A3_EMMC_RSTNOUT |
 580                              GPIO2A4_EMMC_CLKOUT);
 581                 break;
 582         case PERIPH_ID_SDCARD:
 583                 /*
 584                  * We assume that the BROM has already set this up
 585                  * correctly for us and that there's nothing to do
 586                  * here.
 587                  */
 588                 break;
 589         default:
 590                 debug("mmc id = %d iomux error!\n", mmc_id);
 591                 break;
 592         }
 593 }
 594
 595 static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
 596 {
 597         struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
 598
 599         debug("%s: func=%d, flags=%x\n", __func__, func, flags);
 600         switch (func) {
 601         case PERIPH_ID_UART0:
 602         case PERIPH_ID_UART1:
 603         case PERIPH_ID_UART2:
 604         case PERIPH_ID_UART3:
 605         case PERIPH_ID_UART4:
 606                 pinctrl_rk3368_uart_config(priv, func);
 607                 break;
 608         case PERIPH_ID_SPI0:
 609         case PERIPH_ID_SPI1:
 610         case PERIPH_ID_SPI2:
 611                 pinctrl_rk3368_spi_config(priv, func);
 612                 break;
 613         case PERIPH_ID_EMMC:
 614         case PERIPH_ID_SDCARD:
 615                 pinctrl_rk3368_sdmmc_config(priv->grf, func);
 616                 break;
 617 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 618         case PERIPH_ID_GMAC:
 619                 pinctrl_rk3368_gmac_config(priv->grf, func);
 620                 break;
 621 #endif
 622         default:
 623                 return -EINVAL;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
 630                                         struct udevice *periph)
 631 {
 632         u32 cell[3];
 633         int ret;
 634
 635         ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
 636                                    "interrupts", cell, ARRAY_SIZE(cell));
 637         if (ret < 0)
 638                 return -EINVAL;
 639
 640         switch (cell[1]) {
 641         case 59:
 642                 return PERIPH_ID_UART4;
 643         case 58:
 644                 return PERIPH_ID_UART3;
 645         case 57:
 646                 return PERIPH_ID_UART2;
 647         case 56:
 648                 return PERIPH_ID_UART1;
 649         case 55:
 650                 return PERIPH_ID_UART0;
 651         case 44:
 652                 return PERIPH_ID_SPI0;
 653         case 45:
 654                 return PERIPH_ID_SPI1;
 655         case 41:
 656                 return PERIPH_ID_SPI2;
 657         case 35:
 658                 return PERIPH_ID_EMMC;
 659         case 32:
 660                 return PERIPH_ID_SDCARD;
 661 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 662         case 27:
 663                 return PERIPH_ID_GMAC;
 664 #endif
 665         }
 666
 667         return -ENOENT;
 668 }
 669
 670 static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
 671                                            struct udevice *periph)
 672 {
 673         int func;
 674
 675         func = rk3368_pinctrl_get_periph_id(dev, periph);
 676         if (func < 0)
 677                 return func;
 678
 679         return rk3368_pinctrl_request(dev, func, 0);
 680 }
 681
 682 static struct pinctrl_ops rk3368_pinctrl_ops = {
 683         .set_state_simple       = rk3368_pinctrl_set_state_simple,
 684         .request        = rk3368_pinctrl_request,
 685         .get_periph_id  = rk3368_pinctrl_get_periph_id,
 686 };
 687
 688 static int rk3368_pinctrl_probe(struct udevice *dev)
 689 {
 690         struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
 691         int ret = 0;
 692
 693         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 694         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 695
 696         debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
 697
 698         return ret;
 699 }
 700
 701 static const struct udevice_id rk3368_pinctrl_ids[] = {
 702         { .compatible = "rockchip,rk3368-pinctrl" },
 703         { }
 704 };
 705
 706 U_BOOT_DRIVER(pinctrl_rk3368) = {
 707         .name           = "rockchip_rk3368_pinctrl",
 708         .id             = UCLASS_PINCTRL,
 709         .of_match       = rk3368_pinctrl_ids,
 710         .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
 711         .ops            = &rk3368_pinctrl_ops,
 712         .bind           = dm_scan_fdt_dev,
 713         .probe          = rk3368_pinctrl_probe,
 714 };