1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/grf_rv1108.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <dm/pinctrl.h>
17 struct rv1108_pinctrl_priv {
18 struct rv1108_grf *grf;
21 /* GRF_GPIO1B_IOMUX */
24 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
31 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
34 GPIO1B6_I2S_LRCLKTX_M0,
38 GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
45 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
52 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
59 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
66 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
78 /* GRF_GPIO1C_IOMUX */
81 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
87 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
90 GPIO1C6_I2S_LRCLKTX_M1,
93 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
99 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
105 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
111 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
114 GPIO1C2_I2S_SDIO3_M0,
118 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
128 GPIO1C0_I2S_LRCLKRX_M0,
131 /* GRF_GPIO1D_OIMUX */
134 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
140 GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
145 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
151 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
157 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
163 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
170 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
184 /* GRF_GPIO2A_IOMUX */
187 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
193 GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
199 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
205 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
211 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
215 GPIO2A3_SFC_HOLD_IO3,
218 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
225 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
232 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
239 /* GRF_GPIO2D_IOMUX */
242 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
248 GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
253 GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
258 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
265 GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
270 GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
275 GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
280 GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
285 /* GRF_GPIO2D_IOMUX */
288 GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
293 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
298 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
303 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
308 GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
313 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
315 GPIO2D2_UART2_SOUT_M0,
319 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
321 GPIO2D1_UART2_SIN_M0,
333 /* GRF_GPIO3A_IOMUX */
336 GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
340 GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
345 GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
350 GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
355 GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
360 GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
365 GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
375 /* GRF_GPIO3C_IOMUX */
378 GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
383 GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
388 GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
393 GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
398 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
401 GPIO3C3_UART2_SOUT_M1,
404 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
407 GPIO3C2_UART2_SIN_M1,
410 GPIOC1_MASK = 1 << GPIOC1_SHIFT,
420 static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
423 case PERIPH_ID_UART0:
424 rk_clrsetreg(&grf->gpio3a_iomux,
425 GPIO3A6_MASK | GPIO3A5_MASK,
426 GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
427 GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
429 case PERIPH_ID_UART1:
430 rk_clrsetreg(&grf->gpio1d_iomux,
431 GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK |
433 GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT |
434 GPIO1D2_UART0_SIN << GPIO1D2_SHIFT |
435 GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT |
436 GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT);
438 case PERIPH_ID_UART2:
439 rk_clrsetreg(&grf->gpio2d_iomux,
440 GPIO2D2_MASK | GPIO2D1_MASK,
441 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
442 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
447 static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func)
449 rk_clrsetreg(&grf->gpio1b_iomux,
450 GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK |
451 GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK,
452 GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT |
453 GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT |
454 GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT |
455 GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT |
456 GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT |
457 GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT);
458 rk_clrsetreg(&grf->gpio1c_iomux,
459 GPIO1C5_MASK | GPIO1C4_MASK |
460 GPIO1C3_MASK | GPIO1C2_MASK,
461 GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT |
462 GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT |
463 GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT |
464 GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT);
465 writel(0xffff57f5, &grf->gpio1b_drv);
468 static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf)
470 rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK |
471 GPIO2A1_MASK | GPIO2A0_MASK,
472 GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT |
473 GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT |
474 GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT |
475 GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT);
476 rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK,
477 GPIO2B7_SFC_CLK << GPIO2B7_SHIFT |
478 GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT);
481 static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags)
483 struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
486 case PERIPH_ID_UART0:
487 case PERIPH_ID_UART1:
488 case PERIPH_ID_UART2:
489 pinctrl_rv1108_uart_config(priv->grf, func);
492 pinctrl_rv1108_gmac_config(priv->grf, func);
494 pinctrl_rv1108_sfc_config(priv->grf);
502 static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
503 struct udevice *periph)
508 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
514 return PERIPH_ID_SDCARD;
516 return PERIPH_ID_EMMC;
518 return PERIPH_ID_GMAC;
520 return PERIPH_ID_I2C0;
522 return PERIPH_ID_I2C1;
524 return PERIPH_ID_I2C2;
526 return PERIPH_ID_PWM0;
528 return PERIPH_ID_UART0;
530 return PERIPH_ID_UART1;
532 return PERIPH_ID_UART2;
534 return PERIPH_ID_SFC;
540 static int rv1108_pinctrl_set_state_simple(struct udevice *dev,
541 struct udevice *periph)
545 func = rv1108_pinctrl_get_periph_id(dev, periph);
549 return rv1108_pinctrl_request(dev, func, 0);
552 static struct pinctrl_ops rv1108_pinctrl_ops = {
553 .set_state_simple = rv1108_pinctrl_set_state_simple,
554 .request = rv1108_pinctrl_request,
555 .get_periph_id = rv1108_pinctrl_get_periph_id,
558 static int rv1108_pinctrl_probe(struct udevice *dev)
560 struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
562 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
567 static const struct udevice_id rv1108_pinctrl_ids[] = {
568 {.compatible = "rockchip,rv1108-pinctrl" },
572 U_BOOT_DRIVER(pinctrl_rv1108) = {
573 .name = "pinctrl_rv1108",
574 .id = UCLASS_PINCTRL,
575 .of_match = rv1108_pinctrl_ids,
576 .priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv),
577 .ops = &rv1108_pinctrl_ops,
578 .bind = dm_scan_fdt_dev,
579 .probe = rv1108_pinctrl_probe,