1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
13 #include <asm/arch/pwm.h>
14 #include <asm/arch/gpio.h>
15 #include <power/regulator.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #define OSC_24MHZ 24000000
21 struct sunxi_pwm_priv {
22 struct sunxi_pwm *regs;
27 static const u32 prescaler_table[] = {
46 static int sunxi_pwm_config_pinmux(void)
48 #ifdef CONFIG_MACH_SUN50I
49 sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
54 static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
57 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
59 debug("%s: polarity=%u\n", __func__, polarity);
60 priv->invert = polarity;
65 static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
66 uint period_ns, uint duty_ns)
68 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
69 struct sunxi_pwm *regs = priv->regs;
71 u32 v, period = 0, duty;
73 const u32 nsecs_per_sec = 1000000000U;
75 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
77 for (prescaler = 0; prescaler < SUNXI_PWM_CTRL_PRESCALE0_MASK;
79 if (!prescaler_table[prescaler])
81 scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
82 period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
83 if (period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX)
87 if (period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
88 debug("%s: failed to find prescaler value\n", __func__);
92 duty = lldiv(scaled_freq * duty_ns, nsecs_per_sec);
94 if (priv->prescaler != prescaler) {
95 /* Mask clock to update prescaler */
96 v = readl(®s->ctrl);
97 v &= ~SUNXI_PWM_CTRL_CLK_GATE;
98 writel(v, ®s->ctrl);
99 v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
100 v |= (priv->prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
101 writel(v, ®s->ctrl);
102 v |= SUNXI_PWM_CTRL_CLK_GATE;
103 writel(v, ®s->ctrl);
104 priv->prescaler = prescaler;
107 writel(SUNXI_PWM_CH0_PERIOD_PRD(period) |
108 SUNXI_PWM_CH0_PERIOD_DUTY(duty), ®s->ch0_period);
110 debug("%s: prescaler: %d, period: %d, duty: %d\n",
111 __func__, priv->prescaler,
117 static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
119 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
120 struct sunxi_pwm *regs = priv->regs;
123 debug("%s: Enable '%s'\n", __func__, dev->name);
125 v = readl(®s->ctrl);
127 v &= ~SUNXI_PWM_CTRL_ENABLE0;
128 writel(v, ®s->ctrl);
132 sunxi_pwm_config_pinmux();
135 v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
137 v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
138 v |= SUNXI_PWM_CTRL_ENABLE0;
139 writel(v, ®s->ctrl);
144 static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
146 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
148 priv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);
153 static int sunxi_pwm_probe(struct udevice *dev)
158 static const struct pwm_ops sunxi_pwm_ops = {
159 .set_invert = sunxi_pwm_set_invert,
160 .set_config = sunxi_pwm_set_config,
161 .set_enable = sunxi_pwm_set_enable,
164 static const struct udevice_id sunxi_pwm_ids[] = {
165 { .compatible = "allwinner,sun5i-a13-pwm" },
166 { .compatible = "allwinner,sun50i-a64-pwm" },
170 U_BOOT_DRIVER(sunxi_pwm) = {
173 .of_match = sunxi_pwm_ids,
174 .ops = &sunxi_pwm_ops,
175 .ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata,
176 .probe = sunxi_pwm_probe,
177 .priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv),