2 * Copyright 2016 Google Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/pwm.h>
14 struct tegra_pwm_priv {
15 struct pwm_ctlr *regs;
18 static int tegra_pwm_set_config(struct udevice *dev, uint channel,
19 uint period_ns, uint duty_ns)
21 struct tegra_pwm_priv *priv = dev_get_priv(dev);
22 struct pwm_ctlr *regs = priv->regs;
28 debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
29 /* We ignore the period here and just use 32KHz */
30 clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
32 pulse_width = duty_ns * 255 / period_ns;
34 reg = pulse_width << PWM_WIDTH_SHIFT;
35 reg |= 1 << PWM_DIVIDER_SHIFT;
36 writel(reg, ®s[channel].control);
37 debug("%s: pulse_width=%u\n", __func__, pulse_width);
42 static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
44 struct tegra_pwm_priv *priv = dev_get_priv(dev);
45 struct pwm_ctlr *regs = priv->regs;
49 debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
50 clrsetbits_le32(®s[channel].control, PWM_ENABLE_MASK,
51 enable ? PWM_ENABLE_MASK : 0);
56 static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
58 struct tegra_pwm_priv *priv = dev_get_priv(dev);
60 priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
65 static const struct pwm_ops tegra_pwm_ops = {
66 .set_config = tegra_pwm_set_config,
67 .set_enable = tegra_pwm_set_enable,
70 static const struct udevice_id tegra_pwm_ids[] = {
71 { .compatible = "nvidia,tegra124-pwm" },
72 { .compatible = "nvidia,tegra20-pwm" },
76 U_BOOT_DRIVER(tegra_pwm) = {
79 .of_match = tegra_pwm_ids,
80 .ops = &tegra_pwm_ops,
81 .ofdata_to_platdata = tegra_pwm_ofdata_to_platdata,
82 .priv_auto_alloc_size = sizeof(struct tegra_pwm_priv),