2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
7 * SPDX-License-Identifier: GPL-2.0+
12 #include "asm/errno.h"
14 #include "linux/immap_qe.h"
17 #include <asm/arch/immap_ls102xa.h>
20 #define MPC85xx_DEVDISR_QE_DISABLE 0x1
22 qe_map_t *qe_immr = NULL;
23 static qe_snum_t snums[QE_NUM_OF_SNUM];
25 DECLARE_GLOBAL_DATA_PTR;
27 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
31 if (cmd == QE_RESET) {
32 out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
34 out_be32(&qe_immr->cp.cecdr, cmd_data);
35 out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
36 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
38 /* Wait for the QE_CR_FLG to clear */
40 cecr = in_be32(&qe_immr->cp.cecr);
41 } while (cecr & QE_CR_FLG);
47 uint qe_muram_alloc(uint size, uint align)
53 align_mask = align - 1;
54 savebase = gd->arch.mp_alloc_base;
56 off = gd->arch.mp_alloc_base & align_mask;
58 gd->arch.mp_alloc_base += (align - off);
60 if ((off = size & align_mask) != 0)
61 size += (align - off);
63 if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
64 gd->arch.mp_alloc_base = savebase;
65 printf("%s: ran out of ram.\n", __FUNCTION__);
68 retloc = gd->arch.mp_alloc_base;
69 gd->arch.mp_alloc_base += size;
71 memset((void *)&qe_immr->muram[retloc], 0, size);
73 __asm__ __volatile__("sync");
79 void *qe_muram_addr(uint offset)
81 return (void *)&qe_immr->muram[offset];
84 static void qe_sdma_init(void)
87 uint sdma_buffer_base;
89 p = (volatile sdma_t *)&qe_immr->sdma;
91 /* All of DMA transaction in bus 1 */
92 out_be32(&p->sdaqr, 0);
93 out_be32(&p->sdaqmr, 0);
95 /* Allocate 2KB temporary buffer for sdma */
96 sdma_buffer_base = qe_muram_alloc(2048, 4096);
97 out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
99 /* Clear sdma status */
100 out_be32(&p->sdsr, 0x03000000);
102 /* Enable global mode on bus 1, and 2KB buffer size */
103 out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
106 /* This table is a list of the serial numbers of the Threads, taken from the
107 * "SNUM Table" chart in the QE Reference Manual. The order is not important,
108 * we just need to know what the SNUMs are for the threads.
110 static u8 thread_snum[] = {
111 /* Evthreads 16-29 are not supported in MPC8309 */
112 #if !defined(CONFIG_MPC8309)
113 0x04, 0x05, 0x0c, 0x0d,
114 0x14, 0x15, 0x1c, 0x1d,
115 0x24, 0x25, 0x2c, 0x2d,
118 0x88, 0x89, 0x98, 0x99,
119 0xa8, 0xa9, 0xb8, 0xb9,
120 0xc8, 0xc9, 0xd8, 0xd9,
121 0xe8, 0xe9, 0x08, 0x09,
122 0x18, 0x19, 0x28, 0x29,
123 0x38, 0x39, 0x48, 0x49,
124 0x58, 0x59, 0x68, 0x69,
125 0x78, 0x79, 0x80, 0x81
128 static void qe_snums_init(void)
132 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
133 snums[i].state = QE_SNUM_STATE_FREE;
134 snums[i].num = thread_snum[i];
138 int qe_get_snum(void)
143 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
144 if (snums[i].state == QE_SNUM_STATE_FREE) {
145 snums[i].state = QE_SNUM_STATE_USED;
154 void qe_put_snum(u8 snum)
158 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
159 if (snums[i].num == snum) {
160 snums[i].state = QE_SNUM_STATE_FREE;
166 void qe_init(uint qe_base)
168 /* Init the QE IMMR base */
169 qe_immr = (qe_map_t *)qe_base;
171 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
173 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
175 qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
177 /* enable the microcode in IRAM */
178 out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
181 gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
182 gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
191 uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
192 qe_immr = (qe_map_t *)qe_base;
194 u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
195 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
200 void u_qe_resume(void)
203 uint qe_base = CONFIG_SYS_IMMR + QE_IMMR_OFFSET; /* QE immr base */
204 qe_immrr = (qe_map_t *)qe_base;
206 u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
207 out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
213 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
214 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
217 void qe_assign_page(uint snum, uint para_ram_base)
221 out_be32(&qe_immr->cp.cecdr, para_ram_base);
222 out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
223 | QE_CR_FLG | QE_ASSIGN_PAGE);
225 /* Wait for the QE_CR_FLG to clear */
227 cecr = in_be32(&qe_immr->cp.cecr);
228 } while (cecr & QE_CR_FLG );
234 * brg: 0~15 as BRG1~BRG16
236 * BRG input clock comes from the BRGCLK (internal clock generated from
237 the QE clock, it is one-half of the QE clock), If need the clock source
238 from CLKn pin, we have te change the function.
241 #define BRG_CLK (gd->arch.brg_clk)
244 int qe_set_brg(uint brg, uint rate)
250 if (brg >= QE_NUM_OF_BRGS)
252 bp = (uint *)&qe_immr->brg.brgc1;
255 divisor = (BRG_CLK / rate);
256 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
261 *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
262 __asm__ __volatile__("sync");
265 *bp |= QE_BRGC_DIV16;
266 __asm__ __volatile__("sync");
273 /* Set ethernet MII clock master
275 int qe_set_mii_clk_src(int ucc_num)
279 /* check if the UCC number is in range. */
280 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
281 printf("%s: ucc num not in ranges\n", __FUNCTION__);
285 cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
286 cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
287 cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
288 out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
293 /* Firmware information stored here for qe_get_firmware_info() */
294 static struct qe_firmware_info qe_firmware_info;
297 * Set to 1 if QE firmware has been uploaded, and therefore
298 * qe_firmware_info contains valid data.
300 static int qe_firmware_uploaded;
303 * Upload a QE microcode
305 * This function is a worker function for qe_upload_firmware(). It does
306 * the actual uploading of the microcode.
308 static void qe_upload_microcode(const void *base,
309 const struct qe_microcode *ucode)
311 const u32 *code = base + be32_to_cpu(ucode->code_offset);
314 if (ucode->major || ucode->minor || ucode->revision)
315 printf("QE: uploading microcode '%s' version %u.%u.%u\n",
316 (char *)ucode->id, (u16)ucode->major, (u16)ucode->minor,
317 (u16)ucode->revision);
319 printf("QE: uploading microcode '%s'\n", (char *)ucode->id);
321 /* Use auto-increment */
322 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
323 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
325 for (i = 0; i < be32_to_cpu(ucode->count); i++)
326 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
330 * Upload a microcode to the I-RAM at a specific address.
332 * See docs/README.qe_firmware for information on QE microcode uploading.
334 * Currently, only version 1 is supported, so the 'version' field must be
337 * The SOC model and revision are not validated, they are only displayed for
338 * informational purposes.
340 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
341 * all of the microcode structures, minus the CRC.
343 * 'length' is the size that the structure says it is, including the CRC.
345 int qe_upload_firmware(const struct qe_firmware *firmware)
350 size_t calc_size = sizeof(struct qe_firmware);
352 const struct qe_header *hdr;
353 #ifdef CONFIG_DEEP_SLEEP
354 #ifdef CONFIG_LS102XA
355 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
357 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
361 printf("Invalid address\n");
365 hdr = &firmware->header;
366 length = be32_to_cpu(hdr->length);
368 /* Check the magic */
369 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
370 (hdr->magic[2] != 'F')) {
371 printf("QE microcode not found\n");
372 #ifdef CONFIG_DEEP_SLEEP
373 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
378 /* Check the version */
379 if (hdr->version != 1) {
380 printf("Unsupported version\n");
384 /* Validate some of the fields */
385 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
386 printf("Invalid data\n");
390 /* Validate the length and check if there's a CRC */
391 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
393 for (i = 0; i < firmware->count; i++)
395 * For situations where the second RISC uses the same microcode
396 * as the first, the 'code_offset' and 'count' fields will be
397 * zero, so it's okay to add those.
399 calc_size += sizeof(u32) *
400 be32_to_cpu(firmware->microcode[i].count);
402 /* Validate the length */
403 if (length != calc_size + sizeof(u32)) {
404 printf("Invalid length\n");
409 * Validate the CRC. We would normally call crc32_no_comp(), but that
410 * function isn't available unless you turn on JFFS support.
412 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
413 if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
414 printf("Firmware CRC is invalid\n");
419 * If the microcode calls for it, split the I-RAM.
421 if (!firmware->split) {
422 out_be16(&qe_immr->cp.cercr,
423 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
426 if (firmware->soc.model)
427 printf("Firmware '%s' for %u V%u.%u\n",
428 firmware->id, be16_to_cpu(firmware->soc.model),
429 firmware->soc.major, firmware->soc.minor);
431 printf("Firmware '%s'\n", firmware->id);
434 * The QE only supports one microcode per RISC, so clear out all the
435 * saved microcode information and put in the new.
437 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
438 strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
439 qe_firmware_info.extended_modes = firmware->extended_modes;
440 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
441 sizeof(firmware->vtraps));
442 qe_firmware_uploaded = 1;
444 /* Loop through each microcode. */
445 for (i = 0; i < firmware->count; i++) {
446 const struct qe_microcode *ucode = &firmware->microcode[i];
448 /* Upload a microcode if it's present */
449 if (ucode->code_offset)
450 qe_upload_microcode(firmware, ucode);
452 /* Program the traps for this processor */
453 for (j = 0; j < 16; j++) {
454 u32 trap = be32_to_cpu(ucode->traps[j]);
457 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
461 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
469 * Upload a microcode to the I-RAM at a specific address.
471 * See docs/README.qe_firmware for information on QE microcode uploading.
473 * Currently, only version 1 is supported, so the 'version' field must be
476 * The SOC model and revision are not validated, they are only displayed for
477 * informational purposes.
479 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
480 * all of the microcode structures, minus the CRC.
482 * 'length' is the size that the structure says it is, including the CRC.
484 int u_qe_upload_firmware(const struct qe_firmware *firmware)
489 size_t calc_size = sizeof(struct qe_firmware);
491 const struct qe_header *hdr;
492 #ifdef CONFIG_DEEP_SLEEP
493 #ifdef CONFIG_LS102XA
494 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
496 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
500 printf("Invalid address\n");
504 hdr = &firmware->header;
505 length = be32_to_cpu(hdr->length);
507 /* Check the magic */
508 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
509 (hdr->magic[2] != 'F')) {
510 printf("Not a microcode\n");
511 #ifdef CONFIG_DEEP_SLEEP
512 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
517 /* Check the version */
518 if (hdr->version != 1) {
519 printf("Unsupported version\n");
523 /* Validate some of the fields */
524 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
525 printf("Invalid data\n");
529 /* Validate the length and check if there's a CRC */
530 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
532 for (i = 0; i < firmware->count; i++)
534 * For situations where the second RISC uses the same microcode
535 * as the first, the 'code_offset' and 'count' fields will be
536 * zero, so it's okay to add those.
538 calc_size += sizeof(u32) *
539 be32_to_cpu(firmware->microcode[i].count);
541 /* Validate the length */
542 if (length != calc_size + sizeof(u32)) {
543 printf("Invalid length\n");
548 * Validate the CRC. We would normally call crc32_no_comp(), but that
549 * function isn't available unless you turn on JFFS support.
551 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
552 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
553 printf("Firmware CRC is invalid\n");
558 * If the microcode calls for it, split the I-RAM.
560 if (!firmware->split) {
561 out_be16(&qe_immr->cp.cercr,
562 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
565 if (firmware->soc.model)
566 printf("Firmware '%s' for %u V%u.%u\n",
567 firmware->id, be16_to_cpu(firmware->soc.model),
568 firmware->soc.major, firmware->soc.minor);
570 printf("Firmware '%s'\n", firmware->id);
572 /* Loop through each microcode. */
573 for (i = 0; i < firmware->count; i++) {
574 const struct qe_microcode *ucode = &firmware->microcode[i];
576 /* Upload a microcode if it's present */
577 if (ucode->code_offset)
578 qe_upload_microcode(firmware, ucode);
580 /* Program the traps for this processor */
581 for (j = 0; j < 16; j++) {
582 u32 trap = be32_to_cpu(ucode->traps[j]);
585 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
589 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
597 int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
601 const struct qe_header *hdr;
603 #ifdef CONFIG_DEEP_SLEEP
605 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
607 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
614 hdr = &firmware->header;
616 /* Check the magic */
617 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
618 (hdr->magic[2] != 'F')) {
619 #ifdef CONFIG_DEEP_SLEEP
620 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
626 * If the microcode calls for it, split the I-RAM.
628 if (!firmware->split) {
629 out_be16(&qe_immrr->cp.cercr,
630 in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);
633 /* Loop through each microcode. */
634 for (i = 0; i < firmware->count; i++) {
635 const struct qe_microcode *ucode = &firmware->microcode[i];
637 /* Upload a microcode if it's present */
638 if (!ucode->code_offset)
641 code = (const void *)firmware + be32_to_cpu(ucode->code_offset);
643 /* Use auto-increment */
644 out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
645 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
647 for (i = 0; i < be32_to_cpu(ucode->count); i++)
648 out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));
650 /* Program the traps for this processor */
651 for (j = 0; j < 16; j++) {
652 u32 trap = be32_to_cpu(ucode->traps[j]);
655 out_be32(&qe_immrr->rsp[i].tibcr[j], trap);
659 out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
666 struct qe_firmware_info *qe_get_firmware_info(void)
668 return qe_firmware_uploaded ? &qe_firmware_info : NULL;
671 static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
676 return cmd_usage(cmdtp);
678 if (strcmp(argv[1], "fw") == 0) {
679 addr = simple_strtoul(argv[2], NULL, 16);
682 printf("Invalid address\n");
687 * If a length was supplied, compare that with the 'length'
692 ulong length = simple_strtoul(argv[3], NULL, 16);
693 struct qe_firmware *firmware = (void *) addr;
695 if (length != be32_to_cpu(firmware->header.length)) {
696 printf("Length mismatch\n");
701 return qe_upload_firmware((const struct qe_firmware *) addr);
704 return cmd_usage(cmdtp);
709 "QUICC Engine commands",
710 "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
712 "\twith optional length <length> verification."