1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
5 * Dave Liu <daveliu@freescale.com>
6 * based on source code of Shlomi Gridish
12 #include <linux/errno.h>
14 #include <linux/immap_qe.h>
16 #ifdef CONFIG_ARCH_LS1021A
17 #include <asm/arch/immap_ls102xa.h>
20 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
24 #define MPC85xx_DEVDISR_QE_DISABLE 0x1
26 qe_map_t *qe_immr = NULL;
28 static qe_snum_t snums[QE_NUM_OF_SNUM];
31 DECLARE_GLOBAL_DATA_PTR;
33 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
37 if (cmd == QE_RESET) {
38 out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
40 out_be32(&qe_immr->cp.cecdr, cmd_data);
41 out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
42 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
44 /* Wait for the QE_CR_FLG to clear */
46 cecr = in_be32(&qe_immr->cp.cecr);
47 } while (cecr & QE_CR_FLG);
53 uint qe_muram_alloc(uint size, uint align)
59 align_mask = align - 1;
60 savebase = gd->arch.mp_alloc_base;
62 off = gd->arch.mp_alloc_base & align_mask;
64 gd->arch.mp_alloc_base += (align - off);
66 if ((off = size & align_mask) != 0)
67 size += (align - off);
69 if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
70 gd->arch.mp_alloc_base = savebase;
71 printf("%s: ran out of ram.\n", __FUNCTION__);
74 retloc = gd->arch.mp_alloc_base;
75 gd->arch.mp_alloc_base += size;
77 memset((void *)&qe_immr->muram[retloc], 0, size);
79 __asm__ __volatile__("sync");
85 void *qe_muram_addr(uint offset)
87 return (void *)&qe_immr->muram[offset];
91 static void qe_sdma_init(void)
94 uint sdma_buffer_base;
96 p = (volatile sdma_t *)&qe_immr->sdma;
98 /* All of DMA transaction in bus 1 */
99 out_be32(&p->sdaqr, 0);
100 out_be32(&p->sdaqmr, 0);
102 /* Allocate 2KB temporary buffer for sdma */
103 sdma_buffer_base = qe_muram_alloc(2048, 4096);
104 out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
106 /* Clear sdma status */
107 out_be32(&p->sdsr, 0x03000000);
109 /* Enable global mode on bus 1, and 2KB buffer size */
110 out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
113 /* This table is a list of the serial numbers of the Threads, taken from the
114 * "SNUM Table" chart in the QE Reference Manual. The order is not important,
115 * we just need to know what the SNUMs are for the threads.
117 static u8 thread_snum[] = {
118 /* Evthreads 16-29 are not supported in MPC8309 */
119 #if !defined(CONFIG_MPC8309)
120 0x04, 0x05, 0x0c, 0x0d,
121 0x14, 0x15, 0x1c, 0x1d,
122 0x24, 0x25, 0x2c, 0x2d,
125 0x88, 0x89, 0x98, 0x99,
126 0xa8, 0xa9, 0xb8, 0xb9,
127 0xc8, 0xc9, 0xd8, 0xd9,
128 0xe8, 0xe9, 0x08, 0x09,
129 0x18, 0x19, 0x28, 0x29,
130 0x38, 0x39, 0x48, 0x49,
131 0x58, 0x59, 0x68, 0x69,
132 0x78, 0x79, 0x80, 0x81
135 static void qe_snums_init(void)
139 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
140 snums[i].state = QE_SNUM_STATE_FREE;
141 snums[i].num = thread_snum[i];
145 int qe_get_snum(void)
150 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
151 if (snums[i].state == QE_SNUM_STATE_FREE) {
152 snums[i].state = QE_SNUM_STATE_USED;
161 void qe_put_snum(u8 snum)
165 for (i = 0; i < QE_NUM_OF_SNUM; i++) {
166 if (snums[i].num == snum) {
167 snums[i].state = QE_SNUM_STATE_FREE;
173 void qe_init(uint qe_base)
175 /* Init the QE IMMR base */
176 qe_immr = (qe_map_t *)qe_base;
178 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
180 * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
182 qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
184 /* enable the microcode in IRAM */
185 out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
188 gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
189 gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
199 qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
201 void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
202 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
203 int dev = CONFIG_SYS_MMC_ENV_DEV;
204 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
205 u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
207 if (mmc_initialize(gd->bd)) {
208 printf("%s: mmc_initialize() failed\n", __func__);
211 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
212 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
216 printf("\nMMC cannot find device for ucode\n");
218 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
221 (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
225 if (!u_qe_upload_firmware(addr))
226 out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
227 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
234 void u_qe_resume(void)
238 qe_immrr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
239 u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
240 out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
246 qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
247 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
251 void qe_assign_page(uint snum, uint para_ram_base)
255 out_be32(&qe_immr->cp.cecdr, para_ram_base);
256 out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
257 | QE_CR_FLG | QE_ASSIGN_PAGE);
259 /* Wait for the QE_CR_FLG to clear */
261 cecr = in_be32(&qe_immr->cp.cecr);
262 } while (cecr & QE_CR_FLG );
269 * brg: 0~15 as BRG1~BRG16
271 * BRG input clock comes from the BRGCLK (internal clock generated from
272 the QE clock, it is one-half of the QE clock), If need the clock source
273 from CLKn pin, we have te change the function.
276 #define BRG_CLK (gd->arch.brg_clk)
279 int qe_set_brg(uint brg, uint rate)
285 if (brg >= QE_NUM_OF_BRGS)
287 bp = (uint *)&qe_immr->brg.brgc1;
290 divisor = (BRG_CLK / rate);
291 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
296 *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
297 __asm__ __volatile__("sync");
300 *bp |= QE_BRGC_DIV16;
301 __asm__ __volatile__("sync");
308 /* Set ethernet MII clock master
310 int qe_set_mii_clk_src(int ucc_num)
314 /* check if the UCC number is in range. */
315 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
316 printf("%s: ucc num not in ranges\n", __FUNCTION__);
320 cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
321 cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
322 cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
323 out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
328 /* Firmware information stored here for qe_get_firmware_info() */
329 static struct qe_firmware_info qe_firmware_info;
332 * Set to 1 if QE firmware has been uploaded, and therefore
333 * qe_firmware_info contains valid data.
335 static int qe_firmware_uploaded;
338 * Upload a QE microcode
340 * This function is a worker function for qe_upload_firmware(). It does
341 * the actual uploading of the microcode.
343 static void qe_upload_microcode(const void *base,
344 const struct qe_microcode *ucode)
346 const u32 *code = base + be32_to_cpu(ucode->code_offset);
349 if (ucode->major || ucode->minor || ucode->revision)
350 printf("QE: uploading microcode '%s' version %u.%u.%u\n",
351 (char *)ucode->id, (u16)ucode->major, (u16)ucode->minor,
352 (u16)ucode->revision);
354 printf("QE: uploading microcode '%s'\n", (char *)ucode->id);
356 /* Use auto-increment */
357 out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
358 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
360 for (i = 0; i < be32_to_cpu(ucode->count); i++)
361 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
365 * Upload a microcode to the I-RAM at a specific address.
367 * See docs/README.qe_firmware for information on QE microcode uploading.
369 * Currently, only version 1 is supported, so the 'version' field must be
372 * The SOC model and revision are not validated, they are only displayed for
373 * informational purposes.
375 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
376 * all of the microcode structures, minus the CRC.
378 * 'length' is the size that the structure says it is, including the CRC.
380 int qe_upload_firmware(const struct qe_firmware *firmware)
385 size_t calc_size = sizeof(struct qe_firmware);
387 const struct qe_header *hdr;
388 #ifdef CONFIG_DEEP_SLEEP
389 #ifdef CONFIG_ARCH_LS1021A
390 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
392 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
396 printf("Invalid address\n");
400 hdr = &firmware->header;
401 length = be32_to_cpu(hdr->length);
403 /* Check the magic */
404 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
405 (hdr->magic[2] != 'F')) {
406 printf("QE microcode not found\n");
407 #ifdef CONFIG_DEEP_SLEEP
408 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
413 /* Check the version */
414 if (hdr->version != 1) {
415 printf("Unsupported version\n");
419 /* Validate some of the fields */
420 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
421 printf("Invalid data\n");
425 /* Validate the length and check if there's a CRC */
426 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
428 for (i = 0; i < firmware->count; i++)
430 * For situations where the second RISC uses the same microcode
431 * as the first, the 'code_offset' and 'count' fields will be
432 * zero, so it's okay to add those.
434 calc_size += sizeof(u32) *
435 be32_to_cpu(firmware->microcode[i].count);
437 /* Validate the length */
438 if (length != calc_size + sizeof(u32)) {
439 printf("Invalid length\n");
444 * Validate the CRC. We would normally call crc32_no_comp(), but that
445 * function isn't available unless you turn on JFFS support.
447 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
448 if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
449 printf("Firmware CRC is invalid\n");
454 * If the microcode calls for it, split the I-RAM.
456 if (!firmware->split) {
457 out_be16(&qe_immr->cp.cercr,
458 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
461 if (firmware->soc.model)
462 printf("Firmware '%s' for %u V%u.%u\n",
463 firmware->id, be16_to_cpu(firmware->soc.model),
464 firmware->soc.major, firmware->soc.minor);
466 printf("Firmware '%s'\n", firmware->id);
469 * The QE only supports one microcode per RISC, so clear out all the
470 * saved microcode information and put in the new.
472 memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
473 strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
474 qe_firmware_info.extended_modes = firmware->extended_modes;
475 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
476 sizeof(firmware->vtraps));
477 qe_firmware_uploaded = 1;
479 /* Loop through each microcode. */
480 for (i = 0; i < firmware->count; i++) {
481 const struct qe_microcode *ucode = &firmware->microcode[i];
483 /* Upload a microcode if it's present */
484 if (ucode->code_offset)
485 qe_upload_microcode(firmware, ucode);
487 /* Program the traps for this processor */
488 for (j = 0; j < 16; j++) {
489 u32 trap = be32_to_cpu(ucode->traps[j]);
492 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
496 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
504 * Upload a microcode to the I-RAM at a specific address.
506 * See docs/README.qe_firmware for information on QE microcode uploading.
508 * Currently, only version 1 is supported, so the 'version' field must be
511 * The SOC model and revision are not validated, they are only displayed for
512 * informational purposes.
514 * 'calc_size' is the calculated size, in bytes, of the firmware structure and
515 * all of the microcode structures, minus the CRC.
517 * 'length' is the size that the structure says it is, including the CRC.
519 int u_qe_upload_firmware(const struct qe_firmware *firmware)
524 size_t calc_size = sizeof(struct qe_firmware);
526 const struct qe_header *hdr;
527 #ifdef CONFIG_DEEP_SLEEP
528 #ifdef CONFIG_ARCH_LS1021A
529 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
531 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
535 printf("Invalid address\n");
539 hdr = &firmware->header;
540 length = be32_to_cpu(hdr->length);
542 /* Check the magic */
543 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
544 (hdr->magic[2] != 'F')) {
545 printf("Not a microcode\n");
546 #ifdef CONFIG_DEEP_SLEEP
547 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
552 /* Check the version */
553 if (hdr->version != 1) {
554 printf("Unsupported version\n");
558 /* Validate some of the fields */
559 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
560 printf("Invalid data\n");
564 /* Validate the length and check if there's a CRC */
565 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
567 for (i = 0; i < firmware->count; i++)
569 * For situations where the second RISC uses the same microcode
570 * as the first, the 'code_offset' and 'count' fields will be
571 * zero, so it's okay to add those.
573 calc_size += sizeof(u32) *
574 be32_to_cpu(firmware->microcode[i].count);
576 /* Validate the length */
577 if (length != calc_size + sizeof(u32)) {
578 printf("Invalid length\n");
583 * Validate the CRC. We would normally call crc32_no_comp(), but that
584 * function isn't available unless you turn on JFFS support.
586 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
587 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
588 printf("Firmware CRC is invalid\n");
593 * If the microcode calls for it, split the I-RAM.
595 if (!firmware->split) {
596 out_be16(&qe_immr->cp.cercr,
597 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
600 if (firmware->soc.model)
601 printf("Firmware '%s' for %u V%u.%u\n",
602 firmware->id, be16_to_cpu(firmware->soc.model),
603 firmware->soc.major, firmware->soc.minor);
605 printf("Firmware '%s'\n", firmware->id);
607 /* Loop through each microcode. */
608 for (i = 0; i < firmware->count; i++) {
609 const struct qe_microcode *ucode = &firmware->microcode[i];
611 /* Upload a microcode if it's present */
612 if (ucode->code_offset)
613 qe_upload_microcode(firmware, ucode);
615 /* Program the traps for this processor */
616 for (j = 0; j < 16; j++) {
617 u32 trap = be32_to_cpu(ucode->traps[j]);
620 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
624 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
632 int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
636 const struct qe_header *hdr;
638 #ifdef CONFIG_DEEP_SLEEP
640 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
642 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
649 hdr = &firmware->header;
651 /* Check the magic */
652 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
653 (hdr->magic[2] != 'F')) {
654 #ifdef CONFIG_DEEP_SLEEP
655 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
661 * If the microcode calls for it, split the I-RAM.
663 if (!firmware->split) {
664 out_be16(&qe_immrr->cp.cercr,
665 in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);
668 /* Loop through each microcode. */
669 for (i = 0; i < firmware->count; i++) {
670 const struct qe_microcode *ucode = &firmware->microcode[i];
672 /* Upload a microcode if it's present */
673 if (!ucode->code_offset)
676 code = (const void *)firmware + be32_to_cpu(ucode->code_offset);
678 /* Use auto-increment */
679 out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
680 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
682 for (i = 0; i < be32_to_cpu(ucode->count); i++)
683 out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));
685 /* Program the traps for this processor */
686 for (j = 0; j < 16; j++) {
687 u32 trap = be32_to_cpu(ucode->traps[j]);
690 out_be32(&qe_immrr->rsp[i].tibcr[j], trap);
694 out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
701 struct qe_firmware_info *qe_get_firmware_info(void)
703 return qe_firmware_uploaded ? &qe_firmware_info : NULL;
706 static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
711 return cmd_usage(cmdtp);
713 if (strcmp(argv[1], "fw") == 0) {
714 addr = simple_strtoul(argv[2], NULL, 16);
717 printf("Invalid address\n");
722 * If a length was supplied, compare that with the 'length'
727 ulong length = simple_strtoul(argv[3], NULL, 16);
728 struct qe_firmware *firmware = (void *) addr;
730 if (length != be32_to_cpu(firmware->header.length)) {
731 printf("Length mismatch\n");
736 return qe_upload_firmware((const struct qe_firmware *) addr);
739 return cmd_usage(cmdtp);
744 "QUICC Engine commands",
745 "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
747 "\twith optional length <length> verification."