git.sur5r.net Git - u-boot/blob - drivers/qe/uec.c

   1 /*
   2  * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include "common.h"
  23 #include "net.h"
  24 #include "malloc.h"
  25 #include "asm/errno.h"
  26 #include "asm/io.h"
  27 #include "asm/immap_qe.h"
  28 #include "qe.h"
  29 #include "uccf.h"
  30 #include "uec.h"
  31 #include "uec_phy.h"
  32 #include "miiphy.h"
  33 #include <phy.h>
  34
  35 /* Default UTBIPAR SMI address */
  36 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
  37 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
  38 #endif
  39
  40 static uec_info_t uec_info[] = {
  41 #ifdef CONFIG_UEC_ETH1
  42         STD_UEC_INFO(1),        /* UEC1 */
  43 #endif
  44 #ifdef CONFIG_UEC_ETH2
  45         STD_UEC_INFO(2),        /* UEC2 */
  46 #endif
  47 #ifdef CONFIG_UEC_ETH3
  48         STD_UEC_INFO(3),        /* UEC3 */
  49 #endif
  50 #ifdef CONFIG_UEC_ETH4
  51         STD_UEC_INFO(4),        /* UEC4 */
  52 #endif
  53 #ifdef CONFIG_UEC_ETH5
  54         STD_UEC_INFO(5),        /* UEC5 */
  55 #endif
  56 #ifdef CONFIG_UEC_ETH6
  57         STD_UEC_INFO(6),        /* UEC6 */
  58 #endif
  59 #ifdef CONFIG_UEC_ETH7
  60         STD_UEC_INFO(7),        /* UEC7 */
  61 #endif
  62 #ifdef CONFIG_UEC_ETH8
  63         STD_UEC_INFO(8),        /* UEC8 */
  64 #endif
  65 };
  66
  67 #define MAXCONTROLLERS  (8)
  68
  69 static struct eth_device *devlist[MAXCONTROLLERS];
  70
  71 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
  72 {
  73         uec_t           *uec_regs;
  74         u32             maccfg1;
  75
  76         if (!uec) {
  77                 printf("%s: uec not initial\n", __FUNCTION__);
  78                 return -EINVAL;
  79         }
  80         uec_regs = uec->uec_regs;
  81
  82         maccfg1 = in_be32(&uec_regs->maccfg1);
  83
  84         if (mode & COMM_DIR_TX) {
  85                 maccfg1 |= MACCFG1_ENABLE_TX;
  86                 out_be32(&uec_regs->maccfg1, maccfg1);
  87                 uec->mac_tx_enabled = 1;
  88         }
  89
  90         if (mode & COMM_DIR_RX) {
  91                 maccfg1 |= MACCFG1_ENABLE_RX;
  92                 out_be32(&uec_regs->maccfg1, maccfg1);
  93                 uec->mac_rx_enabled = 1;
  94         }
  95
  96         return 0;
  97 }
  98
  99 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
 100 {
 101         uec_t           *uec_regs;
 102         u32             maccfg1;
 103
 104         if (!uec) {
 105                 printf("%s: uec not initial\n", __FUNCTION__);
 106                 return -EINVAL;
 107         }
 108         uec_regs = uec->uec_regs;
 109
 110         maccfg1 = in_be32(&uec_regs->maccfg1);
 111
 112         if (mode & COMM_DIR_TX) {
 113                 maccfg1 &= ~MACCFG1_ENABLE_TX;
 114                 out_be32(&uec_regs->maccfg1, maccfg1);
 115                 uec->mac_tx_enabled = 0;
 116         }
 117
 118         if (mode & COMM_DIR_RX) {
 119                 maccfg1 &= ~MACCFG1_ENABLE_RX;
 120                 out_be32(&uec_regs->maccfg1, maccfg1);
 121                 uec->mac_rx_enabled = 0;
 122         }
 123
 124         return 0;
 125 }
 126
 127 static int uec_graceful_stop_tx(uec_private_t *uec)
 128 {
 129         ucc_fast_t              *uf_regs;
 130         u32                     cecr_subblock;
 131         u32                     ucce;
 132
 133         if (!uec || !uec->uccf) {
 134                 printf("%s: No handle passed.\n", __FUNCTION__);
 135                 return -EINVAL;
 136         }
 137
 138         uf_regs = uec->uccf->uf_regs;
 139
 140         /* Clear the grace stop event */
 141         out_be32(&uf_regs->ucce, UCCE_GRA);
 142
 143         /* Issue host command */
 144         cecr_subblock =
 145                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 146         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
 147                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 148
 149         /* Wait for command to complete */
 150         do {
 151                 ucce = in_be32(&uf_regs->ucce);
 152         } while (! (ucce & UCCE_GRA));
 153
 154         uec->grace_stopped_tx = 1;
 155
 156         return 0;
 157 }
 158
 159 static int uec_graceful_stop_rx(uec_private_t *uec)
 160 {
 161         u32             cecr_subblock;
 162         u8              ack;
 163
 164         if (!uec) {
 165                 printf("%s: No handle passed.\n", __FUNCTION__);
 166                 return -EINVAL;
 167         }
 168
 169         if (!uec->p_rx_glbl_pram) {
 170                 printf("%s: No init rx global parameter\n", __FUNCTION__);
 171                 return -EINVAL;
 172         }
 173
 174         /* Clear acknowledge bit */
 175         ack = uec->p_rx_glbl_pram->rxgstpack;
 176         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
 177         uec->p_rx_glbl_pram->rxgstpack = ack;
 178
 179         /* Keep issuing cmd and checking ack bit until it is asserted */
 180         do {
 181                 /* Issue host command */
 182                 cecr_subblock =
 183                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 184                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
 185                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 186                 ack = uec->p_rx_glbl_pram->rxgstpack;
 187         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
 188
 189         uec->grace_stopped_rx = 1;
 190
 191         return 0;
 192 }
 193
 194 static int uec_restart_tx(uec_private_t *uec)
 195 {
 196         u32             cecr_subblock;
 197
 198         if (!uec || !uec->uec_info) {
 199                 printf("%s: No handle passed.\n", __FUNCTION__);
 200                 return -EINVAL;
 201         }
 202
 203         cecr_subblock =
 204          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 205         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
 206                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 207
 208         uec->grace_stopped_tx = 0;
 209
 210         return 0;
 211 }
 212
 213 static int uec_restart_rx(uec_private_t *uec)
 214 {
 215         u32             cecr_subblock;
 216
 217         if (!uec || !uec->uec_info) {
 218                 printf("%s: No handle passed.\n", __FUNCTION__);
 219                 return -EINVAL;
 220         }
 221
 222         cecr_subblock =
 223          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
 224         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
 225                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
 226
 227         uec->grace_stopped_rx = 0;
 228
 229         return 0;
 230 }
 231
 232 static int uec_open(uec_private_t *uec, comm_dir_e mode)
 233 {
 234         ucc_fast_private_t      *uccf;
 235
 236         if (!uec || !uec->uccf) {
 237                 printf("%s: No handle passed.\n", __FUNCTION__);
 238                 return -EINVAL;
 239         }
 240         uccf = uec->uccf;
 241
 242         /* check if the UCC number is in range. */
 243         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 244                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 245                 return -EINVAL;
 246         }
 247
 248         /* Enable MAC */
 249         uec_mac_enable(uec, mode);
 250
 251         /* Enable UCC fast */
 252         ucc_fast_enable(uccf, mode);
 253
 254         /* RISC microcode start */
 255         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
 256                 uec_restart_tx(uec);
 257         }
 258         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
 259                 uec_restart_rx(uec);
 260         }
 261
 262         return 0;
 263 }
 264
 265 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
 266 {
 267         ucc_fast_private_t      *uccf;
 268
 269         if (!uec || !uec->uccf) {
 270                 printf("%s: No handle passed.\n", __FUNCTION__);
 271                 return -EINVAL;
 272         }
 273         uccf = uec->uccf;
 274
 275         /* check if the UCC number is in range. */
 276         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
 277                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
 278                 return -EINVAL;
 279         }
 280         /* Stop any transmissions */
 281         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
 282                 uec_graceful_stop_tx(uec);
 283         }
 284         /* Stop any receptions */
 285         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
 286                 uec_graceful_stop_rx(uec);
 287         }
 288
 289         /* Disable the UCC fast */
 290         ucc_fast_disable(uec->uccf, mode);
 291
 292         /* Disable the MAC */
 293         uec_mac_disable(uec, mode);
 294
 295         return 0;
 296 }
 297
 298 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
 299 {
 300         uec_t           *uec_regs;
 301         u32             maccfg2;
 302
 303         if (!uec) {
 304                 printf("%s: uec not initial\n", __FUNCTION__);
 305                 return -EINVAL;
 306         }
 307         uec_regs = uec->uec_regs;
 308
 309         if (duplex == DUPLEX_HALF) {
 310                 maccfg2 = in_be32(&uec_regs->maccfg2);
 311                 maccfg2 &= ~MACCFG2_FDX;
 312                 out_be32(&uec_regs->maccfg2, maccfg2);
 313         }
 314
 315         if (duplex == DUPLEX_FULL) {
 316                 maccfg2 = in_be32(&uec_regs->maccfg2);
 317                 maccfg2 |= MACCFG2_FDX;
 318                 out_be32(&uec_regs->maccfg2, maccfg2);
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int uec_set_mac_if_mode(uec_private_t *uec,
 325                 phy_interface_t if_mode, int speed)
 326 {
 327         phy_interface_t         enet_if_mode;
 328         uec_info_t              *uec_info;
 329         uec_t                   *uec_regs;
 330         u32                     upsmr;
 331         u32                     maccfg2;
 332
 333         if (!uec) {
 334                 printf("%s: uec not initial\n", __FUNCTION__);
 335                 return -EINVAL;
 336         }
 337
 338         uec_info = uec->uec_info;
 339         uec_regs = uec->uec_regs;
 340         enet_if_mode = if_mode;
 341
 342         maccfg2 = in_be32(&uec_regs->maccfg2);
 343         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
 344
 345         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
 346         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
 347
 348         switch (speed) {
 349                 case SPEED_10:
 350                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 351                         switch (enet_if_mode) {
 352                                 case PHY_INTERFACE_MODE_MII:
 353                                         break;
 354                                 case PHY_INTERFACE_MODE_RGMII:
 355                                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
 356                                         break;
 357                                 case PHY_INTERFACE_MODE_RMII:
 358                                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
 359                                         break;
 360                                 default:
 361                                         return -EINVAL;
 362                                         break;
 363                         }
 364                         break;
 365                 case SPEED_100:
 366                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
 367                         switch (enet_if_mode) {
 368                                 case PHY_INTERFACE_MODE_MII:
 369                                         break;
 370                                 case PHY_INTERFACE_MODE_RGMII:
 371                                         upsmr |= UPSMR_RPM;
 372                                         break;
 373                                 case PHY_INTERFACE_MODE_RMII:
 374                                         upsmr |= UPSMR_RMM;
 375                                         break;
 376                                 default:
 377                                         return -EINVAL;
 378                                         break;
 379                         }
 380                         break;
 381                 case SPEED_1000:
 382                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 383                         switch (enet_if_mode) {
 384                                 case PHY_INTERFACE_MODE_GMII:
 385                                         break;
 386                                 case PHY_INTERFACE_MODE_TBI:
 387                                         upsmr |= UPSMR_TBIM;
 388                                         break;
 389                                 case PHY_INTERFACE_MODE_RTBI:
 390                                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 391                                         break;
 392                                 case PHY_INTERFACE_MODE_RGMII_RXID:
 393                                 case PHY_INTERFACE_MODE_RGMII_TXID:
 394                                 case PHY_INTERFACE_MODE_RGMII_ID:
 395                                 case PHY_INTERFACE_MODE_RGMII:
 396                                         upsmr |= UPSMR_RPM;
 397                                         break;
 398                                 case PHY_INTERFACE_MODE_SGMII:
 399                                         upsmr |= UPSMR_SGMM;
 400                                         break;
 401                                 default:
 402                                         return -EINVAL;
 403                                         break;
 404                         }
 405                         break;
 406                 default:
 407                         return -EINVAL;
 408                         break;
 409         }
 410
 411         out_be32(&uec_regs->maccfg2, maccfg2);
 412         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
 413
 414         return 0;
 415 }
 416
 417 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
 418 {
 419         uint            timeout = 0x1000;
 420         u32             miimcfg = 0;
 421
 422         miimcfg = in_be32(&uec_mii_regs->miimcfg);
 423         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
 424         out_be32(&uec_mii_regs->miimcfg, miimcfg);
 425
 426         /* Wait until the bus is free */
 427         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
 428         if (timeout <= 0) {
 429                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
 430                 return -ETIMEDOUT;
 431         }
 432
 433         return 0;
 434 }
 435
 436 static int init_phy(struct eth_device *dev)
 437 {
 438         uec_private_t           *uec;
 439         uec_mii_t               *umii_regs;
 440         struct uec_mii_info     *mii_info;
 441         struct phy_info         *curphy;
 442         int                     err;
 443
 444         uec = (uec_private_t *)dev->priv;
 445         umii_regs = uec->uec_mii_regs;
 446
 447         uec->oldlink = 0;
 448         uec->oldspeed = 0;
 449         uec->oldduplex = -1;
 450
 451         mii_info = malloc(sizeof(*mii_info));
 452         if (!mii_info) {
 453                 printf("%s: Could not allocate mii_info", dev->name);
 454                 return -ENOMEM;
 455         }
 456         memset(mii_info, 0, sizeof(*mii_info));
 457
 458         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 459                 mii_info->speed = SPEED_1000;
 460         } else {
 461                 mii_info->speed = SPEED_100;
 462         }
 463
 464         mii_info->duplex = DUPLEX_FULL;
 465         mii_info->pause = 0;
 466         mii_info->link = 1;
 467
 468         mii_info->advertising = (ADVERTISED_10baseT_Half |
 469                                 ADVERTISED_10baseT_Full |
 470                                 ADVERTISED_100baseT_Half |
 471                                 ADVERTISED_100baseT_Full |
 472                                 ADVERTISED_1000baseT_Full);
 473         mii_info->autoneg = 1;
 474         mii_info->mii_id = uec->uec_info->phy_address;
 475         mii_info->dev = dev;
 476
 477         mii_info->mdio_read = &uec_read_phy_reg;
 478         mii_info->mdio_write = &uec_write_phy_reg;
 479
 480         uec->mii_info = mii_info;
 481
 482         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
 483
 484         if (init_mii_management_configuration(umii_regs)) {
 485                 printf("%s: The MII Bus is stuck!", dev->name);
 486                 err = -1;
 487                 goto bus_fail;
 488         }
 489
 490         /* get info for this PHY */
 491         curphy = uec_get_phy_info(uec->mii_info);
 492         if (!curphy) {
 493                 printf("%s: No PHY found", dev->name);
 494                 err = -1;
 495                 goto no_phy;
 496         }
 497
 498         mii_info->phyinfo = curphy;
 499
 500         /* Run the commands which initialize the PHY */
 501         if (curphy->init) {
 502                 err = curphy->init(uec->mii_info);
 503                 if (err)
 504                         goto phy_init_fail;
 505         }
 506
 507         return 0;
 508
 509 phy_init_fail:
 510 no_phy:
 511 bus_fail:
 512         free(mii_info);
 513         return err;
 514 }
 515
 516 static void adjust_link(struct eth_device *dev)
 517 {
 518         uec_private_t           *uec = (uec_private_t *)dev->priv;
 519         uec_t                   *uec_regs;
 520         struct uec_mii_info     *mii_info = uec->mii_info;
 521
 522         extern void change_phy_interface_mode(struct eth_device *dev,
 523                                  phy_interface_t mode, int speed);
 524         uec_regs = uec->uec_regs;
 525
 526         if (mii_info->link) {
 527                 /* Now we make sure that we can be in full duplex mode.
 528                 * If not, we operate in half-duplex mode. */
 529                 if (mii_info->duplex != uec->oldduplex) {
 530                         if (!(mii_info->duplex)) {
 531                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
 532                                 printf("%s: Half Duplex\n", dev->name);
 533                         } else {
 534                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
 535                                 printf("%s: Full Duplex\n", dev->name);
 536                         }
 537                         uec->oldduplex = mii_info->duplex;
 538                 }
 539
 540                 if (mii_info->speed != uec->oldspeed) {
 541                         phy_interface_t mode =
 542                                 uec->uec_info->enet_interface_type;
 543                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
 544                                 switch (mii_info->speed) {
 545                                 case SPEED_1000:
 546                                         break;
 547                                 case SPEED_100:
 548                                         printf ("switching to rgmii 100\n");
 549                                         mode = PHY_INTERFACE_MODE_RGMII;
 550                                         break;
 551                                 case SPEED_10:
 552                                         printf ("switching to rgmii 10\n");
 553                                         mode = PHY_INTERFACE_MODE_RGMII;
 554                                         break;
 555                                 default:
 556                                         printf("%s: Ack,Speed(%d)is illegal\n",
 557                                                 dev->name, mii_info->speed);
 558                                         break;
 559                                 }
 560                         }
 561
 562                         /* change phy */
 563                         change_phy_interface_mode(dev, mode, mii_info->speed);
 564                         /* change the MAC interface mode */
 565                         uec_set_mac_if_mode(uec, mode, mii_info->speed);
 566
 567                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
 568                         uec->oldspeed = mii_info->speed;
 569                 }
 570
 571                 if (!uec->oldlink) {
 572                         printf("%s: Link is up\n", dev->name);
 573                         uec->oldlink = 1;
 574                 }
 575
 576         } else { /* if (mii_info->link) */
 577                 if (uec->oldlink) {
 578                         printf("%s: Link is down\n", dev->name);
 579                         uec->oldlink = 0;
 580                         uec->oldspeed = 0;
 581                         uec->oldduplex = -1;
 582                 }
 583         }
 584 }
 585
 586 static void phy_change(struct eth_device *dev)
 587 {
 588         uec_private_t   *uec = (uec_private_t *)dev->priv;
 589
 590 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
 591     defined(CONFIG_P1021) || defined(CONFIG_P1025)
 592         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 593
 594         /* QE9 and QE12 need to be set for enabling QE MII managment signals */
 595         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
 596         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 597 #endif
 598
 599         /* Update the link, speed, duplex */
 600         uec->mii_info->phyinfo->read_status(uec->mii_info);
 601
 602 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
 603     defined(CONFIG_P1021) || defined(CONFIG_P1025)
 604         /*
 605          * QE12 is muxed with LBCTL, it needs to be released for enabling
 606          * LBCTL signal for LBC usage.
 607          */
 608         clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
 609 #endif
 610
 611         /* Adjust the interface according to speed */
 612         adjust_link(dev);
 613 }
 614
 615 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 616
 617 /*
 618  * Find a device index from the devlist by name
 619  *
 620  * Returns:
 621  *  The index where the device is located, -1 on error
 622  */
 623 static int uec_miiphy_find_dev_by_name(const char *devname)
 624 {
 625         int i;
 626
 627         for (i = 0; i < MAXCONTROLLERS; i++) {
 628                 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
 629                         break;
 630                 }
 631         }
 632
 633         /* If device cannot be found, returns -1 */
 634         if (i == MAXCONTROLLERS) {
 635                 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
 636                 i = -1;
 637         }
 638
 639         return i;
 640 }
 641
 642 /*
 643  * Read a MII PHY register.
 644  *
 645  * Returns:
 646  *  0 on success
 647  */
 648 static int uec_miiphy_read(const char *devname, unsigned char addr,
 649                             unsigned char reg, unsigned short *value)
 650 {
 651         int devindex = 0;
 652
 653         if (devname == NULL || value == NULL) {
 654                 debug("%s: NULL pointer given\n", __FUNCTION__);
 655         } else {
 656                 devindex = uec_miiphy_find_dev_by_name(devname);
 657                 if (devindex >= 0) {
 658                         *value = uec_read_phy_reg(devlist[devindex], addr, reg);
 659                 }
 660         }
 661         return 0;
 662 }
 663
 664 /*
 665  * Write a MII PHY register.
 666  *
 667  * Returns:
 668  *  0 on success
 669  */
 670 static int uec_miiphy_write(const char *devname, unsigned char addr,
 671                              unsigned char reg, unsigned short value)
 672 {
 673         int devindex = 0;
 674
 675         if (devname == NULL) {
 676                 debug("%s: NULL pointer given\n", __FUNCTION__);
 677         } else {
 678                 devindex = uec_miiphy_find_dev_by_name(devname);
 679                 if (devindex >= 0) {
 680                         uec_write_phy_reg(devlist[devindex], addr, reg, value);
 681                 }
 682         }
 683         return 0;
 684 }
 685 #endif
 686
 687 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
 688 {
 689         uec_t           *uec_regs;
 690         u32             mac_addr1;
 691         u32             mac_addr2;
 692
 693         if (!uec) {
 694                 printf("%s: uec not initial\n", __FUNCTION__);
 695                 return -EINVAL;
 696         }
 697
 698         uec_regs = uec->uec_regs;
 699
 700         /* if a station address of 0x12345678ABCD, perform a write to
 701         MACSTNADDR1 of 0xCDAB7856,
 702         MACSTNADDR2 of 0x34120000 */
 703
 704         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
 705                         (mac_addr[3] << 8)  | (mac_addr[2]);
 706         out_be32(&uec_regs->macstnaddr1, mac_addr1);
 707
 708         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
 709         out_be32(&uec_regs->macstnaddr2, mac_addr2);
 710
 711         return 0;
 712 }
 713
 714 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
 715                                          int *threads_num_ret)
 716 {
 717         int     num_threads_numerica;
 718
 719         switch (threads_num) {
 720                 case UEC_NUM_OF_THREADS_1:
 721                         num_threads_numerica = 1;
 722                         break;
 723                 case UEC_NUM_OF_THREADS_2:
 724                         num_threads_numerica = 2;
 725                         break;
 726                 case UEC_NUM_OF_THREADS_4:
 727                         num_threads_numerica = 4;
 728                         break;
 729                 case UEC_NUM_OF_THREADS_6:
 730                         num_threads_numerica = 6;
 731                         break;
 732                 case UEC_NUM_OF_THREADS_8:
 733                         num_threads_numerica = 8;
 734                         break;
 735                 default:
 736                         printf("%s: Bad number of threads value.",
 737                                  __FUNCTION__);
 738                         return -EINVAL;
 739         }
 740
 741         *threads_num_ret = num_threads_numerica;
 742
 743         return 0;
 744 }
 745
 746 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
 747 {
 748         uec_info_t      *uec_info;
 749         u32             end_bd;
 750         u8              bmrx = 0;
 751         int             i;
 752
 753         uec_info = uec->uec_info;
 754
 755         /* Alloc global Tx parameter RAM page */
 756         uec->tx_glbl_pram_offset = qe_muram_alloc(
 757                                 sizeof(uec_tx_global_pram_t),
 758                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
 759         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
 760                                 qe_muram_addr(uec->tx_glbl_pram_offset);
 761
 762         /* Zero the global Tx prameter RAM */
 763         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
 764
 765         /* Init global Tx parameter RAM */
 766
 767         /* TEMODER, RMON statistics disable, one Tx queue */
 768         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
 769
 770         /* SQPTR */
 771         uec->send_q_mem_reg_offset = qe_muram_alloc(
 772                                 sizeof(uec_send_queue_qd_t),
 773                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
 774         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
 775                                 qe_muram_addr(uec->send_q_mem_reg_offset);
 776         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
 777
 778         /* Setup the table with TxBDs ring */
 779         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
 780                                          * SIZEOFBD;
 781         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
 782                                  (u32)(uec->p_tx_bd_ring));
 783         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
 784                                                  end_bd);
 785
 786         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
 787         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
 788
 789         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
 790         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
 791
 792         /* TSTATE, global snooping, big endian, the CSB bus selected */
 793         bmrx = BMR_INIT_VALUE;
 794         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
 795
 796         /* IPH_Offset */
 797         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
 798                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
 799         }
 800
 801         /* VTAG table */
 802         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
 803                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
 804         }
 805
 806         /* TQPTR */
 807         uec->thread_dat_tx_offset = qe_muram_alloc(
 808                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
 809                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
 810
 811         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
 812                                 qe_muram_addr(uec->thread_dat_tx_offset);
 813         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
 814 }
 815
 816 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
 817 {
 818         u8      bmrx = 0;
 819         int     i;
 820         uec_82xx_address_filtering_pram_t       *p_af_pram;
 821
 822         /* Allocate global Rx parameter RAM page */
 823         uec->rx_glbl_pram_offset = qe_muram_alloc(
 824                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
 825         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
 826                                 qe_muram_addr(uec->rx_glbl_pram_offset);
 827
 828         /* Zero Global Rx parameter RAM */
 829         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
 830
 831         /* Init global Rx parameter RAM */
 832         /* REMODER, Extended feature mode disable, VLAN disable,
 833          LossLess flow control disable, Receive firmware statisic disable,
 834          Extended address parsing mode disable, One Rx queues,
 835          Dynamic maximum/minimum frame length disable, IP checksum check
 836          disable, IP address alignment disable
 837         */
 838         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
 839
 840         /* RQPTR */
 841         uec->thread_dat_rx_offset = qe_muram_alloc(
 842                         num_threads_rx * sizeof(uec_thread_data_rx_t),
 843                          UEC_THREAD_DATA_ALIGNMENT);
 844         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
 845                                 qe_muram_addr(uec->thread_dat_rx_offset);
 846         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
 847
 848         /* Type_or_Len */
 849         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
 850
 851         /* RxRMON base pointer, we don't need it */
 852         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
 853
 854         /* IntCoalescingPTR, we don't need it, no interrupt */
 855         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
 856
 857         /* RSTATE, global snooping, big endian, the CSB bus selected */
 858         bmrx = BMR_INIT_VALUE;
 859         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
 860
 861         /* MRBLR */
 862         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
 863
 864         /* RBDQPTR */
 865         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
 866                                 sizeof(uec_rx_bd_queues_entry_t) + \
 867                                 sizeof(uec_rx_prefetched_bds_t),
 868                                  UEC_RX_BD_QUEUES_ALIGNMENT);
 869         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
 870                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
 871
 872         /* Zero it */
 873         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
 874                                         sizeof(uec_rx_prefetched_bds_t));
 875         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
 876         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
 877                  (u32)uec->p_rx_bd_ring);
 878
 879         /* MFLR */
 880         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
 881         /* MINFLR */
 882         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
 883         /* MAXD1 */
 884         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
 885         /* MAXD2 */
 886         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
 887         /* ECAM_PTR */
 888         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
 889         /* L2QT */
 890         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
 891         /* L3QT */
 892         for (i = 0; i < 8; i++) {
 893                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
 894         }
 895
 896         /* VLAN_TYPE */
 897         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
 898         /* TCI */
 899         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
 900
 901         /* Clear PQ2 style address filtering hash table */
 902         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
 903                         uec->p_rx_glbl_pram->addressfiltering;
 904
 905         p_af_pram->iaddr_h = 0;
 906         p_af_pram->iaddr_l = 0;
 907         p_af_pram->gaddr_h = 0;
 908         p_af_pram->gaddr_l = 0;
 909 }
 910
 911 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
 912                                          int thread_tx, int thread_rx)
 913 {
 914         uec_init_cmd_pram_t             *p_init_enet_param;
 915         u32                             init_enet_param_offset;
 916         uec_info_t                      *uec_info;
 917         int                             i;
 918         int                             snum;
 919         u32                             init_enet_offset;
 920         u32                             entry_val;
 921         u32                             command;
 922         u32                             cecr_subblock;
 923
 924         uec_info = uec->uec_info;
 925
 926         /* Allocate init enet command parameter */
 927         uec->init_enet_param_offset = qe_muram_alloc(
 928                                         sizeof(uec_init_cmd_pram_t), 4);
 929         init_enet_param_offset = uec->init_enet_param_offset;
 930         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
 931                                 qe_muram_addr(uec->init_enet_param_offset);
 932
 933         /* Zero init enet command struct */
 934         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
 935
 936         /* Init the command struct */
 937         p_init_enet_param = uec->p_init_enet_param;
 938         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
 939         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
 940         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
 941         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
 942         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
 943         p_init_enet_param->largestexternallookupkeysize = 0;
 944
 945         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
 946                                          << ENET_INIT_PARAM_RGF_SHIFT;
 947         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
 948                                          << ENET_INIT_PARAM_TGF_SHIFT;
 949
 950         /* Init Rx global parameter pointer */
 951         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
 952                                                  (u32)uec_info->risc_rx;
 953
 954         /* Init Rx threads */
 955         for (i = 0; i < (thread_rx + 1); i++) {
 956                 if ((snum = qe_get_snum()) < 0) {
 957                         printf("%s can not get snum\n", __FUNCTION__);
 958                         return -ENOMEM;
 959                 }
 960
 961                 if (i==0) {
 962                         init_enet_offset = 0;
 963                 } else {
 964                         init_enet_offset = qe_muram_alloc(
 965                                         sizeof(uec_thread_rx_pram_t),
 966                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
 967                 }
 968
 969                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 970                                  init_enet_offset | (u32)uec_info->risc_rx;
 971                 p_init_enet_param->rxthread[i] = entry_val;
 972         }
 973
 974         /* Init Tx global parameter pointer */
 975         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
 976                                          (u32)uec_info->risc_tx;
 977
 978         /* Init Tx threads */
 979         for (i = 0; i < thread_tx; i++) {
 980                 if ((snum = qe_get_snum()) < 0) {
 981                         printf("%s can not get snum\n", __FUNCTION__);
 982                         return -ENOMEM;
 983                 }
 984
 985                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
 986                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
 987
 988                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
 989                                  init_enet_offset | (u32)uec_info->risc_tx;
 990                 p_init_enet_param->txthread[i] = entry_val;
 991         }
 992
 993         __asm__ __volatile__("sync");
 994
 995         /* Issue QE command */
 996         command = QE_INIT_TX_RX;
 997         cecr_subblock = ucc_fast_get_qe_cr_subblock(
 998                                 uec->uec_info->uf_info.ucc_num);
 999         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
1000                                                  init_enet_param_offset);
1001
1002         return 0;
1003 }
1004
1005 static int uec_startup(uec_private_t *uec)
1006 {
1007         uec_info_t                      *uec_info;
1008         ucc_fast_info_t                 *uf_info;
1009         ucc_fast_private_t              *uccf;
1010         ucc_fast_t                      *uf_regs;
1011         uec_t                           *uec_regs;
1012         int                             num_threads_tx;
1013         int                             num_threads_rx;
1014         u32                             utbipar;
1015         u32                             length;
1016         u32                             align;
1017         qe_bd_t                         *bd;
1018         u8                              *buf;
1019         int                             i;
1020
1021         if (!uec || !uec->uec_info) {
1022                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1023                 return -EINVAL;
1024         }
1025
1026         uec_info = uec->uec_info;
1027         uf_info = &(uec_info->uf_info);
1028
1029         /* Check if Rx BD ring len is illegal */
1030         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1031                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1032                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1033                          __FUNCTION__);
1034                 return -EINVAL;
1035         }
1036
1037         /* Check if Tx BD ring len is illegal */
1038         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1039                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1040                          __FUNCTION__);
1041                 return -EINVAL;
1042         }
1043
1044         /* Check if MRBLR is illegal */
1045         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
1046                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1047                          __FUNCTION__);
1048                 return -EINVAL;
1049         }
1050
1051         /* Both Rx and Tx are stopped */
1052         uec->grace_stopped_rx = 1;
1053         uec->grace_stopped_tx = 1;
1054
1055         /* Init UCC fast */
1056         if (ucc_fast_init(uf_info, &uccf)) {
1057                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1058                 return -ENOMEM;
1059         }
1060
1061         /* Save uccf */
1062         uec->uccf = uccf;
1063
1064         /* Convert the Tx threads number */
1065         if (uec_convert_threads_num(uec_info->num_threads_tx,
1066                                          &num_threads_tx)) {
1067                 return -EINVAL;
1068         }
1069
1070         /* Convert the Rx threads number */
1071         if (uec_convert_threads_num(uec_info->num_threads_rx,
1072                                          &num_threads_rx)) {
1073                 return -EINVAL;
1074         }
1075
1076         uf_regs = uccf->uf_regs;
1077
1078         /* UEC register is following UCC fast registers */
1079         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1080
1081         /* Save the UEC register pointer to UEC private struct */
1082         uec->uec_regs = uec_regs;
1083
1084         /* Init UPSMR, enable hardware statistics (UCC) */
1085         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1086
1087         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1088         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1089
1090         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1091         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1092
1093         /* Setup MAC interface mode */
1094         uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
1095
1096         /* Setup MII management base */
1097 #ifndef CONFIG_eTSEC_MDIO_BUS
1098         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1099 #else
1100         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1101 #endif
1102
1103         /* Setup MII master clock source */
1104         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1105
1106         /* Setup UTBIPAR */
1107         utbipar = in_be32(&uec_regs->utbipar);
1108         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1109
1110         /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1111          * This frees up the remaining SMI addresses for use.
1112          */
1113         utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
1114         out_be32(&uec_regs->utbipar, utbipar);
1115
1116         /* Configure the TBI for SGMII operation */
1117         if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) &&
1118            (uec->uec_info->speed == SPEED_1000)) {
1119                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1120                         ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1121
1122                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1123                         ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1124
1125                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1126                         ENET_TBI_MII_CR, TBICR_SETTINGS);
1127         }
1128
1129         /* Allocate Tx BDs */
1130         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1131                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1132                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1133         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1134                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1135                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1136         }
1137
1138         align = UEC_TX_BD_RING_ALIGNMENT;
1139         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1140         if (uec->tx_bd_ring_offset != 0) {
1141                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1142                                                  & ~(align - 1));
1143         }
1144
1145         /* Zero all of Tx BDs */
1146         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1147
1148         /* Allocate Rx BDs */
1149         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1150         align = UEC_RX_BD_RING_ALIGNMENT;
1151         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1152         if (uec->rx_bd_ring_offset != 0) {
1153                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1154                                                          & ~(align - 1));
1155         }
1156
1157         /* Zero all of Rx BDs */
1158         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1159
1160         /* Allocate Rx buffer */
1161         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1162         align = UEC_RX_DATA_BUF_ALIGNMENT;
1163         uec->rx_buf_offset = (u32)malloc(length + align);
1164         if (uec->rx_buf_offset != 0) {
1165                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1166                                                  & ~(align - 1));
1167         }
1168
1169         /* Zero all of the Rx buffer */
1170         memset((void *)(uec->rx_buf_offset), 0, length + align);
1171
1172         /* Init TxBD ring */
1173         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1174         uec->txBd = bd;
1175
1176         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1177                 BD_DATA_CLEAR(bd);
1178                 BD_STATUS_SET(bd, 0);
1179                 BD_LENGTH_SET(bd, 0);
1180                 bd ++;
1181         }
1182         BD_STATUS_SET((--bd), TxBD_WRAP);
1183
1184         /* Init RxBD ring */
1185         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1186         uec->rxBd = bd;
1187         buf = uec->p_rx_buf;
1188         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1189                 BD_DATA_SET(bd, buf);
1190                 BD_LENGTH_SET(bd, 0);
1191                 BD_STATUS_SET(bd, RxBD_EMPTY);
1192                 buf += MAX_RXBUF_LEN;
1193                 bd ++;
1194         }
1195         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1196
1197         /* Init global Tx parameter RAM */
1198         uec_init_tx_parameter(uec, num_threads_tx);
1199
1200         /* Init global Rx parameter RAM */
1201         uec_init_rx_parameter(uec, num_threads_rx);
1202
1203         /* Init ethernet Tx and Rx parameter command */
1204         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1205                                          num_threads_rx)) {
1206                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1207                 return -ENOMEM;
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int uec_init(struct eth_device* dev, bd_t *bd)
1214 {
1215         uec_private_t           *uec;
1216         int                     err, i;
1217         struct phy_info         *curphy;
1218 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1219     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1220         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1221 #endif
1222
1223         uec = (uec_private_t *)dev->priv;
1224
1225         if (uec->the_first_run == 0) {
1226 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1227     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1228         /* QE9 and QE12 need to be set for enabling QE MII managment signals */
1229         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
1230         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1231 #endif
1232
1233                 err = init_phy(dev);
1234                 if (err) {
1235                         printf("%s: Cannot initialize PHY, aborting.\n",
1236                                dev->name);
1237                         return err;
1238                 }
1239
1240                 curphy = uec->mii_info->phyinfo;
1241
1242                 if (curphy->config_aneg) {
1243                         err = curphy->config_aneg(uec->mii_info);
1244                         if (err) {
1245                                 printf("%s: Can't negotiate PHY\n", dev->name);
1246                                 return err;
1247                         }
1248                 }
1249
1250                 /* Give PHYs up to 5 sec to report a link */
1251                 i = 50;
1252                 do {
1253                         err = curphy->read_status(uec->mii_info);
1254                         if (!(((i-- > 0) && !uec->mii_info->link) || err))
1255                                 break;
1256                         udelay(100000);
1257                 } while (1);
1258
1259 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1260     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1261                 /* QE12 needs to be released for enabling LBCTL signal*/
1262                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1263 #endif
1264
1265                 if (err || i <= 0)
1266                         printf("warning: %s: timeout on PHY link\n", dev->name);
1267
1268                 adjust_link(dev);
1269                 uec->the_first_run = 1;
1270         }
1271
1272         /* Set up the MAC address */
1273         if (dev->enetaddr[0] & 0x01) {
1274                 printf("%s: MacAddress is multcast address\n",
1275                          __FUNCTION__);
1276                 return -1;
1277         }
1278         uec_set_mac_address(uec, dev->enetaddr);
1279
1280
1281         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1282         if (err) {
1283                 printf("%s: cannot enable UEC device\n", dev->name);
1284                 return -1;
1285         }
1286
1287         phy_change(dev);
1288
1289         return (uec->mii_info->link ? 0 : -1);
1290 }
1291
1292 static void uec_halt(struct eth_device* dev)
1293 {
1294         uec_private_t   *uec = (uec_private_t *)dev->priv;
1295         uec_stop(uec, COMM_DIR_RX_AND_TX);
1296 }
1297
1298 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1299 {
1300         uec_private_t           *uec;
1301         ucc_fast_private_t      *uccf;
1302         volatile qe_bd_t        *bd;
1303         u16                     status;
1304         int                     i;
1305         int                     result = 0;
1306
1307         uec = (uec_private_t *)dev->priv;
1308         uccf = uec->uccf;
1309         bd = uec->txBd;
1310
1311         /* Find an empty TxBD */
1312         for (i = 0; bd->status & TxBD_READY; i++) {
1313                 if (i > 0x100000) {
1314                         printf("%s: tx buffer not ready\n", dev->name);
1315                         return result;
1316                 }
1317         }
1318
1319         /* Init TxBD */
1320         BD_DATA_SET(bd, buf);
1321         BD_LENGTH_SET(bd, len);
1322         status = bd->status;
1323         status &= BD_WRAP;
1324         status |= (TxBD_READY | TxBD_LAST);
1325         BD_STATUS_SET(bd, status);
1326
1327         /* Tell UCC to transmit the buffer */
1328         ucc_fast_transmit_on_demand(uccf);
1329
1330         /* Wait for buffer to be transmitted */
1331         for (i = 0; bd->status & TxBD_READY; i++) {
1332                 if (i > 0x100000) {
1333                         printf("%s: tx error\n", dev->name);
1334                         return result;
1335                 }
1336         }
1337
1338         /* Ok, the buffer be transimitted */
1339         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1340         uec->txBd = bd;
1341         result = 1;
1342
1343         return result;
1344 }
1345
1346 static int uec_recv(struct eth_device* dev)
1347 {
1348         uec_private_t           *uec = dev->priv;
1349         volatile qe_bd_t        *bd;
1350         u16                     status;
1351         u16                     len;
1352         u8                      *data;
1353
1354         bd = uec->rxBd;
1355         status = bd->status;
1356
1357         while (!(status & RxBD_EMPTY)) {
1358                 if (!(status & RxBD_ERROR)) {
1359                         data = BD_DATA(bd);
1360                         len = BD_LENGTH(bd);
1361                         NetReceive(data, len);
1362                 } else {
1363                         printf("%s: Rx error\n", dev->name);
1364                 }
1365                 status &= BD_CLEAN;
1366                 BD_LENGTH_SET(bd, 0);
1367                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1368                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1369                 status = bd->status;
1370         }
1371         uec->rxBd = bd;
1372
1373         return 1;
1374 }
1375
1376 int uec_initialize(bd_t *bis, uec_info_t *uec_info)
1377 {
1378         struct eth_device       *dev;
1379         int                     i;
1380         uec_private_t           *uec;
1381         int                     err;
1382
1383         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1384         if (!dev)
1385                 return 0;
1386         memset(dev, 0, sizeof(struct eth_device));
1387
1388         /* Allocate the UEC private struct */
1389         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1390         if (!uec) {
1391                 return -ENOMEM;
1392         }
1393         memset(uec, 0, sizeof(uec_private_t));
1394
1395         /* Adjust uec_info */
1396 #if (MAX_QE_RISC == 4)
1397         uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1398         uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1399 #endif
1400
1401         devlist[uec_info->uf_info.ucc_num] = dev;
1402
1403         uec->uec_info = uec_info;
1404         uec->dev = dev;
1405
1406         sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
1407         dev->iobase = 0;
1408         dev->priv = (void *)uec;
1409         dev->init = uec_init;
1410         dev->halt = uec_halt;
1411         dev->send = uec_send;
1412         dev->recv = uec_recv;
1413
1414         /* Clear the ethnet address */
1415         for (i = 0; i < 6; i++)
1416                 dev->enetaddr[i] = 0;
1417
1418         eth_register(dev);
1419
1420         err = uec_startup(uec);
1421         if (err) {
1422                 printf("%s: Cannot configure net device, aborting.",dev->name);
1423                 return err;
1424         }
1425
1426 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1427         miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1428 #endif
1429
1430         return 1;
1431 }
1432
1433 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
1434 {
1435         int i;
1436
1437         for (i = 0; i < num; i++)
1438                 uec_initialize(bis, &uecs[i]);
1439
1440         return 0;
1441 }
1442
1443 int uec_standard_init(bd_t *bis)
1444 {
1445         return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
1446 }