]> git.sur5r.net Git - u-boot/blob - drivers/qe/uec.c
Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash
[u-boot] / drivers / qe / uec.c
1 /*
2  * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21
22 #include "common.h"
23 #include "net.h"
24 #include "malloc.h"
25 #include "asm/errno.h"
26 #include "asm/io.h"
27 #include "asm/immap_qe.h"
28 #include "qe.h"
29 #include "uccf.h"
30 #include "uec.h"
31 #include "uec_phy.h"
32 #include "miiphy.h"
33 #include <phy.h>
34
35 /* Default UTBIPAR SMI address */
36 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
37 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
38 #endif
39
40 static uec_info_t uec_info[] = {
41 #ifdef CONFIG_UEC_ETH1
42         STD_UEC_INFO(1),        /* UEC1 */
43 #endif
44 #ifdef CONFIG_UEC_ETH2
45         STD_UEC_INFO(2),        /* UEC2 */
46 #endif
47 #ifdef CONFIG_UEC_ETH3
48         STD_UEC_INFO(3),        /* UEC3 */
49 #endif
50 #ifdef CONFIG_UEC_ETH4
51         STD_UEC_INFO(4),        /* UEC4 */
52 #endif
53 #ifdef CONFIG_UEC_ETH5
54         STD_UEC_INFO(5),        /* UEC5 */
55 #endif
56 #ifdef CONFIG_UEC_ETH6
57         STD_UEC_INFO(6),        /* UEC6 */
58 #endif
59 #ifdef CONFIG_UEC_ETH7
60         STD_UEC_INFO(7),        /* UEC7 */
61 #endif
62 #ifdef CONFIG_UEC_ETH8
63         STD_UEC_INFO(8),        /* UEC8 */
64 #endif
65 };
66
67 #define MAXCONTROLLERS  (8)
68
69 static struct eth_device *devlist[MAXCONTROLLERS];
70
71 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
72 {
73         uec_t           *uec_regs;
74         u32             maccfg1;
75
76         if (!uec) {
77                 printf("%s: uec not initial\n", __FUNCTION__);
78                 return -EINVAL;
79         }
80         uec_regs = uec->uec_regs;
81
82         maccfg1 = in_be32(&uec_regs->maccfg1);
83
84         if (mode & COMM_DIR_TX) {
85                 maccfg1 |= MACCFG1_ENABLE_TX;
86                 out_be32(&uec_regs->maccfg1, maccfg1);
87                 uec->mac_tx_enabled = 1;
88         }
89
90         if (mode & COMM_DIR_RX) {
91                 maccfg1 |= MACCFG1_ENABLE_RX;
92                 out_be32(&uec_regs->maccfg1, maccfg1);
93                 uec->mac_rx_enabled = 1;
94         }
95
96         return 0;
97 }
98
99 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
100 {
101         uec_t           *uec_regs;
102         u32             maccfg1;
103
104         if (!uec) {
105                 printf("%s: uec not initial\n", __FUNCTION__);
106                 return -EINVAL;
107         }
108         uec_regs = uec->uec_regs;
109
110         maccfg1 = in_be32(&uec_regs->maccfg1);
111
112         if (mode & COMM_DIR_TX) {
113                 maccfg1 &= ~MACCFG1_ENABLE_TX;
114                 out_be32(&uec_regs->maccfg1, maccfg1);
115                 uec->mac_tx_enabled = 0;
116         }
117
118         if (mode & COMM_DIR_RX) {
119                 maccfg1 &= ~MACCFG1_ENABLE_RX;
120                 out_be32(&uec_regs->maccfg1, maccfg1);
121                 uec->mac_rx_enabled = 0;
122         }
123
124         return 0;
125 }
126
127 static int uec_graceful_stop_tx(uec_private_t *uec)
128 {
129         ucc_fast_t              *uf_regs;
130         u32                     cecr_subblock;
131         u32                     ucce;
132
133         if (!uec || !uec->uccf) {
134                 printf("%s: No handle passed.\n", __FUNCTION__);
135                 return -EINVAL;
136         }
137
138         uf_regs = uec->uccf->uf_regs;
139
140         /* Clear the grace stop event */
141         out_be32(&uf_regs->ucce, UCCE_GRA);
142
143         /* Issue host command */
144         cecr_subblock =
145                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
146         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
147                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
148
149         /* Wait for command to complete */
150         do {
151                 ucce = in_be32(&uf_regs->ucce);
152         } while (! (ucce & UCCE_GRA));
153
154         uec->grace_stopped_tx = 1;
155
156         return 0;
157 }
158
159 static int uec_graceful_stop_rx(uec_private_t *uec)
160 {
161         u32             cecr_subblock;
162         u8              ack;
163
164         if (!uec) {
165                 printf("%s: No handle passed.\n", __FUNCTION__);
166                 return -EINVAL;
167         }
168
169         if (!uec->p_rx_glbl_pram) {
170                 printf("%s: No init rx global parameter\n", __FUNCTION__);
171                 return -EINVAL;
172         }
173
174         /* Clear acknowledge bit */
175         ack = uec->p_rx_glbl_pram->rxgstpack;
176         ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
177         uec->p_rx_glbl_pram->rxgstpack = ack;
178
179         /* Keep issuing cmd and checking ack bit until it is asserted */
180         do {
181                 /* Issue host command */
182                 cecr_subblock =
183                  ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
184                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
185                                  (u8)QE_CR_PROTOCOL_ETHERNET, 0);
186                 ack = uec->p_rx_glbl_pram->rxgstpack;
187         } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
188
189         uec->grace_stopped_rx = 1;
190
191         return 0;
192 }
193
194 static int uec_restart_tx(uec_private_t *uec)
195 {
196         u32             cecr_subblock;
197
198         if (!uec || !uec->uec_info) {
199                 printf("%s: No handle passed.\n", __FUNCTION__);
200                 return -EINVAL;
201         }
202
203         cecr_subblock =
204          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
205         qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
206                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
207
208         uec->grace_stopped_tx = 0;
209
210         return 0;
211 }
212
213 static int uec_restart_rx(uec_private_t *uec)
214 {
215         u32             cecr_subblock;
216
217         if (!uec || !uec->uec_info) {
218                 printf("%s: No handle passed.\n", __FUNCTION__);
219                 return -EINVAL;
220         }
221
222         cecr_subblock =
223          ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
224         qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
225                          (u8)QE_CR_PROTOCOL_ETHERNET, 0);
226
227         uec->grace_stopped_rx = 0;
228
229         return 0;
230 }
231
232 static int uec_open(uec_private_t *uec, comm_dir_e mode)
233 {
234         ucc_fast_private_t      *uccf;
235
236         if (!uec || !uec->uccf) {
237                 printf("%s: No handle passed.\n", __FUNCTION__);
238                 return -EINVAL;
239         }
240         uccf = uec->uccf;
241
242         /* check if the UCC number is in range. */
243         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
244                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
245                 return -EINVAL;
246         }
247
248         /* Enable MAC */
249         uec_mac_enable(uec, mode);
250
251         /* Enable UCC fast */
252         ucc_fast_enable(uccf, mode);
253
254         /* RISC microcode start */
255         if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
256                 uec_restart_tx(uec);
257         }
258         if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
259                 uec_restart_rx(uec);
260         }
261
262         return 0;
263 }
264
265 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
266 {
267         if (!uec || !uec->uccf) {
268                 printf("%s: No handle passed.\n", __FUNCTION__);
269                 return -EINVAL;
270         }
271
272         /* check if the UCC number is in range. */
273         if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
274                 printf("%s: ucc_num out of range.\n", __FUNCTION__);
275                 return -EINVAL;
276         }
277         /* Stop any transmissions */
278         if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
279                 uec_graceful_stop_tx(uec);
280         }
281         /* Stop any receptions */
282         if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
283                 uec_graceful_stop_rx(uec);
284         }
285
286         /* Disable the UCC fast */
287         ucc_fast_disable(uec->uccf, mode);
288
289         /* Disable the MAC */
290         uec_mac_disable(uec, mode);
291
292         return 0;
293 }
294
295 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
296 {
297         uec_t           *uec_regs;
298         u32             maccfg2;
299
300         if (!uec) {
301                 printf("%s: uec not initial\n", __FUNCTION__);
302                 return -EINVAL;
303         }
304         uec_regs = uec->uec_regs;
305
306         if (duplex == DUPLEX_HALF) {
307                 maccfg2 = in_be32(&uec_regs->maccfg2);
308                 maccfg2 &= ~MACCFG2_FDX;
309                 out_be32(&uec_regs->maccfg2, maccfg2);
310         }
311
312         if (duplex == DUPLEX_FULL) {
313                 maccfg2 = in_be32(&uec_regs->maccfg2);
314                 maccfg2 |= MACCFG2_FDX;
315                 out_be32(&uec_regs->maccfg2, maccfg2);
316         }
317
318         return 0;
319 }
320
321 static int uec_set_mac_if_mode(uec_private_t *uec,
322                 phy_interface_t if_mode, int speed)
323 {
324         phy_interface_t         enet_if_mode;
325         uec_t                   *uec_regs;
326         u32                     upsmr;
327         u32                     maccfg2;
328
329         if (!uec) {
330                 printf("%s: uec not initial\n", __FUNCTION__);
331                 return -EINVAL;
332         }
333
334         uec_regs = uec->uec_regs;
335         enet_if_mode = if_mode;
336
337         maccfg2 = in_be32(&uec_regs->maccfg2);
338         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
339
340         upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
341         upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
342
343         switch (speed) {
344                 case SPEED_10:
345                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
346                         switch (enet_if_mode) {
347                                 case PHY_INTERFACE_MODE_MII:
348                                         break;
349                                 case PHY_INTERFACE_MODE_RGMII:
350                                         upsmr |= (UPSMR_RPM | UPSMR_R10M);
351                                         break;
352                                 case PHY_INTERFACE_MODE_RMII:
353                                         upsmr |= (UPSMR_R10M | UPSMR_RMM);
354                                         break;
355                                 default:
356                                         return -EINVAL;
357                                         break;
358                         }
359                         break;
360                 case SPEED_100:
361                         maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
362                         switch (enet_if_mode) {
363                                 case PHY_INTERFACE_MODE_MII:
364                                         break;
365                                 case PHY_INTERFACE_MODE_RGMII:
366                                         upsmr |= UPSMR_RPM;
367                                         break;
368                                 case PHY_INTERFACE_MODE_RMII:
369                                         upsmr |= UPSMR_RMM;
370                                         break;
371                                 default:
372                                         return -EINVAL;
373                                         break;
374                         }
375                         break;
376                 case SPEED_1000:
377                         maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
378                         switch (enet_if_mode) {
379                                 case PHY_INTERFACE_MODE_GMII:
380                                         break;
381                                 case PHY_INTERFACE_MODE_TBI:
382                                         upsmr |= UPSMR_TBIM;
383                                         break;
384                                 case PHY_INTERFACE_MODE_RTBI:
385                                         upsmr |= (UPSMR_RPM | UPSMR_TBIM);
386                                         break;
387                                 case PHY_INTERFACE_MODE_RGMII_RXID:
388                                 case PHY_INTERFACE_MODE_RGMII_TXID:
389                                 case PHY_INTERFACE_MODE_RGMII_ID:
390                                 case PHY_INTERFACE_MODE_RGMII:
391                                         upsmr |= UPSMR_RPM;
392                                         break;
393                                 case PHY_INTERFACE_MODE_SGMII:
394                                         upsmr |= UPSMR_SGMM;
395                                         break;
396                                 default:
397                                         return -EINVAL;
398                                         break;
399                         }
400                         break;
401                 default:
402                         return -EINVAL;
403                         break;
404         }
405
406         out_be32(&uec_regs->maccfg2, maccfg2);
407         out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
408
409         return 0;
410 }
411
412 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
413 {
414         uint            timeout = 0x1000;
415         u32             miimcfg = 0;
416
417         miimcfg = in_be32(&uec_mii_regs->miimcfg);
418         miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
419         out_be32(&uec_mii_regs->miimcfg, miimcfg);
420
421         /* Wait until the bus is free */
422         while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
423         if (timeout <= 0) {
424                 printf("%s: The MII Bus is stuck!", __FUNCTION__);
425                 return -ETIMEDOUT;
426         }
427
428         return 0;
429 }
430
431 static int init_phy(struct eth_device *dev)
432 {
433         uec_private_t           *uec;
434         uec_mii_t               *umii_regs;
435         struct uec_mii_info     *mii_info;
436         struct phy_info         *curphy;
437         int                     err;
438
439         uec = (uec_private_t *)dev->priv;
440         umii_regs = uec->uec_mii_regs;
441
442         uec->oldlink = 0;
443         uec->oldspeed = 0;
444         uec->oldduplex = -1;
445
446         mii_info = malloc(sizeof(*mii_info));
447         if (!mii_info) {
448                 printf("%s: Could not allocate mii_info", dev->name);
449                 return -ENOMEM;
450         }
451         memset(mii_info, 0, sizeof(*mii_info));
452
453         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
454                 mii_info->speed = SPEED_1000;
455         } else {
456                 mii_info->speed = SPEED_100;
457         }
458
459         mii_info->duplex = DUPLEX_FULL;
460         mii_info->pause = 0;
461         mii_info->link = 1;
462
463         mii_info->advertising = (ADVERTISED_10baseT_Half |
464                                 ADVERTISED_10baseT_Full |
465                                 ADVERTISED_100baseT_Half |
466                                 ADVERTISED_100baseT_Full |
467                                 ADVERTISED_1000baseT_Full);
468         mii_info->autoneg = 1;
469         mii_info->mii_id = uec->uec_info->phy_address;
470         mii_info->dev = dev;
471
472         mii_info->mdio_read = &uec_read_phy_reg;
473         mii_info->mdio_write = &uec_write_phy_reg;
474
475         uec->mii_info = mii_info;
476
477         qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
478
479         if (init_mii_management_configuration(umii_regs)) {
480                 printf("%s: The MII Bus is stuck!", dev->name);
481                 err = -1;
482                 goto bus_fail;
483         }
484
485         /* get info for this PHY */
486         curphy = uec_get_phy_info(uec->mii_info);
487         if (!curphy) {
488                 printf("%s: No PHY found", dev->name);
489                 err = -1;
490                 goto no_phy;
491         }
492
493         mii_info->phyinfo = curphy;
494
495         /* Run the commands which initialize the PHY */
496         if (curphy->init) {
497                 err = curphy->init(uec->mii_info);
498                 if (err)
499                         goto phy_init_fail;
500         }
501
502         return 0;
503
504 phy_init_fail:
505 no_phy:
506 bus_fail:
507         free(mii_info);
508         return err;
509 }
510
511 static void adjust_link(struct eth_device *dev)
512 {
513         uec_private_t           *uec = (uec_private_t *)dev->priv;
514         struct uec_mii_info     *mii_info = uec->mii_info;
515
516         extern void change_phy_interface_mode(struct eth_device *dev,
517                                  phy_interface_t mode, int speed);
518
519         if (mii_info->link) {
520                 /* Now we make sure that we can be in full duplex mode.
521                 * If not, we operate in half-duplex mode. */
522                 if (mii_info->duplex != uec->oldduplex) {
523                         if (!(mii_info->duplex)) {
524                                 uec_set_mac_duplex(uec, DUPLEX_HALF);
525                                 printf("%s: Half Duplex\n", dev->name);
526                         } else {
527                                 uec_set_mac_duplex(uec, DUPLEX_FULL);
528                                 printf("%s: Full Duplex\n", dev->name);
529                         }
530                         uec->oldduplex = mii_info->duplex;
531                 }
532
533                 if (mii_info->speed != uec->oldspeed) {
534                         phy_interface_t mode =
535                                 uec->uec_info->enet_interface_type;
536                         if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
537                                 switch (mii_info->speed) {
538                                 case SPEED_1000:
539                                         break;
540                                 case SPEED_100:
541                                         printf ("switching to rgmii 100\n");
542                                         mode = PHY_INTERFACE_MODE_RGMII;
543                                         break;
544                                 case SPEED_10:
545                                         printf ("switching to rgmii 10\n");
546                                         mode = PHY_INTERFACE_MODE_RGMII;
547                                         break;
548                                 default:
549                                         printf("%s: Ack,Speed(%d)is illegal\n",
550                                                 dev->name, mii_info->speed);
551                                         break;
552                                 }
553                         }
554
555                         /* change phy */
556                         change_phy_interface_mode(dev, mode, mii_info->speed);
557                         /* change the MAC interface mode */
558                         uec_set_mac_if_mode(uec, mode, mii_info->speed);
559
560                         printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
561                         uec->oldspeed = mii_info->speed;
562                 }
563
564                 if (!uec->oldlink) {
565                         printf("%s: Link is up\n", dev->name);
566                         uec->oldlink = 1;
567                 }
568
569         } else { /* if (mii_info->link) */
570                 if (uec->oldlink) {
571                         printf("%s: Link is down\n", dev->name);
572                         uec->oldlink = 0;
573                         uec->oldspeed = 0;
574                         uec->oldduplex = -1;
575                 }
576         }
577 }
578
579 static void phy_change(struct eth_device *dev)
580 {
581         uec_private_t   *uec = (uec_private_t *)dev->priv;
582
583 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
584     defined(CONFIG_P1021) || defined(CONFIG_P1025)
585         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
586
587         /* QE9 and QE12 need to be set for enabling QE MII managment signals */
588         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
589         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
590 #endif
591
592         /* Update the link, speed, duplex */
593         uec->mii_info->phyinfo->read_status(uec->mii_info);
594
595 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
596     defined(CONFIG_P1021) || defined(CONFIG_P1025)
597         /*
598          * QE12 is muxed with LBCTL, it needs to be released for enabling
599          * LBCTL signal for LBC usage.
600          */
601         clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
602 #endif
603
604         /* Adjust the interface according to speed */
605         adjust_link(dev);
606 }
607
608 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
609
610 /*
611  * Find a device index from the devlist by name
612  *
613  * Returns:
614  *  The index where the device is located, -1 on error
615  */
616 static int uec_miiphy_find_dev_by_name(const char *devname)
617 {
618         int i;
619
620         for (i = 0; i < MAXCONTROLLERS; i++) {
621                 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
622                         break;
623                 }
624         }
625
626         /* If device cannot be found, returns -1 */
627         if (i == MAXCONTROLLERS) {
628                 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
629                 i = -1;
630         }
631
632         return i;
633 }
634
635 /*
636  * Read a MII PHY register.
637  *
638  * Returns:
639  *  0 on success
640  */
641 static int uec_miiphy_read(const char *devname, unsigned char addr,
642                             unsigned char reg, unsigned short *value)
643 {
644         int devindex = 0;
645
646         if (devname == NULL || value == NULL) {
647                 debug("%s: NULL pointer given\n", __FUNCTION__);
648         } else {
649                 devindex = uec_miiphy_find_dev_by_name(devname);
650                 if (devindex >= 0) {
651                         *value = uec_read_phy_reg(devlist[devindex], addr, reg);
652                 }
653         }
654         return 0;
655 }
656
657 /*
658  * Write a MII PHY register.
659  *
660  * Returns:
661  *  0 on success
662  */
663 static int uec_miiphy_write(const char *devname, unsigned char addr,
664                              unsigned char reg, unsigned short value)
665 {
666         int devindex = 0;
667
668         if (devname == NULL) {
669                 debug("%s: NULL pointer given\n", __FUNCTION__);
670         } else {
671                 devindex = uec_miiphy_find_dev_by_name(devname);
672                 if (devindex >= 0) {
673                         uec_write_phy_reg(devlist[devindex], addr, reg, value);
674                 }
675         }
676         return 0;
677 }
678 #endif
679
680 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
681 {
682         uec_t           *uec_regs;
683         u32             mac_addr1;
684         u32             mac_addr2;
685
686         if (!uec) {
687                 printf("%s: uec not initial\n", __FUNCTION__);
688                 return -EINVAL;
689         }
690
691         uec_regs = uec->uec_regs;
692
693         /* if a station address of 0x12345678ABCD, perform a write to
694         MACSTNADDR1 of 0xCDAB7856,
695         MACSTNADDR2 of 0x34120000 */
696
697         mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
698                         (mac_addr[3] << 8)  | (mac_addr[2]);
699         out_be32(&uec_regs->macstnaddr1, mac_addr1);
700
701         mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
702         out_be32(&uec_regs->macstnaddr2, mac_addr2);
703
704         return 0;
705 }
706
707 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
708                                          int *threads_num_ret)
709 {
710         int     num_threads_numerica;
711
712         switch (threads_num) {
713                 case UEC_NUM_OF_THREADS_1:
714                         num_threads_numerica = 1;
715                         break;
716                 case UEC_NUM_OF_THREADS_2:
717                         num_threads_numerica = 2;
718                         break;
719                 case UEC_NUM_OF_THREADS_4:
720                         num_threads_numerica = 4;
721                         break;
722                 case UEC_NUM_OF_THREADS_6:
723                         num_threads_numerica = 6;
724                         break;
725                 case UEC_NUM_OF_THREADS_8:
726                         num_threads_numerica = 8;
727                         break;
728                 default:
729                         printf("%s: Bad number of threads value.",
730                                  __FUNCTION__);
731                         return -EINVAL;
732         }
733
734         *threads_num_ret = num_threads_numerica;
735
736         return 0;
737 }
738
739 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
740 {
741         uec_info_t      *uec_info;
742         u32             end_bd;
743         u8              bmrx = 0;
744         int             i;
745
746         uec_info = uec->uec_info;
747
748         /* Alloc global Tx parameter RAM page */
749         uec->tx_glbl_pram_offset = qe_muram_alloc(
750                                 sizeof(uec_tx_global_pram_t),
751                                  UEC_TX_GLOBAL_PRAM_ALIGNMENT);
752         uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
753                                 qe_muram_addr(uec->tx_glbl_pram_offset);
754
755         /* Zero the global Tx prameter RAM */
756         memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
757
758         /* Init global Tx parameter RAM */
759
760         /* TEMODER, RMON statistics disable, one Tx queue */
761         out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
762
763         /* SQPTR */
764         uec->send_q_mem_reg_offset = qe_muram_alloc(
765                                 sizeof(uec_send_queue_qd_t),
766                                  UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
767         uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
768                                 qe_muram_addr(uec->send_q_mem_reg_offset);
769         out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
770
771         /* Setup the table with TxBDs ring */
772         end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
773                                          * SIZEOFBD;
774         out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
775                                  (u32)(uec->p_tx_bd_ring));
776         out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
777                                                  end_bd);
778
779         /* Scheduler Base Pointer, we have only one Tx queue, no need it */
780         out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
781
782         /* TxRMON Base Pointer, TxRMON disable, we don't need it */
783         out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
784
785         /* TSTATE, global snooping, big endian, the CSB bus selected */
786         bmrx = BMR_INIT_VALUE;
787         out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
788
789         /* IPH_Offset */
790         for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
791                 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
792         }
793
794         /* VTAG table */
795         for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
796                 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
797         }
798
799         /* TQPTR */
800         uec->thread_dat_tx_offset = qe_muram_alloc(
801                 num_threads_tx * sizeof(uec_thread_data_tx_t) +
802                  32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
803
804         uec->p_thread_data_tx = (uec_thread_data_tx_t *)
805                                 qe_muram_addr(uec->thread_dat_tx_offset);
806         out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
807 }
808
809 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
810 {
811         u8      bmrx = 0;
812         int     i;
813         uec_82xx_address_filtering_pram_t       *p_af_pram;
814
815         /* Allocate global Rx parameter RAM page */
816         uec->rx_glbl_pram_offset = qe_muram_alloc(
817                 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
818         uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
819                                 qe_muram_addr(uec->rx_glbl_pram_offset);
820
821         /* Zero Global Rx parameter RAM */
822         memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
823
824         /* Init global Rx parameter RAM */
825         /* REMODER, Extended feature mode disable, VLAN disable,
826          LossLess flow control disable, Receive firmware statisic disable,
827          Extended address parsing mode disable, One Rx queues,
828          Dynamic maximum/minimum frame length disable, IP checksum check
829          disable, IP address alignment disable
830         */
831         out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
832
833         /* RQPTR */
834         uec->thread_dat_rx_offset = qe_muram_alloc(
835                         num_threads_rx * sizeof(uec_thread_data_rx_t),
836                          UEC_THREAD_DATA_ALIGNMENT);
837         uec->p_thread_data_rx = (uec_thread_data_rx_t *)
838                                 qe_muram_addr(uec->thread_dat_rx_offset);
839         out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
840
841         /* Type_or_Len */
842         out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
843
844         /* RxRMON base pointer, we don't need it */
845         out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
846
847         /* IntCoalescingPTR, we don't need it, no interrupt */
848         out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
849
850         /* RSTATE, global snooping, big endian, the CSB bus selected */
851         bmrx = BMR_INIT_VALUE;
852         out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
853
854         /* MRBLR */
855         out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
856
857         /* RBDQPTR */
858         uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
859                                 sizeof(uec_rx_bd_queues_entry_t) + \
860                                 sizeof(uec_rx_prefetched_bds_t),
861                                  UEC_RX_BD_QUEUES_ALIGNMENT);
862         uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
863                                 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
864
865         /* Zero it */
866         memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
867                                         sizeof(uec_rx_prefetched_bds_t));
868         out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
869         out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
870                  (u32)uec->p_rx_bd_ring);
871
872         /* MFLR */
873         out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
874         /* MINFLR */
875         out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
876         /* MAXD1 */
877         out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
878         /* MAXD2 */
879         out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
880         /* ECAM_PTR */
881         out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
882         /* L2QT */
883         out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
884         /* L3QT */
885         for (i = 0; i < 8; i++) {
886                 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
887         }
888
889         /* VLAN_TYPE */
890         out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
891         /* TCI */
892         out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
893
894         /* Clear PQ2 style address filtering hash table */
895         p_af_pram = (uec_82xx_address_filtering_pram_t *) \
896                         uec->p_rx_glbl_pram->addressfiltering;
897
898         p_af_pram->iaddr_h = 0;
899         p_af_pram->iaddr_l = 0;
900         p_af_pram->gaddr_h = 0;
901         p_af_pram->gaddr_l = 0;
902 }
903
904 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
905                                          int thread_tx, int thread_rx)
906 {
907         uec_init_cmd_pram_t             *p_init_enet_param;
908         u32                             init_enet_param_offset;
909         uec_info_t                      *uec_info;
910         int                             i;
911         int                             snum;
912         u32                             init_enet_offset;
913         u32                             entry_val;
914         u32                             command;
915         u32                             cecr_subblock;
916
917         uec_info = uec->uec_info;
918
919         /* Allocate init enet command parameter */
920         uec->init_enet_param_offset = qe_muram_alloc(
921                                         sizeof(uec_init_cmd_pram_t), 4);
922         init_enet_param_offset = uec->init_enet_param_offset;
923         uec->p_init_enet_param = (uec_init_cmd_pram_t *)
924                                 qe_muram_addr(uec->init_enet_param_offset);
925
926         /* Zero init enet command struct */
927         memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
928
929         /* Init the command struct */
930         p_init_enet_param = uec->p_init_enet_param;
931         p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
932         p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
933         p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
934         p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
935         p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
936         p_init_enet_param->largestexternallookupkeysize = 0;
937
938         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
939                                          << ENET_INIT_PARAM_RGF_SHIFT;
940         p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
941                                          << ENET_INIT_PARAM_TGF_SHIFT;
942
943         /* Init Rx global parameter pointer */
944         p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
945                                                  (u32)uec_info->risc_rx;
946
947         /* Init Rx threads */
948         for (i = 0; i < (thread_rx + 1); i++) {
949                 if ((snum = qe_get_snum()) < 0) {
950                         printf("%s can not get snum\n", __FUNCTION__);
951                         return -ENOMEM;
952                 }
953
954                 if (i==0) {
955                         init_enet_offset = 0;
956                 } else {
957                         init_enet_offset = qe_muram_alloc(
958                                         sizeof(uec_thread_rx_pram_t),
959                                          UEC_THREAD_RX_PRAM_ALIGNMENT);
960                 }
961
962                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
963                                  init_enet_offset | (u32)uec_info->risc_rx;
964                 p_init_enet_param->rxthread[i] = entry_val;
965         }
966
967         /* Init Tx global parameter pointer */
968         p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
969                                          (u32)uec_info->risc_tx;
970
971         /* Init Tx threads */
972         for (i = 0; i < thread_tx; i++) {
973                 if ((snum = qe_get_snum()) < 0) {
974                         printf("%s can not get snum\n", __FUNCTION__);
975                         return -ENOMEM;
976                 }
977
978                 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
979                                                  UEC_THREAD_TX_PRAM_ALIGNMENT);
980
981                 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
982                                  init_enet_offset | (u32)uec_info->risc_tx;
983                 p_init_enet_param->txthread[i] = entry_val;
984         }
985
986         __asm__ __volatile__("sync");
987
988         /* Issue QE command */
989         command = QE_INIT_TX_RX;
990         cecr_subblock = ucc_fast_get_qe_cr_subblock(
991                                 uec->uec_info->uf_info.ucc_num);
992         qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
993                                                  init_enet_param_offset);
994
995         return 0;
996 }
997
998 static int uec_startup(uec_private_t *uec)
999 {
1000         uec_info_t                      *uec_info;
1001         ucc_fast_info_t                 *uf_info;
1002         ucc_fast_private_t              *uccf;
1003         ucc_fast_t                      *uf_regs;
1004         uec_t                           *uec_regs;
1005         int                             num_threads_tx;
1006         int                             num_threads_rx;
1007         u32                             utbipar;
1008         u32                             length;
1009         u32                             align;
1010         qe_bd_t                         *bd;
1011         u8                              *buf;
1012         int                             i;
1013
1014         if (!uec || !uec->uec_info) {
1015                 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1016                 return -EINVAL;
1017         }
1018
1019         uec_info = uec->uec_info;
1020         uf_info = &(uec_info->uf_info);
1021
1022         /* Check if Rx BD ring len is illegal */
1023         if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1024                 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1025                 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1026                          __FUNCTION__);
1027                 return -EINVAL;
1028         }
1029
1030         /* Check if Tx BD ring len is illegal */
1031         if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1032                 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1033                          __FUNCTION__);
1034                 return -EINVAL;
1035         }
1036
1037         /* Check if MRBLR is illegal */
1038         if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
1039                 printf("%s: max rx buffer length must be mutliple of 128.\n",
1040                          __FUNCTION__);
1041                 return -EINVAL;
1042         }
1043
1044         /* Both Rx and Tx are stopped */
1045         uec->grace_stopped_rx = 1;
1046         uec->grace_stopped_tx = 1;
1047
1048         /* Init UCC fast */
1049         if (ucc_fast_init(uf_info, &uccf)) {
1050                 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1051                 return -ENOMEM;
1052         }
1053
1054         /* Save uccf */
1055         uec->uccf = uccf;
1056
1057         /* Convert the Tx threads number */
1058         if (uec_convert_threads_num(uec_info->num_threads_tx,
1059                                          &num_threads_tx)) {
1060                 return -EINVAL;
1061         }
1062
1063         /* Convert the Rx threads number */
1064         if (uec_convert_threads_num(uec_info->num_threads_rx,
1065                                          &num_threads_rx)) {
1066                 return -EINVAL;
1067         }
1068
1069         uf_regs = uccf->uf_regs;
1070
1071         /* UEC register is following UCC fast registers */
1072         uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1073
1074         /* Save the UEC register pointer to UEC private struct */
1075         uec->uec_regs = uec_regs;
1076
1077         /* Init UPSMR, enable hardware statistics (UCC) */
1078         out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1079
1080         /* Init MACCFG1, flow control disable, disable Tx and Rx */
1081         out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1082
1083         /* Init MACCFG2, length check, MAC PAD and CRC enable */
1084         out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1085
1086         /* Setup MAC interface mode */
1087         uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
1088
1089         /* Setup MII management base */
1090 #ifndef CONFIG_eTSEC_MDIO_BUS
1091         uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1092 #else
1093         uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1094 #endif
1095
1096         /* Setup MII master clock source */
1097         qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1098
1099         /* Setup UTBIPAR */
1100         utbipar = in_be32(&uec_regs->utbipar);
1101         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1102
1103         /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1104          * This frees up the remaining SMI addresses for use.
1105          */
1106         utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
1107         out_be32(&uec_regs->utbipar, utbipar);
1108
1109         /* Configure the TBI for SGMII operation */
1110         if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) &&
1111            (uec->uec_info->speed == SPEED_1000)) {
1112                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1113                         ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1114
1115                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1116                         ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1117
1118                 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1119                         ENET_TBI_MII_CR, TBICR_SETTINGS);
1120         }
1121
1122         /* Allocate Tx BDs */
1123         length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1124                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1125                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1126         if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1127                  UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1128                 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1129         }
1130
1131         align = UEC_TX_BD_RING_ALIGNMENT;
1132         uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1133         if (uec->tx_bd_ring_offset != 0) {
1134                 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1135                                                  & ~(align - 1));
1136         }
1137
1138         /* Zero all of Tx BDs */
1139         memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1140
1141         /* Allocate Rx BDs */
1142         length = uec_info->rx_bd_ring_len * SIZEOFBD;
1143         align = UEC_RX_BD_RING_ALIGNMENT;
1144         uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1145         if (uec->rx_bd_ring_offset != 0) {
1146                 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1147                                                          & ~(align - 1));
1148         }
1149
1150         /* Zero all of Rx BDs */
1151         memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1152
1153         /* Allocate Rx buffer */
1154         length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1155         align = UEC_RX_DATA_BUF_ALIGNMENT;
1156         uec->rx_buf_offset = (u32)malloc(length + align);
1157         if (uec->rx_buf_offset != 0) {
1158                 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1159                                                  & ~(align - 1));
1160         }
1161
1162         /* Zero all of the Rx buffer */
1163         memset((void *)(uec->rx_buf_offset), 0, length + align);
1164
1165         /* Init TxBD ring */
1166         bd = (qe_bd_t *)uec->p_tx_bd_ring;
1167         uec->txBd = bd;
1168
1169         for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1170                 BD_DATA_CLEAR(bd);
1171                 BD_STATUS_SET(bd, 0);
1172                 BD_LENGTH_SET(bd, 0);
1173                 bd ++;
1174         }
1175         BD_STATUS_SET((--bd), TxBD_WRAP);
1176
1177         /* Init RxBD ring */
1178         bd = (qe_bd_t *)uec->p_rx_bd_ring;
1179         uec->rxBd = bd;
1180         buf = uec->p_rx_buf;
1181         for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1182                 BD_DATA_SET(bd, buf);
1183                 BD_LENGTH_SET(bd, 0);
1184                 BD_STATUS_SET(bd, RxBD_EMPTY);
1185                 buf += MAX_RXBUF_LEN;
1186                 bd ++;
1187         }
1188         BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1189
1190         /* Init global Tx parameter RAM */
1191         uec_init_tx_parameter(uec, num_threads_tx);
1192
1193         /* Init global Rx parameter RAM */
1194         uec_init_rx_parameter(uec, num_threads_rx);
1195
1196         /* Init ethernet Tx and Rx parameter command */
1197         if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1198                                          num_threads_rx)) {
1199                 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1200                 return -ENOMEM;
1201         }
1202
1203         return 0;
1204 }
1205
1206 static int uec_init(struct eth_device* dev, bd_t *bd)
1207 {
1208         uec_private_t           *uec;
1209         int                     err, i;
1210         struct phy_info         *curphy;
1211 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1212     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1213         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1214 #endif
1215
1216         uec = (uec_private_t *)dev->priv;
1217
1218         if (uec->the_first_run == 0) {
1219 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1220     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1221         /* QE9 and QE12 need to be set for enabling QE MII managment signals */
1222         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
1223         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1224 #endif
1225
1226                 err = init_phy(dev);
1227                 if (err) {
1228                         printf("%s: Cannot initialize PHY, aborting.\n",
1229                                dev->name);
1230                         return err;
1231                 }
1232
1233                 curphy = uec->mii_info->phyinfo;
1234
1235                 if (curphy->config_aneg) {
1236                         err = curphy->config_aneg(uec->mii_info);
1237                         if (err) {
1238                                 printf("%s: Can't negotiate PHY\n", dev->name);
1239                                 return err;
1240                         }
1241                 }
1242
1243                 /* Give PHYs up to 5 sec to report a link */
1244                 i = 50;
1245                 do {
1246                         err = curphy->read_status(uec->mii_info);
1247                         if (!(((i-- > 0) && !uec->mii_info->link) || err))
1248                                 break;
1249                         udelay(100000);
1250                 } while (1);
1251
1252 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1253     defined(CONFIG_P1021) || defined(CONFIG_P1025)
1254                 /* QE12 needs to be released for enabling LBCTL signal*/
1255                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1256 #endif
1257
1258                 if (err || i <= 0)
1259                         printf("warning: %s: timeout on PHY link\n", dev->name);
1260
1261                 adjust_link(dev);
1262                 uec->the_first_run = 1;
1263         }
1264
1265         /* Set up the MAC address */
1266         if (dev->enetaddr[0] & 0x01) {
1267                 printf("%s: MacAddress is multcast address\n",
1268                          __FUNCTION__);
1269                 return -1;
1270         }
1271         uec_set_mac_address(uec, dev->enetaddr);
1272
1273
1274         err = uec_open(uec, COMM_DIR_RX_AND_TX);
1275         if (err) {
1276                 printf("%s: cannot enable UEC device\n", dev->name);
1277                 return -1;
1278         }
1279
1280         phy_change(dev);
1281
1282         return (uec->mii_info->link ? 0 : -1);
1283 }
1284
1285 static void uec_halt(struct eth_device* dev)
1286 {
1287         uec_private_t   *uec = (uec_private_t *)dev->priv;
1288         uec_stop(uec, COMM_DIR_RX_AND_TX);
1289 }
1290
1291 static int uec_send(struct eth_device *dev, void *buf, int len)
1292 {
1293         uec_private_t           *uec;
1294         ucc_fast_private_t      *uccf;
1295         volatile qe_bd_t        *bd;
1296         u16                     status;
1297         int                     i;
1298         int                     result = 0;
1299
1300         uec = (uec_private_t *)dev->priv;
1301         uccf = uec->uccf;
1302         bd = uec->txBd;
1303
1304         /* Find an empty TxBD */
1305         for (i = 0; bd->status & TxBD_READY; i++) {
1306                 if (i > 0x100000) {
1307                         printf("%s: tx buffer not ready\n", dev->name);
1308                         return result;
1309                 }
1310         }
1311
1312         /* Init TxBD */
1313         BD_DATA_SET(bd, buf);
1314         BD_LENGTH_SET(bd, len);
1315         status = bd->status;
1316         status &= BD_WRAP;
1317         status |= (TxBD_READY | TxBD_LAST);
1318         BD_STATUS_SET(bd, status);
1319
1320         /* Tell UCC to transmit the buffer */
1321         ucc_fast_transmit_on_demand(uccf);
1322
1323         /* Wait for buffer to be transmitted */
1324         for (i = 0; bd->status & TxBD_READY; i++) {
1325                 if (i > 0x100000) {
1326                         printf("%s: tx error\n", dev->name);
1327                         return result;
1328                 }
1329         }
1330
1331         /* Ok, the buffer be transimitted */
1332         BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1333         uec->txBd = bd;
1334         result = 1;
1335
1336         return result;
1337 }
1338
1339 static int uec_recv(struct eth_device* dev)
1340 {
1341         uec_private_t           *uec = dev->priv;
1342         volatile qe_bd_t        *bd;
1343         u16                     status;
1344         u16                     len;
1345         u8                      *data;
1346
1347         bd = uec->rxBd;
1348         status = bd->status;
1349
1350         while (!(status & RxBD_EMPTY)) {
1351                 if (!(status & RxBD_ERROR)) {
1352                         data = BD_DATA(bd);
1353                         len = BD_LENGTH(bd);
1354                         NetReceive(data, len);
1355                 } else {
1356                         printf("%s: Rx error\n", dev->name);
1357                 }
1358                 status &= BD_CLEAN;
1359                 BD_LENGTH_SET(bd, 0);
1360                 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1361                 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1362                 status = bd->status;
1363         }
1364         uec->rxBd = bd;
1365
1366         return 1;
1367 }
1368
1369 int uec_initialize(bd_t *bis, uec_info_t *uec_info)
1370 {
1371         struct eth_device       *dev;
1372         int                     i;
1373         uec_private_t           *uec;
1374         int                     err;
1375
1376         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1377         if (!dev)
1378                 return 0;
1379         memset(dev, 0, sizeof(struct eth_device));
1380
1381         /* Allocate the UEC private struct */
1382         uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1383         if (!uec) {
1384                 return -ENOMEM;
1385         }
1386         memset(uec, 0, sizeof(uec_private_t));
1387
1388         /* Adjust uec_info */
1389 #if (MAX_QE_RISC == 4)
1390         uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1391         uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1392 #endif
1393
1394         devlist[uec_info->uf_info.ucc_num] = dev;
1395
1396         uec->uec_info = uec_info;
1397         uec->dev = dev;
1398
1399         sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
1400         dev->iobase = 0;
1401         dev->priv = (void *)uec;
1402         dev->init = uec_init;
1403         dev->halt = uec_halt;
1404         dev->send = uec_send;
1405         dev->recv = uec_recv;
1406
1407         /* Clear the ethnet address */
1408         for (i = 0; i < 6; i++)
1409                 dev->enetaddr[i] = 0;
1410
1411         eth_register(dev);
1412
1413         err = uec_startup(uec);
1414         if (err) {
1415                 printf("%s: Cannot configure net device, aborting.",dev->name);
1416                 return err;
1417         }
1418
1419 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1420         miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1421 #endif
1422
1423         return 1;
1424 }
1425
1426 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
1427 {
1428         int i;
1429
1430         for (i = 0; i < num; i++)
1431                 uec_initialize(bis, &uecs[i]);
1432
1433         return 0;
1434 }
1435
1436 int uec_standard_init(bd_t *bis)
1437 {
1438         return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
1439 }