1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
5 * Dave Liu <daveliu@freescale.com>
11 #include <linux/errno.h>
13 #include <linux/immap_qe.h>
21 /* Default UTBIPAR SMI address */
22 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
23 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
26 static uec_info_t uec_info[] = {
27 #ifdef CONFIG_UEC_ETH1
28 STD_UEC_INFO(1), /* UEC1 */
30 #ifdef CONFIG_UEC_ETH2
31 STD_UEC_INFO(2), /* UEC2 */
33 #ifdef CONFIG_UEC_ETH3
34 STD_UEC_INFO(3), /* UEC3 */
36 #ifdef CONFIG_UEC_ETH4
37 STD_UEC_INFO(4), /* UEC4 */
39 #ifdef CONFIG_UEC_ETH5
40 STD_UEC_INFO(5), /* UEC5 */
42 #ifdef CONFIG_UEC_ETH6
43 STD_UEC_INFO(6), /* UEC6 */
45 #ifdef CONFIG_UEC_ETH7
46 STD_UEC_INFO(7), /* UEC7 */
48 #ifdef CONFIG_UEC_ETH8
49 STD_UEC_INFO(8), /* UEC8 */
53 #define MAXCONTROLLERS (8)
55 static struct eth_device *devlist[MAXCONTROLLERS];
57 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
63 printf("%s: uec not initial\n", __FUNCTION__);
66 uec_regs = uec->uec_regs;
68 maccfg1 = in_be32(&uec_regs->maccfg1);
70 if (mode & COMM_DIR_TX) {
71 maccfg1 |= MACCFG1_ENABLE_TX;
72 out_be32(&uec_regs->maccfg1, maccfg1);
73 uec->mac_tx_enabled = 1;
76 if (mode & COMM_DIR_RX) {
77 maccfg1 |= MACCFG1_ENABLE_RX;
78 out_be32(&uec_regs->maccfg1, maccfg1);
79 uec->mac_rx_enabled = 1;
85 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
91 printf("%s: uec not initial\n", __FUNCTION__);
94 uec_regs = uec->uec_regs;
96 maccfg1 = in_be32(&uec_regs->maccfg1);
98 if (mode & COMM_DIR_TX) {
99 maccfg1 &= ~MACCFG1_ENABLE_TX;
100 out_be32(&uec_regs->maccfg1, maccfg1);
101 uec->mac_tx_enabled = 0;
104 if (mode & COMM_DIR_RX) {
105 maccfg1 &= ~MACCFG1_ENABLE_RX;
106 out_be32(&uec_regs->maccfg1, maccfg1);
107 uec->mac_rx_enabled = 0;
113 static int uec_graceful_stop_tx(uec_private_t *uec)
119 if (!uec || !uec->uccf) {
120 printf("%s: No handle passed.\n", __FUNCTION__);
124 uf_regs = uec->uccf->uf_regs;
126 /* Clear the grace stop event */
127 out_be32(&uf_regs->ucce, UCCE_GRA);
129 /* Issue host command */
131 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
132 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
133 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
135 /* Wait for command to complete */
137 ucce = in_be32(&uf_regs->ucce);
138 } while (! (ucce & UCCE_GRA));
140 uec->grace_stopped_tx = 1;
145 static int uec_graceful_stop_rx(uec_private_t *uec)
151 printf("%s: No handle passed.\n", __FUNCTION__);
155 if (!uec->p_rx_glbl_pram) {
156 printf("%s: No init rx global parameter\n", __FUNCTION__);
160 /* Clear acknowledge bit */
161 ack = uec->p_rx_glbl_pram->rxgstpack;
162 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
163 uec->p_rx_glbl_pram->rxgstpack = ack;
165 /* Keep issuing cmd and checking ack bit until it is asserted */
167 /* Issue host command */
169 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
170 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
171 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
172 ack = uec->p_rx_glbl_pram->rxgstpack;
173 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
175 uec->grace_stopped_rx = 1;
180 static int uec_restart_tx(uec_private_t *uec)
184 if (!uec || !uec->uec_info) {
185 printf("%s: No handle passed.\n", __FUNCTION__);
190 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
191 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
192 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
194 uec->grace_stopped_tx = 0;
199 static int uec_restart_rx(uec_private_t *uec)
203 if (!uec || !uec->uec_info) {
204 printf("%s: No handle passed.\n", __FUNCTION__);
209 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
210 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
211 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
213 uec->grace_stopped_rx = 0;
218 static int uec_open(uec_private_t *uec, comm_dir_e mode)
220 ucc_fast_private_t *uccf;
222 if (!uec || !uec->uccf) {
223 printf("%s: No handle passed.\n", __FUNCTION__);
228 /* check if the UCC number is in range. */
229 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
230 printf("%s: ucc_num out of range.\n", __FUNCTION__);
235 uec_mac_enable(uec, mode);
237 /* Enable UCC fast */
238 ucc_fast_enable(uccf, mode);
240 /* RISC microcode start */
241 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
244 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
251 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
253 if (!uec || !uec->uccf) {
254 printf("%s: No handle passed.\n", __FUNCTION__);
258 /* check if the UCC number is in range. */
259 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
260 printf("%s: ucc_num out of range.\n", __FUNCTION__);
263 /* Stop any transmissions */
264 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
265 uec_graceful_stop_tx(uec);
267 /* Stop any receptions */
268 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
269 uec_graceful_stop_rx(uec);
272 /* Disable the UCC fast */
273 ucc_fast_disable(uec->uccf, mode);
275 /* Disable the MAC */
276 uec_mac_disable(uec, mode);
281 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
287 printf("%s: uec not initial\n", __FUNCTION__);
290 uec_regs = uec->uec_regs;
292 if (duplex == DUPLEX_HALF) {
293 maccfg2 = in_be32(&uec_regs->maccfg2);
294 maccfg2 &= ~MACCFG2_FDX;
295 out_be32(&uec_regs->maccfg2, maccfg2);
298 if (duplex == DUPLEX_FULL) {
299 maccfg2 = in_be32(&uec_regs->maccfg2);
300 maccfg2 |= MACCFG2_FDX;
301 out_be32(&uec_regs->maccfg2, maccfg2);
307 static int uec_set_mac_if_mode(uec_private_t *uec,
308 phy_interface_t if_mode, int speed)
310 phy_interface_t enet_if_mode;
316 printf("%s: uec not initial\n", __FUNCTION__);
320 uec_regs = uec->uec_regs;
321 enet_if_mode = if_mode;
323 maccfg2 = in_be32(&uec_regs->maccfg2);
324 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
326 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
327 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
331 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
332 switch (enet_if_mode) {
333 case PHY_INTERFACE_MODE_MII:
335 case PHY_INTERFACE_MODE_RGMII:
336 upsmr |= (UPSMR_RPM | UPSMR_R10M);
338 case PHY_INTERFACE_MODE_RMII:
339 upsmr |= (UPSMR_R10M | UPSMR_RMM);
347 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
348 switch (enet_if_mode) {
349 case PHY_INTERFACE_MODE_MII:
351 case PHY_INTERFACE_MODE_RGMII:
354 case PHY_INTERFACE_MODE_RMII:
363 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
364 switch (enet_if_mode) {
365 case PHY_INTERFACE_MODE_GMII:
367 case PHY_INTERFACE_MODE_TBI:
370 case PHY_INTERFACE_MODE_RTBI:
371 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
373 case PHY_INTERFACE_MODE_RGMII_RXID:
374 case PHY_INTERFACE_MODE_RGMII_TXID:
375 case PHY_INTERFACE_MODE_RGMII_ID:
376 case PHY_INTERFACE_MODE_RGMII:
379 case PHY_INTERFACE_MODE_SGMII:
392 out_be32(&uec_regs->maccfg2, maccfg2);
393 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
398 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
400 uint timeout = 0x1000;
403 miimcfg = in_be32(&uec_mii_regs->miimcfg);
404 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
405 out_be32(&uec_mii_regs->miimcfg, miimcfg);
407 /* Wait until the bus is free */
408 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
410 printf("%s: The MII Bus is stuck!", __FUNCTION__);
417 static int init_phy(struct eth_device *dev)
420 uec_mii_t *umii_regs;
421 struct uec_mii_info *mii_info;
422 struct phy_info *curphy;
425 uec = (uec_private_t *)dev->priv;
426 umii_regs = uec->uec_mii_regs;
432 mii_info = malloc(sizeof(*mii_info));
434 printf("%s: Could not allocate mii_info", dev->name);
437 memset(mii_info, 0, sizeof(*mii_info));
439 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
440 mii_info->speed = SPEED_1000;
442 mii_info->speed = SPEED_100;
445 mii_info->duplex = DUPLEX_FULL;
449 mii_info->advertising = (ADVERTISED_10baseT_Half |
450 ADVERTISED_10baseT_Full |
451 ADVERTISED_100baseT_Half |
452 ADVERTISED_100baseT_Full |
453 ADVERTISED_1000baseT_Full);
454 mii_info->autoneg = 1;
455 mii_info->mii_id = uec->uec_info->phy_address;
458 mii_info->mdio_read = &uec_read_phy_reg;
459 mii_info->mdio_write = &uec_write_phy_reg;
461 uec->mii_info = mii_info;
463 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
465 if (init_mii_management_configuration(umii_regs)) {
466 printf("%s: The MII Bus is stuck!", dev->name);
471 /* get info for this PHY */
472 curphy = uec_get_phy_info(uec->mii_info);
474 printf("%s: No PHY found", dev->name);
479 mii_info->phyinfo = curphy;
481 /* Run the commands which initialize the PHY */
483 err = curphy->init(uec->mii_info);
497 static void adjust_link(struct eth_device *dev)
499 uec_private_t *uec = (uec_private_t *)dev->priv;
500 struct uec_mii_info *mii_info = uec->mii_info;
502 extern void change_phy_interface_mode(struct eth_device *dev,
503 phy_interface_t mode, int speed);
505 if (mii_info->link) {
506 /* Now we make sure that we can be in full duplex mode.
507 * If not, we operate in half-duplex mode. */
508 if (mii_info->duplex != uec->oldduplex) {
509 if (!(mii_info->duplex)) {
510 uec_set_mac_duplex(uec, DUPLEX_HALF);
511 printf("%s: Half Duplex\n", dev->name);
513 uec_set_mac_duplex(uec, DUPLEX_FULL);
514 printf("%s: Full Duplex\n", dev->name);
516 uec->oldduplex = mii_info->duplex;
519 if (mii_info->speed != uec->oldspeed) {
520 phy_interface_t mode =
521 uec->uec_info->enet_interface_type;
522 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
523 switch (mii_info->speed) {
527 printf ("switching to rgmii 100\n");
528 mode = PHY_INTERFACE_MODE_RGMII;
531 printf ("switching to rgmii 10\n");
532 mode = PHY_INTERFACE_MODE_RGMII;
535 printf("%s: Ack,Speed(%d)is illegal\n",
536 dev->name, mii_info->speed);
542 change_phy_interface_mode(dev, mode, mii_info->speed);
543 /* change the MAC interface mode */
544 uec_set_mac_if_mode(uec, mode, mii_info->speed);
546 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
547 uec->oldspeed = mii_info->speed;
551 printf("%s: Link is up\n", dev->name);
555 } else { /* if (mii_info->link) */
557 printf("%s: Link is down\n", dev->name);
565 static void phy_change(struct eth_device *dev)
567 uec_private_t *uec = (uec_private_t *)dev->priv;
569 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
570 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
572 /* QE9 and QE12 need to be set for enabling QE MII managment signals */
573 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
574 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
577 /* Update the link, speed, duplex */
578 uec->mii_info->phyinfo->read_status(uec->mii_info);
580 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
582 * QE12 is muxed with LBCTL, it needs to be released for enabling
583 * LBCTL signal for LBC usage.
585 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
588 /* Adjust the interface according to speed */
592 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
595 * Find a device index from the devlist by name
598 * The index where the device is located, -1 on error
600 static int uec_miiphy_find_dev_by_name(const char *devname)
604 for (i = 0; i < MAXCONTROLLERS; i++) {
605 if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
610 /* If device cannot be found, returns -1 */
611 if (i == MAXCONTROLLERS) {
612 debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
620 * Read a MII PHY register.
625 static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
627 unsigned short value = 0;
630 if (bus->name == NULL) {
631 debug("%s: NULL pointer given\n", __FUNCTION__);
633 devindex = uec_miiphy_find_dev_by_name(bus->name);
635 value = uec_read_phy_reg(devlist[devindex], addr, reg);
642 * Write a MII PHY register.
647 static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
652 if (bus->name == NULL) {
653 debug("%s: NULL pointer given\n", __FUNCTION__);
655 devindex = uec_miiphy_find_dev_by_name(bus->name);
657 uec_write_phy_reg(devlist[devindex], addr, reg, value);
664 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
671 printf("%s: uec not initial\n", __FUNCTION__);
675 uec_regs = uec->uec_regs;
677 /* if a station address of 0x12345678ABCD, perform a write to
678 MACSTNADDR1 of 0xCDAB7856,
679 MACSTNADDR2 of 0x34120000 */
681 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
682 (mac_addr[3] << 8) | (mac_addr[2]);
683 out_be32(&uec_regs->macstnaddr1, mac_addr1);
685 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
686 out_be32(&uec_regs->macstnaddr2, mac_addr2);
691 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
692 int *threads_num_ret)
694 int num_threads_numerica;
696 switch (threads_num) {
697 case UEC_NUM_OF_THREADS_1:
698 num_threads_numerica = 1;
700 case UEC_NUM_OF_THREADS_2:
701 num_threads_numerica = 2;
703 case UEC_NUM_OF_THREADS_4:
704 num_threads_numerica = 4;
706 case UEC_NUM_OF_THREADS_6:
707 num_threads_numerica = 6;
709 case UEC_NUM_OF_THREADS_8:
710 num_threads_numerica = 8;
713 printf("%s: Bad number of threads value.",
718 *threads_num_ret = num_threads_numerica;
723 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
725 uec_info_t *uec_info;
730 uec_info = uec->uec_info;
732 /* Alloc global Tx parameter RAM page */
733 uec->tx_glbl_pram_offset = qe_muram_alloc(
734 sizeof(uec_tx_global_pram_t),
735 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
736 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
737 qe_muram_addr(uec->tx_glbl_pram_offset);
739 /* Zero the global Tx prameter RAM */
740 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
742 /* Init global Tx parameter RAM */
744 /* TEMODER, RMON statistics disable, one Tx queue */
745 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
748 uec->send_q_mem_reg_offset = qe_muram_alloc(
749 sizeof(uec_send_queue_qd_t),
750 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
751 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
752 qe_muram_addr(uec->send_q_mem_reg_offset);
753 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
755 /* Setup the table with TxBDs ring */
756 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
758 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
759 (u32)(uec->p_tx_bd_ring));
760 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
763 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
764 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
766 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
767 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
769 /* TSTATE, global snooping, big endian, the CSB bus selected */
770 bmrx = BMR_INIT_VALUE;
771 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
774 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
775 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
779 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
780 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
784 uec->thread_dat_tx_offset = qe_muram_alloc(
785 num_threads_tx * sizeof(uec_thread_data_tx_t) +
786 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
788 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
789 qe_muram_addr(uec->thread_dat_tx_offset);
790 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
793 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
797 uec_82xx_address_filtering_pram_t *p_af_pram;
799 /* Allocate global Rx parameter RAM page */
800 uec->rx_glbl_pram_offset = qe_muram_alloc(
801 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
802 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
803 qe_muram_addr(uec->rx_glbl_pram_offset);
805 /* Zero Global Rx parameter RAM */
806 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
808 /* Init global Rx parameter RAM */
809 /* REMODER, Extended feature mode disable, VLAN disable,
810 LossLess flow control disable, Receive firmware statisic disable,
811 Extended address parsing mode disable, One Rx queues,
812 Dynamic maximum/minimum frame length disable, IP checksum check
813 disable, IP address alignment disable
815 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
818 uec->thread_dat_rx_offset = qe_muram_alloc(
819 num_threads_rx * sizeof(uec_thread_data_rx_t),
820 UEC_THREAD_DATA_ALIGNMENT);
821 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
822 qe_muram_addr(uec->thread_dat_rx_offset);
823 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
826 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
828 /* RxRMON base pointer, we don't need it */
829 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
831 /* IntCoalescingPTR, we don't need it, no interrupt */
832 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
834 /* RSTATE, global snooping, big endian, the CSB bus selected */
835 bmrx = BMR_INIT_VALUE;
836 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
839 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
842 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
843 sizeof(uec_rx_bd_queues_entry_t) + \
844 sizeof(uec_rx_prefetched_bds_t),
845 UEC_RX_BD_QUEUES_ALIGNMENT);
846 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
847 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
850 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
851 sizeof(uec_rx_prefetched_bds_t));
852 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
853 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
854 (u32)uec->p_rx_bd_ring);
857 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
859 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
861 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
863 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
865 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
867 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
869 for (i = 0; i < 8; i++) {
870 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
874 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
876 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
878 /* Clear PQ2 style address filtering hash table */
879 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
880 uec->p_rx_glbl_pram->addressfiltering;
882 p_af_pram->iaddr_h = 0;
883 p_af_pram->iaddr_l = 0;
884 p_af_pram->gaddr_h = 0;
885 p_af_pram->gaddr_l = 0;
888 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
889 int thread_tx, int thread_rx)
891 uec_init_cmd_pram_t *p_init_enet_param;
892 u32 init_enet_param_offset;
893 uec_info_t *uec_info;
896 u32 init_enet_offset;
901 uec_info = uec->uec_info;
903 /* Allocate init enet command parameter */
904 uec->init_enet_param_offset = qe_muram_alloc(
905 sizeof(uec_init_cmd_pram_t), 4);
906 init_enet_param_offset = uec->init_enet_param_offset;
907 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
908 qe_muram_addr(uec->init_enet_param_offset);
910 /* Zero init enet command struct */
911 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
913 /* Init the command struct */
914 p_init_enet_param = uec->p_init_enet_param;
915 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
916 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
917 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
918 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
919 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
920 p_init_enet_param->largestexternallookupkeysize = 0;
922 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
923 << ENET_INIT_PARAM_RGF_SHIFT;
924 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
925 << ENET_INIT_PARAM_TGF_SHIFT;
927 /* Init Rx global parameter pointer */
928 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
929 (u32)uec_info->risc_rx;
931 /* Init Rx threads */
932 for (i = 0; i < (thread_rx + 1); i++) {
933 if ((snum = qe_get_snum()) < 0) {
934 printf("%s can not get snum\n", __FUNCTION__);
939 init_enet_offset = 0;
941 init_enet_offset = qe_muram_alloc(
942 sizeof(uec_thread_rx_pram_t),
943 UEC_THREAD_RX_PRAM_ALIGNMENT);
946 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
947 init_enet_offset | (u32)uec_info->risc_rx;
948 p_init_enet_param->rxthread[i] = entry_val;
951 /* Init Tx global parameter pointer */
952 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
953 (u32)uec_info->risc_tx;
955 /* Init Tx threads */
956 for (i = 0; i < thread_tx; i++) {
957 if ((snum = qe_get_snum()) < 0) {
958 printf("%s can not get snum\n", __FUNCTION__);
962 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
963 UEC_THREAD_TX_PRAM_ALIGNMENT);
965 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
966 init_enet_offset | (u32)uec_info->risc_tx;
967 p_init_enet_param->txthread[i] = entry_val;
970 __asm__ __volatile__("sync");
972 /* Issue QE command */
973 command = QE_INIT_TX_RX;
974 cecr_subblock = ucc_fast_get_qe_cr_subblock(
975 uec->uec_info->uf_info.ucc_num);
976 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
977 init_enet_param_offset);
982 static int uec_startup(uec_private_t *uec)
984 uec_info_t *uec_info;
985 ucc_fast_info_t *uf_info;
986 ucc_fast_private_t *uccf;
998 if (!uec || !uec->uec_info) {
999 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1003 uec_info = uec->uec_info;
1004 uf_info = &(uec_info->uf_info);
1006 /* Check if Rx BD ring len is illegal */
1007 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1008 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1009 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1014 /* Check if Tx BD ring len is illegal */
1015 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1016 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1021 /* Check if MRBLR is illegal */
1022 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
1023 printf("%s: max rx buffer length must be mutliple of 128.\n",
1028 /* Both Rx and Tx are stopped */
1029 uec->grace_stopped_rx = 1;
1030 uec->grace_stopped_tx = 1;
1033 if (ucc_fast_init(uf_info, &uccf)) {
1034 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1041 /* Convert the Tx threads number */
1042 if (uec_convert_threads_num(uec_info->num_threads_tx,
1047 /* Convert the Rx threads number */
1048 if (uec_convert_threads_num(uec_info->num_threads_rx,
1053 uf_regs = uccf->uf_regs;
1055 /* UEC register is following UCC fast registers */
1056 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1058 /* Save the UEC register pointer to UEC private struct */
1059 uec->uec_regs = uec_regs;
1061 /* Init UPSMR, enable hardware statistics (UCC) */
1062 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1064 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1065 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1067 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1068 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1070 /* Setup MAC interface mode */
1071 uec_set_mac_if_mode(uec, uec_info->enet_interface_type, uec_info->speed);
1073 /* Setup MII management base */
1074 #ifndef CONFIG_eTSEC_MDIO_BUS
1075 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1077 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1080 /* Setup MII master clock source */
1081 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1084 utbipar = in_be32(&uec_regs->utbipar);
1085 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1087 /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1088 * This frees up the remaining SMI addresses for use.
1090 utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
1091 out_be32(&uec_regs->utbipar, utbipar);
1093 /* Configure the TBI for SGMII operation */
1094 if ((uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII) &&
1095 (uec->uec_info->speed == SPEED_1000)) {
1096 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1097 ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1099 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1100 ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1102 uec_write_phy_reg(uec->dev, uec_regs->utbipar,
1103 ENET_TBI_MII_CR, TBICR_SETTINGS);
1106 /* Allocate Tx BDs */
1107 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1108 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1109 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1110 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1111 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1112 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1115 align = UEC_TX_BD_RING_ALIGNMENT;
1116 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1117 if (uec->tx_bd_ring_offset != 0) {
1118 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1122 /* Zero all of Tx BDs */
1123 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1125 /* Allocate Rx BDs */
1126 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1127 align = UEC_RX_BD_RING_ALIGNMENT;
1128 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1129 if (uec->rx_bd_ring_offset != 0) {
1130 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1134 /* Zero all of Rx BDs */
1135 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1137 /* Allocate Rx buffer */
1138 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1139 align = UEC_RX_DATA_BUF_ALIGNMENT;
1140 uec->rx_buf_offset = (u32)malloc(length + align);
1141 if (uec->rx_buf_offset != 0) {
1142 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1146 /* Zero all of the Rx buffer */
1147 memset((void *)(uec->rx_buf_offset), 0, length + align);
1149 /* Init TxBD ring */
1150 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1153 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1155 BD_STATUS_SET(bd, 0);
1156 BD_LENGTH_SET(bd, 0);
1159 BD_STATUS_SET((--bd), TxBD_WRAP);
1161 /* Init RxBD ring */
1162 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1164 buf = uec->p_rx_buf;
1165 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1166 BD_DATA_SET(bd, buf);
1167 BD_LENGTH_SET(bd, 0);
1168 BD_STATUS_SET(bd, RxBD_EMPTY);
1169 buf += MAX_RXBUF_LEN;
1172 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1174 /* Init global Tx parameter RAM */
1175 uec_init_tx_parameter(uec, num_threads_tx);
1177 /* Init global Rx parameter RAM */
1178 uec_init_rx_parameter(uec, num_threads_rx);
1180 /* Init ethernet Tx and Rx parameter command */
1181 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1183 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1190 static int uec_init(struct eth_device* dev, bd_t *bd)
1194 struct phy_info *curphy;
1195 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1196 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1199 uec = (uec_private_t *)dev->priv;
1201 if (uec->the_first_run == 0) {
1202 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1203 /* QE9 and QE12 need to be set for enabling QE MII managment signals */
1204 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
1205 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1208 err = init_phy(dev);
1210 printf("%s: Cannot initialize PHY, aborting.\n",
1215 curphy = uec->mii_info->phyinfo;
1217 if (curphy->config_aneg) {
1218 err = curphy->config_aneg(uec->mii_info);
1220 printf("%s: Can't negotiate PHY\n", dev->name);
1225 /* Give PHYs up to 5 sec to report a link */
1228 err = curphy->read_status(uec->mii_info);
1229 if (!(((i-- > 0) && !uec->mii_info->link) || err))
1234 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
1235 /* QE12 needs to be released for enabling LBCTL signal*/
1236 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
1240 printf("warning: %s: timeout on PHY link\n", dev->name);
1243 uec->the_first_run = 1;
1246 /* Set up the MAC address */
1247 if (dev->enetaddr[0] & 0x01) {
1248 printf("%s: MacAddress is multcast address\n",
1252 uec_set_mac_address(uec, dev->enetaddr);
1255 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1257 printf("%s: cannot enable UEC device\n", dev->name);
1263 return (uec->mii_info->link ? 0 : -1);
1266 static void uec_halt(struct eth_device* dev)
1268 uec_private_t *uec = (uec_private_t *)dev->priv;
1269 uec_stop(uec, COMM_DIR_RX_AND_TX);
1272 static int uec_send(struct eth_device *dev, void *buf, int len)
1275 ucc_fast_private_t *uccf;
1276 volatile qe_bd_t *bd;
1281 uec = (uec_private_t *)dev->priv;
1285 /* Find an empty TxBD */
1286 for (i = 0; bd->status & TxBD_READY; i++) {
1288 printf("%s: tx buffer not ready\n", dev->name);
1294 BD_DATA_SET(bd, buf);
1295 BD_LENGTH_SET(bd, len);
1296 status = bd->status;
1298 status |= (TxBD_READY | TxBD_LAST);
1299 BD_STATUS_SET(bd, status);
1301 /* Tell UCC to transmit the buffer */
1302 ucc_fast_transmit_on_demand(uccf);
1304 /* Wait for buffer to be transmitted */
1305 for (i = 0; bd->status & TxBD_READY; i++) {
1307 printf("%s: tx error\n", dev->name);
1312 /* Ok, the buffer be transimitted */
1313 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1320 static int uec_recv(struct eth_device* dev)
1322 uec_private_t *uec = dev->priv;
1323 volatile qe_bd_t *bd;
1329 status = bd->status;
1331 while (!(status & RxBD_EMPTY)) {
1332 if (!(status & RxBD_ERROR)) {
1334 len = BD_LENGTH(bd);
1335 net_process_received_packet(data, len);
1337 printf("%s: Rx error\n", dev->name);
1340 BD_LENGTH_SET(bd, 0);
1341 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1342 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1343 status = bd->status;
1350 int uec_initialize(bd_t *bis, uec_info_t *uec_info)
1352 struct eth_device *dev;
1357 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1360 memset(dev, 0, sizeof(struct eth_device));
1362 /* Allocate the UEC private struct */
1363 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1367 memset(uec, 0, sizeof(uec_private_t));
1369 /* Adjust uec_info */
1370 #if (MAX_QE_RISC == 4)
1371 uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1372 uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1375 devlist[uec_info->uf_info.ucc_num] = dev;
1377 uec->uec_info = uec_info;
1380 sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num);
1382 dev->priv = (void *)uec;
1383 dev->init = uec_init;
1384 dev->halt = uec_halt;
1385 dev->send = uec_send;
1386 dev->recv = uec_recv;
1388 /* Clear the ethnet address */
1389 for (i = 0; i < 6; i++)
1390 dev->enetaddr[i] = 0;
1394 err = uec_startup(uec);
1396 printf("%s: Cannot configure net device, aborting.",dev->name);
1400 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1402 struct mii_dev *mdiodev = mdio_alloc();
1405 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
1406 mdiodev->read = uec_miiphy_read;
1407 mdiodev->write = uec_miiphy_write;
1409 retval = mdio_register(mdiodev);
1417 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
1421 for (i = 0; i < num; i++)
1422 uec_initialize(bis, &uecs[i]);
1427 int uec_standard_init(bd_t *bis)
1429 return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));