2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "asm/errno.h"
27 #include "asm/immap_qe.h"
34 #ifdef CONFIG_UEC_ETH1
35 static uec_info_t eth1_uec_info = {
37 .ucc_num = CONFIG_SYS_UEC1_UCC_NUM,
38 .rx_clock = CONFIG_SYS_UEC1_RX_CLK,
39 .tx_clock = CONFIG_SYS_UEC1_TX_CLK,
40 .eth_type = CONFIG_SYS_UEC1_ETH_TYPE,
42 #if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
43 .num_threads_tx = UEC_NUM_OF_THREADS_1,
44 .num_threads_rx = UEC_NUM_OF_THREADS_1,
46 .num_threads_tx = UEC_NUM_OF_THREADS_4,
47 .num_threads_rx = UEC_NUM_OF_THREADS_4,
49 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
50 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
53 .phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
54 .enet_interface = CONFIG_SYS_UEC1_INTERFACE_MODE,
57 #ifdef CONFIG_UEC_ETH2
58 static uec_info_t eth2_uec_info = {
60 .ucc_num = CONFIG_SYS_UEC2_UCC_NUM,
61 .rx_clock = CONFIG_SYS_UEC2_RX_CLK,
62 .tx_clock = CONFIG_SYS_UEC2_TX_CLK,
63 .eth_type = CONFIG_SYS_UEC2_ETH_TYPE,
65 #if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
66 .num_threads_tx = UEC_NUM_OF_THREADS_1,
67 .num_threads_rx = UEC_NUM_OF_THREADS_1,
69 .num_threads_tx = UEC_NUM_OF_THREADS_4,
70 .num_threads_rx = UEC_NUM_OF_THREADS_4,
72 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
73 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
76 .phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
77 .enet_interface = CONFIG_SYS_UEC2_INTERFACE_MODE,
80 #ifdef CONFIG_UEC_ETH3
81 static uec_info_t eth3_uec_info = {
83 .ucc_num = CONFIG_SYS_UEC3_UCC_NUM,
84 .rx_clock = CONFIG_SYS_UEC3_RX_CLK,
85 .tx_clock = CONFIG_SYS_UEC3_TX_CLK,
86 .eth_type = CONFIG_SYS_UEC3_ETH_TYPE,
88 #if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
89 .num_threads_tx = UEC_NUM_OF_THREADS_1,
90 .num_threads_rx = UEC_NUM_OF_THREADS_1,
92 .num_threads_tx = UEC_NUM_OF_THREADS_4,
93 .num_threads_rx = UEC_NUM_OF_THREADS_4,
95 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
96 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
99 .phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
100 .enet_interface = CONFIG_SYS_UEC3_INTERFACE_MODE,
103 #ifdef CONFIG_UEC_ETH4
104 static uec_info_t eth4_uec_info = {
106 .ucc_num = CONFIG_SYS_UEC4_UCC_NUM,
107 .rx_clock = CONFIG_SYS_UEC4_RX_CLK,
108 .tx_clock = CONFIG_SYS_UEC4_TX_CLK,
109 .eth_type = CONFIG_SYS_UEC4_ETH_TYPE,
111 #if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
112 .num_threads_tx = UEC_NUM_OF_THREADS_1,
113 .num_threads_rx = UEC_NUM_OF_THREADS_1,
115 .num_threads_tx = UEC_NUM_OF_THREADS_4,
116 .num_threads_rx = UEC_NUM_OF_THREADS_4,
118 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
119 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
120 .tx_bd_ring_len = 16,
121 .rx_bd_ring_len = 16,
122 .phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
123 .enet_interface = CONFIG_SYS_UEC4_INTERFACE_MODE,
126 #ifdef CONFIG_UEC_ETH5
127 static uec_info_t eth5_uec_info = {
129 .ucc_num = CONFIG_SYS_UEC5_UCC_NUM,
130 .rx_clock = CONFIG_SYS_UEC5_RX_CLK,
131 .tx_clock = CONFIG_SYS_UEC5_TX_CLK,
132 .eth_type = CONFIG_SYS_UEC5_ETH_TYPE,
134 #if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
135 .num_threads_tx = UEC_NUM_OF_THREADS_1,
136 .num_threads_rx = UEC_NUM_OF_THREADS_1,
138 .num_threads_tx = UEC_NUM_OF_THREADS_4,
139 .num_threads_rx = UEC_NUM_OF_THREADS_4,
141 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
142 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
143 .tx_bd_ring_len = 16,
144 .rx_bd_ring_len = 16,
145 .phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
146 .enet_interface = CONFIG_SYS_UEC5_INTERFACE_MODE,
149 #ifdef CONFIG_UEC_ETH6
150 static uec_info_t eth6_uec_info = {
152 .ucc_num = CONFIG_SYS_UEC6_UCC_NUM,
153 .rx_clock = CONFIG_SYS_UEC6_RX_CLK,
154 .tx_clock = CONFIG_SYS_UEC6_TX_CLK,
155 .eth_type = CONFIG_SYS_UEC6_ETH_TYPE,
157 #if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
158 .num_threads_tx = UEC_NUM_OF_THREADS_1,
159 .num_threads_rx = UEC_NUM_OF_THREADS_1,
161 .num_threads_tx = UEC_NUM_OF_THREADS_4,
162 .num_threads_rx = UEC_NUM_OF_THREADS_4,
164 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
165 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
166 .tx_bd_ring_len = 16,
167 .rx_bd_ring_len = 16,
168 .phy_address = CONFIG_SYS_UEC6_PHY_ADDR,
169 .enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE,
173 #define MAXCONTROLLERS (6)
175 static struct eth_device *devlist[MAXCONTROLLERS];
177 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
178 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
180 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
186 printf("%s: uec not initial\n", __FUNCTION__);
189 uec_regs = uec->uec_regs;
191 maccfg1 = in_be32(&uec_regs->maccfg1);
193 if (mode & COMM_DIR_TX) {
194 maccfg1 |= MACCFG1_ENABLE_TX;
195 out_be32(&uec_regs->maccfg1, maccfg1);
196 uec->mac_tx_enabled = 1;
199 if (mode & COMM_DIR_RX) {
200 maccfg1 |= MACCFG1_ENABLE_RX;
201 out_be32(&uec_regs->maccfg1, maccfg1);
202 uec->mac_rx_enabled = 1;
208 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
214 printf("%s: uec not initial\n", __FUNCTION__);
217 uec_regs = uec->uec_regs;
219 maccfg1 = in_be32(&uec_regs->maccfg1);
221 if (mode & COMM_DIR_TX) {
222 maccfg1 &= ~MACCFG1_ENABLE_TX;
223 out_be32(&uec_regs->maccfg1, maccfg1);
224 uec->mac_tx_enabled = 0;
227 if (mode & COMM_DIR_RX) {
228 maccfg1 &= ~MACCFG1_ENABLE_RX;
229 out_be32(&uec_regs->maccfg1, maccfg1);
230 uec->mac_rx_enabled = 0;
236 static int uec_graceful_stop_tx(uec_private_t *uec)
242 if (!uec || !uec->uccf) {
243 printf("%s: No handle passed.\n", __FUNCTION__);
247 uf_regs = uec->uccf->uf_regs;
249 /* Clear the grace stop event */
250 out_be32(&uf_regs->ucce, UCCE_GRA);
252 /* Issue host command */
254 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
255 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
256 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
258 /* Wait for command to complete */
260 ucce = in_be32(&uf_regs->ucce);
261 } while (! (ucce & UCCE_GRA));
263 uec->grace_stopped_tx = 1;
268 static int uec_graceful_stop_rx(uec_private_t *uec)
274 printf("%s: No handle passed.\n", __FUNCTION__);
278 if (!uec->p_rx_glbl_pram) {
279 printf("%s: No init rx global parameter\n", __FUNCTION__);
283 /* Clear acknowledge bit */
284 ack = uec->p_rx_glbl_pram->rxgstpack;
285 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
286 uec->p_rx_glbl_pram->rxgstpack = ack;
288 /* Keep issuing cmd and checking ack bit until it is asserted */
290 /* Issue host command */
292 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
293 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
294 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
295 ack = uec->p_rx_glbl_pram->rxgstpack;
296 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
298 uec->grace_stopped_rx = 1;
303 static int uec_restart_tx(uec_private_t *uec)
307 if (!uec || !uec->uec_info) {
308 printf("%s: No handle passed.\n", __FUNCTION__);
313 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
314 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
315 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
317 uec->grace_stopped_tx = 0;
322 static int uec_restart_rx(uec_private_t *uec)
326 if (!uec || !uec->uec_info) {
327 printf("%s: No handle passed.\n", __FUNCTION__);
332 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
333 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
334 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
336 uec->grace_stopped_rx = 0;
341 static int uec_open(uec_private_t *uec, comm_dir_e mode)
343 ucc_fast_private_t *uccf;
345 if (!uec || !uec->uccf) {
346 printf("%s: No handle passed.\n", __FUNCTION__);
351 /* check if the UCC number is in range. */
352 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
353 printf("%s: ucc_num out of range.\n", __FUNCTION__);
358 uec_mac_enable(uec, mode);
360 /* Enable UCC fast */
361 ucc_fast_enable(uccf, mode);
363 /* RISC microcode start */
364 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
367 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
374 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
376 ucc_fast_private_t *uccf;
378 if (!uec || !uec->uccf) {
379 printf("%s: No handle passed.\n", __FUNCTION__);
384 /* check if the UCC number is in range. */
385 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
386 printf("%s: ucc_num out of range.\n", __FUNCTION__);
389 /* Stop any transmissions */
390 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
391 uec_graceful_stop_tx(uec);
393 /* Stop any receptions */
394 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
395 uec_graceful_stop_rx(uec);
398 /* Disable the UCC fast */
399 ucc_fast_disable(uec->uccf, mode);
401 /* Disable the MAC */
402 uec_mac_disable(uec, mode);
407 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
413 printf("%s: uec not initial\n", __FUNCTION__);
416 uec_regs = uec->uec_regs;
418 if (duplex == DUPLEX_HALF) {
419 maccfg2 = in_be32(&uec_regs->maccfg2);
420 maccfg2 &= ~MACCFG2_FDX;
421 out_be32(&uec_regs->maccfg2, maccfg2);
424 if (duplex == DUPLEX_FULL) {
425 maccfg2 = in_be32(&uec_regs->maccfg2);
426 maccfg2 |= MACCFG2_FDX;
427 out_be32(&uec_regs->maccfg2, maccfg2);
433 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
435 enet_interface_e enet_if_mode;
436 uec_info_t *uec_info;
442 printf("%s: uec not initial\n", __FUNCTION__);
446 uec_info = uec->uec_info;
447 uec_regs = uec->uec_regs;
448 enet_if_mode = if_mode;
450 maccfg2 = in_be32(&uec_regs->maccfg2);
451 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
453 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
454 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
456 switch (enet_if_mode) {
459 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
462 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
465 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
469 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
470 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
472 case ENET_1000_RGMII_RXID:
473 case ENET_1000_RGMII_ID:
474 case ENET_1000_RGMII:
475 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
479 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
483 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
484 upsmr |= (UPSMR_RPM | UPSMR_R10M);
487 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
491 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
492 upsmr |= (UPSMR_R10M | UPSMR_RMM);
498 out_be32(&uec_regs->maccfg2, maccfg2);
499 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
504 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
506 uint timeout = 0x1000;
509 miimcfg = in_be32(&uec_mii_regs->miimcfg);
510 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
511 out_be32(&uec_mii_regs->miimcfg, miimcfg);
513 /* Wait until the bus is free */
514 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
516 printf("%s: The MII Bus is stuck!", __FUNCTION__);
523 static int init_phy(struct eth_device *dev)
526 uec_mii_t *umii_regs;
527 struct uec_mii_info *mii_info;
528 struct phy_info *curphy;
531 uec = (uec_private_t *)dev->priv;
532 umii_regs = uec->uec_mii_regs;
538 mii_info = malloc(sizeof(*mii_info));
540 printf("%s: Could not allocate mii_info", dev->name);
543 memset(mii_info, 0, sizeof(*mii_info));
545 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
546 mii_info->speed = SPEED_1000;
548 mii_info->speed = SPEED_100;
551 mii_info->duplex = DUPLEX_FULL;
555 mii_info->advertising = (ADVERTISED_10baseT_Half |
556 ADVERTISED_10baseT_Full |
557 ADVERTISED_100baseT_Half |
558 ADVERTISED_100baseT_Full |
559 ADVERTISED_1000baseT_Full);
560 mii_info->autoneg = 1;
561 mii_info->mii_id = uec->uec_info->phy_address;
564 mii_info->mdio_read = &uec_read_phy_reg;
565 mii_info->mdio_write = &uec_write_phy_reg;
567 uec->mii_info = mii_info;
569 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
571 if (init_mii_management_configuration(umii_regs)) {
572 printf("%s: The MII Bus is stuck!", dev->name);
577 /* get info for this PHY */
578 curphy = uec_get_phy_info(uec->mii_info);
580 printf("%s: No PHY found", dev->name);
585 mii_info->phyinfo = curphy;
587 /* Run the commands which initialize the PHY */
589 err = curphy->init(uec->mii_info);
603 static void adjust_link(struct eth_device *dev)
605 uec_private_t *uec = (uec_private_t *)dev->priv;
607 struct uec_mii_info *mii_info = uec->mii_info;
609 extern void change_phy_interface_mode(struct eth_device *dev,
610 enet_interface_e mode);
611 uec_regs = uec->uec_regs;
613 if (mii_info->link) {
614 /* Now we make sure that we can be in full duplex mode.
615 * If not, we operate in half-duplex mode. */
616 if (mii_info->duplex != uec->oldduplex) {
617 if (!(mii_info->duplex)) {
618 uec_set_mac_duplex(uec, DUPLEX_HALF);
619 printf("%s: Half Duplex\n", dev->name);
621 uec_set_mac_duplex(uec, DUPLEX_FULL);
622 printf("%s: Full Duplex\n", dev->name);
624 uec->oldduplex = mii_info->duplex;
627 if (mii_info->speed != uec->oldspeed) {
628 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
629 switch (mii_info->speed) {
633 printf ("switching to rgmii 100\n");
634 /* change phy to rgmii 100 */
635 change_phy_interface_mode(dev,
637 /* change the MAC interface mode */
638 uec_set_mac_if_mode(uec,ENET_100_RGMII);
641 printf ("switching to rgmii 10\n");
642 /* change phy to rgmii 10 */
643 change_phy_interface_mode(dev,
645 /* change the MAC interface mode */
646 uec_set_mac_if_mode(uec,ENET_10_RGMII);
649 printf("%s: Ack,Speed(%d)is illegal\n",
650 dev->name, mii_info->speed);
655 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
656 uec->oldspeed = mii_info->speed;
660 printf("%s: Link is up\n", dev->name);
664 } else { /* if (mii_info->link) */
666 printf("%s: Link is down\n", dev->name);
674 static void phy_change(struct eth_device *dev)
676 uec_private_t *uec = (uec_private_t *)dev->priv;
678 /* Update the link, speed, duplex */
679 uec->mii_info->phyinfo->read_status(uec->mii_info);
681 /* Adjust the interface according to speed */
685 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
686 && !defined(BITBANGMII)
689 * Read a MII PHY register.
694 static int uec_miiphy_read(char *devname, unsigned char addr,
695 unsigned char reg, unsigned short *value)
697 *value = uec_read_phy_reg(devlist[0], addr, reg);
703 * Write a MII PHY register.
708 static int uec_miiphy_write(char *devname, unsigned char addr,
709 unsigned char reg, unsigned short value)
711 uec_write_phy_reg(devlist[0], addr, reg, value);
718 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
725 printf("%s: uec not initial\n", __FUNCTION__);
729 uec_regs = uec->uec_regs;
731 /* if a station address of 0x12345678ABCD, perform a write to
732 MACSTNADDR1 of 0xCDAB7856,
733 MACSTNADDR2 of 0x34120000 */
735 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
736 (mac_addr[3] << 8) | (mac_addr[2]);
737 out_be32(&uec_regs->macstnaddr1, mac_addr1);
739 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
740 out_be32(&uec_regs->macstnaddr2, mac_addr2);
745 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
746 int *threads_num_ret)
748 int num_threads_numerica;
750 switch (threads_num) {
751 case UEC_NUM_OF_THREADS_1:
752 num_threads_numerica = 1;
754 case UEC_NUM_OF_THREADS_2:
755 num_threads_numerica = 2;
757 case UEC_NUM_OF_THREADS_4:
758 num_threads_numerica = 4;
760 case UEC_NUM_OF_THREADS_6:
761 num_threads_numerica = 6;
763 case UEC_NUM_OF_THREADS_8:
764 num_threads_numerica = 8;
767 printf("%s: Bad number of threads value.",
772 *threads_num_ret = num_threads_numerica;
777 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
779 uec_info_t *uec_info;
784 uec_info = uec->uec_info;
786 /* Alloc global Tx parameter RAM page */
787 uec->tx_glbl_pram_offset = qe_muram_alloc(
788 sizeof(uec_tx_global_pram_t),
789 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
790 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
791 qe_muram_addr(uec->tx_glbl_pram_offset);
793 /* Zero the global Tx prameter RAM */
794 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
796 /* Init global Tx parameter RAM */
798 /* TEMODER, RMON statistics disable, one Tx queue */
799 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
802 uec->send_q_mem_reg_offset = qe_muram_alloc(
803 sizeof(uec_send_queue_qd_t),
804 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
805 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
806 qe_muram_addr(uec->send_q_mem_reg_offset);
807 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
809 /* Setup the table with TxBDs ring */
810 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
812 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
813 (u32)(uec->p_tx_bd_ring));
814 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
817 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
818 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
820 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
821 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
823 /* TSTATE, global snooping, big endian, the CSB bus selected */
824 bmrx = BMR_INIT_VALUE;
825 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
828 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
829 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
833 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
834 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
838 uec->thread_dat_tx_offset = qe_muram_alloc(
839 num_threads_tx * sizeof(uec_thread_data_tx_t) +
840 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
842 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
843 qe_muram_addr(uec->thread_dat_tx_offset);
844 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
847 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
851 uec_82xx_address_filtering_pram_t *p_af_pram;
853 /* Allocate global Rx parameter RAM page */
854 uec->rx_glbl_pram_offset = qe_muram_alloc(
855 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
856 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
857 qe_muram_addr(uec->rx_glbl_pram_offset);
859 /* Zero Global Rx parameter RAM */
860 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
862 /* Init global Rx parameter RAM */
863 /* REMODER, Extended feature mode disable, VLAN disable,
864 LossLess flow control disable, Receive firmware statisic disable,
865 Extended address parsing mode disable, One Rx queues,
866 Dynamic maximum/minimum frame length disable, IP checksum check
867 disable, IP address alignment disable
869 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
872 uec->thread_dat_rx_offset = qe_muram_alloc(
873 num_threads_rx * sizeof(uec_thread_data_rx_t),
874 UEC_THREAD_DATA_ALIGNMENT);
875 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
876 qe_muram_addr(uec->thread_dat_rx_offset);
877 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
880 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
882 /* RxRMON base pointer, we don't need it */
883 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
885 /* IntCoalescingPTR, we don't need it, no interrupt */
886 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
888 /* RSTATE, global snooping, big endian, the CSB bus selected */
889 bmrx = BMR_INIT_VALUE;
890 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
893 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
896 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
897 sizeof(uec_rx_bd_queues_entry_t) + \
898 sizeof(uec_rx_prefetched_bds_t),
899 UEC_RX_BD_QUEUES_ALIGNMENT);
900 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
901 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
904 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
905 sizeof(uec_rx_prefetched_bds_t));
906 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
907 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
908 (u32)uec->p_rx_bd_ring);
911 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
913 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
915 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
917 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
919 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
921 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
923 for (i = 0; i < 8; i++) {
924 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
928 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
930 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
932 /* Clear PQ2 style address filtering hash table */
933 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
934 uec->p_rx_glbl_pram->addressfiltering;
936 p_af_pram->iaddr_h = 0;
937 p_af_pram->iaddr_l = 0;
938 p_af_pram->gaddr_h = 0;
939 p_af_pram->gaddr_l = 0;
942 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
943 int thread_tx, int thread_rx)
945 uec_init_cmd_pram_t *p_init_enet_param;
946 u32 init_enet_param_offset;
947 uec_info_t *uec_info;
950 u32 init_enet_offset;
955 uec_info = uec->uec_info;
957 /* Allocate init enet command parameter */
958 uec->init_enet_param_offset = qe_muram_alloc(
959 sizeof(uec_init_cmd_pram_t), 4);
960 init_enet_param_offset = uec->init_enet_param_offset;
961 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
962 qe_muram_addr(uec->init_enet_param_offset);
964 /* Zero init enet command struct */
965 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
967 /* Init the command struct */
968 p_init_enet_param = uec->p_init_enet_param;
969 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
970 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
971 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
972 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
973 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
974 p_init_enet_param->largestexternallookupkeysize = 0;
976 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
977 << ENET_INIT_PARAM_RGF_SHIFT;
978 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
979 << ENET_INIT_PARAM_TGF_SHIFT;
981 /* Init Rx global parameter pointer */
982 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
983 (u32)uec_info->riscRx;
985 /* Init Rx threads */
986 for (i = 0; i < (thread_rx + 1); i++) {
987 if ((snum = qe_get_snum()) < 0) {
988 printf("%s can not get snum\n", __FUNCTION__);
993 init_enet_offset = 0;
995 init_enet_offset = qe_muram_alloc(
996 sizeof(uec_thread_rx_pram_t),
997 UEC_THREAD_RX_PRAM_ALIGNMENT);
1000 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1001 init_enet_offset | (u32)uec_info->riscRx;
1002 p_init_enet_param->rxthread[i] = entry_val;
1005 /* Init Tx global parameter pointer */
1006 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
1007 (u32)uec_info->riscTx;
1009 /* Init Tx threads */
1010 for (i = 0; i < thread_tx; i++) {
1011 if ((snum = qe_get_snum()) < 0) {
1012 printf("%s can not get snum\n", __FUNCTION__);
1016 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
1017 UEC_THREAD_TX_PRAM_ALIGNMENT);
1019 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1020 init_enet_offset | (u32)uec_info->riscTx;
1021 p_init_enet_param->txthread[i] = entry_val;
1024 __asm__ __volatile__("sync");
1026 /* Issue QE command */
1027 command = QE_INIT_TX_RX;
1028 cecr_subblock = ucc_fast_get_qe_cr_subblock(
1029 uec->uec_info->uf_info.ucc_num);
1030 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
1031 init_enet_param_offset);
1036 static int uec_startup(uec_private_t *uec)
1038 uec_info_t *uec_info;
1039 ucc_fast_info_t *uf_info;
1040 ucc_fast_private_t *uccf;
1041 ucc_fast_t *uf_regs;
1046 enet_interface_e enet_interface;
1053 if (!uec || !uec->uec_info) {
1054 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1058 uec_info = uec->uec_info;
1059 uf_info = &(uec_info->uf_info);
1061 /* Check if Rx BD ring len is illegal */
1062 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1063 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1064 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1069 /* Check if Tx BD ring len is illegal */
1070 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1071 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1076 /* Check if MRBLR is illegal */
1077 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
1078 printf("%s: max rx buffer length must be mutliple of 128.\n",
1083 /* Both Rx and Tx are stopped */
1084 uec->grace_stopped_rx = 1;
1085 uec->grace_stopped_tx = 1;
1088 if (ucc_fast_init(uf_info, &uccf)) {
1089 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1096 /* Convert the Tx threads number */
1097 if (uec_convert_threads_num(uec_info->num_threads_tx,
1102 /* Convert the Rx threads number */
1103 if (uec_convert_threads_num(uec_info->num_threads_rx,
1108 uf_regs = uccf->uf_regs;
1110 /* UEC register is following UCC fast registers */
1111 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1113 /* Save the UEC register pointer to UEC private struct */
1114 uec->uec_regs = uec_regs;
1116 /* Init UPSMR, enable hardware statistics (UCC) */
1117 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1119 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1120 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1122 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1123 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1125 /* Setup MAC interface mode */
1126 uec_set_mac_if_mode(uec, uec_info->enet_interface);
1128 /* Setup MII management base */
1129 #ifndef CONFIG_eTSEC_MDIO_BUS
1130 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1132 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1135 /* Setup MII master clock source */
1136 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1139 utbipar = in_be32(&uec_regs->utbipar);
1140 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1141 enet_interface = uec->uec_info->enet_interface;
1142 if (enet_interface == ENET_1000_TBI ||
1143 enet_interface == ENET_1000_RTBI) {
1144 utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num)
1145 << UTBIPAR_PHY_ADDRESS_SHIFT;
1147 utbipar |= (0x10 + uec_info->uf_info.ucc_num)
1148 << UTBIPAR_PHY_ADDRESS_SHIFT;
1151 out_be32(&uec_regs->utbipar, utbipar);
1153 /* Allocate Tx BDs */
1154 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1155 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1156 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1157 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1158 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1159 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1162 align = UEC_TX_BD_RING_ALIGNMENT;
1163 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1164 if (uec->tx_bd_ring_offset != 0) {
1165 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1169 /* Zero all of Tx BDs */
1170 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1172 /* Allocate Rx BDs */
1173 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1174 align = UEC_RX_BD_RING_ALIGNMENT;
1175 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1176 if (uec->rx_bd_ring_offset != 0) {
1177 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1181 /* Zero all of Rx BDs */
1182 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1184 /* Allocate Rx buffer */
1185 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1186 align = UEC_RX_DATA_BUF_ALIGNMENT;
1187 uec->rx_buf_offset = (u32)malloc(length + align);
1188 if (uec->rx_buf_offset != 0) {
1189 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1193 /* Zero all of the Rx buffer */
1194 memset((void *)(uec->rx_buf_offset), 0, length + align);
1196 /* Init TxBD ring */
1197 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1200 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1202 BD_STATUS_SET(bd, 0);
1203 BD_LENGTH_SET(bd, 0);
1206 BD_STATUS_SET((--bd), TxBD_WRAP);
1208 /* Init RxBD ring */
1209 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1211 buf = uec->p_rx_buf;
1212 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1213 BD_DATA_SET(bd, buf);
1214 BD_LENGTH_SET(bd, 0);
1215 BD_STATUS_SET(bd, RxBD_EMPTY);
1216 buf += MAX_RXBUF_LEN;
1219 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1221 /* Init global Tx parameter RAM */
1222 uec_init_tx_parameter(uec, num_threads_tx);
1224 /* Init global Rx parameter RAM */
1225 uec_init_rx_parameter(uec, num_threads_rx);
1227 /* Init ethernet Tx and Rx parameter command */
1228 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1230 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1237 static int uec_init(struct eth_device* dev, bd_t *bd)
1241 struct phy_info *curphy;
1243 uec = (uec_private_t *)dev->priv;
1245 if (uec->the_first_run == 0) {
1246 err = init_phy(dev);
1248 printf("%s: Cannot initialize PHY, aborting.\n",
1253 curphy = uec->mii_info->phyinfo;
1255 if (curphy->config_aneg) {
1256 err = curphy->config_aneg(uec->mii_info);
1258 printf("%s: Can't negotiate PHY\n", dev->name);
1263 /* Give PHYs up to 5 sec to report a link */
1266 err = curphy->read_status(uec->mii_info);
1268 } while (((i-- > 0) && !uec->mii_info->link) || err);
1271 printf("warning: %s: timeout on PHY link\n", dev->name);
1273 uec->the_first_run = 1;
1276 /* Set up the MAC address */
1277 if (dev->enetaddr[0] & 0x01) {
1278 printf("%s: MacAddress is multcast address\n",
1282 uec_set_mac_address(uec, dev->enetaddr);
1285 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1287 printf("%s: cannot enable UEC device\n", dev->name);
1293 return (uec->mii_info->link ? 0 : -1);
1296 static void uec_halt(struct eth_device* dev)
1298 uec_private_t *uec = (uec_private_t *)dev->priv;
1299 uec_stop(uec, COMM_DIR_RX_AND_TX);
1302 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1305 ucc_fast_private_t *uccf;
1306 volatile qe_bd_t *bd;
1311 uec = (uec_private_t *)dev->priv;
1315 /* Find an empty TxBD */
1316 for (i = 0; bd->status & TxBD_READY; i++) {
1318 printf("%s: tx buffer not ready\n", dev->name);
1324 BD_DATA_SET(bd, buf);
1325 BD_LENGTH_SET(bd, len);
1326 status = bd->status;
1328 status |= (TxBD_READY | TxBD_LAST);
1329 BD_STATUS_SET(bd, status);
1331 /* Tell UCC to transmit the buffer */
1332 ucc_fast_transmit_on_demand(uccf);
1334 /* Wait for buffer to be transmitted */
1335 for (i = 0; bd->status & TxBD_READY; i++) {
1337 printf("%s: tx error\n", dev->name);
1342 /* Ok, the buffer be transimitted */
1343 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1350 static int uec_recv(struct eth_device* dev)
1352 uec_private_t *uec = dev->priv;
1353 volatile qe_bd_t *bd;
1359 status = bd->status;
1361 while (!(status & RxBD_EMPTY)) {
1362 if (!(status & RxBD_ERROR)) {
1364 len = BD_LENGTH(bd);
1365 NetReceive(data, len);
1367 printf("%s: Rx error\n", dev->name);
1370 BD_LENGTH_SET(bd, 0);
1371 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1372 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1373 status = bd->status;
1380 int uec_initialize(int index)
1382 struct eth_device *dev;
1385 uec_info_t *uec_info;
1388 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1391 memset(dev, 0, sizeof(struct eth_device));
1393 /* Allocate the UEC private struct */
1394 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1398 memset(uec, 0, sizeof(uec_private_t));
1400 /* Init UEC private struct, they come from board.h */
1403 #ifdef CONFIG_UEC_ETH1
1404 uec_info = ð1_uec_info;
1406 } else if (index == 1) {
1407 #ifdef CONFIG_UEC_ETH2
1408 uec_info = ð2_uec_info;
1410 } else if (index == 2) {
1411 #ifdef CONFIG_UEC_ETH3
1412 uec_info = ð3_uec_info;
1414 } else if (index == 3) {
1415 #ifdef CONFIG_UEC_ETH4
1416 uec_info = ð4_uec_info;
1419 printf("%s: index is illegal.\n", __FUNCTION__);
1423 devlist[index] = dev;
1425 uec->uec_info = uec_info;
1427 sprintf(dev->name, "FSL UEC%d", index);
1429 dev->priv = (void *)uec;
1430 dev->init = uec_init;
1431 dev->halt = uec_halt;
1432 dev->send = uec_send;
1433 dev->recv = uec_recv;
1435 /* Clear the ethnet address */
1436 for (i = 0; i < 6; i++)
1437 dev->enetaddr[i] = 0;
1441 err = uec_startup(uec);
1443 printf("%s: Cannot configure net device, aborting.",dev->name);
1447 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1448 && !defined(BITBANGMII)
1449 miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);