2 * Copyright (C) 2005 Freescale Semiconductor, Inc.
4 * Author: Shlomi Gridish
6 * Description: UCC GETH Driver -- PHY handling
8 * Based on 8260_io/fcc_enet.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
20 #include "asm/errno.h"
21 #include "asm/immap_qe.h"
29 #define ugphy_printk(format, arg...) \
30 printf(format "\n", ## arg)
32 #define ugphy_dbg(format, arg...) \
33 ugphy_printk(format , ## arg)
34 #define ugphy_err(format, arg...) \
35 ugphy_printk(format , ## arg)
36 #define ugphy_info(format, arg...) \
37 ugphy_printk(format , ## arg)
38 #define ugphy_warn(format, arg...) \
39 ugphy_printk(format , ## arg)
41 #ifdef UEC_VERBOSE_DEBUG
42 #define ugphy_vdbg ugphy_dbg
44 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
45 #endif /* UEC_VERBOSE_DEBUG */
47 /*--------------------------------------------------------------------+
48 * Fixed PHY (PHY-less) support for Ethernet Ports.
50 * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
51 *--------------------------------------------------------------------*/
54 * Some boards do not have a PHY for each ethernet port. These ports are known
55 * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
56 * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
57 * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
58 * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
59 * speed and duplex should be for the port.
61 * Example board header configuration file:
62 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
63 * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
65 * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
66 * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
67 * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
68 * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
70 * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
71 * {name, speed, duplex},
73 * #define CONFIG_SYS_FIXED_PHY_PORTS \
74 * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
75 * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
78 #ifndef CONFIG_FIXED_PHY
79 #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
82 #ifndef CONFIG_SYS_FIXED_PHY_PORTS
83 #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
86 struct fixed_phy_port {
87 char name[NAMESIZE]; /* ethernet port name */
88 unsigned int speed; /* specified speed 10,100 or 1000 */
89 unsigned int duplex; /* specified duplex FULL or HALF */
92 static const struct fixed_phy_port fixed_phy_port[] = {
93 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
96 /*--------------------------------------------------------------------+
97 * BitBang MII support for ethernet ports
99 * Based from MPC8560ADS implementation
100 *--------------------------------------------------------------------*/
102 * Example board header file to define bitbang ethernet ports:
104 * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
105 * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
107 #ifndef CONFIG_SYS_BITBANG_PHY_PORTS
108 #define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
111 #if defined(CONFIG_BITBANGMII)
112 static const char *bitbang_phy_port[] = {
113 CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
115 #endif /* CONFIG_BITBANGMII */
117 static void config_genmii_advert (struct uec_mii_info *mii_info);
118 static void genmii_setup_forced (struct uec_mii_info *mii_info);
119 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
120 static int gbit_config_aneg (struct uec_mii_info *mii_info);
121 static int genmii_config_aneg (struct uec_mii_info *mii_info);
122 static int genmii_update_link (struct uec_mii_info *mii_info);
123 static int genmii_read_status (struct uec_mii_info *mii_info);
124 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
125 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
127 /* Write value to the PHY for this device to the register at regnum, */
128 /* waiting until the write is done before it returns. All PHY */
129 /* configuration has to be done through the TSEC1 MIIM regs */
130 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
132 uec_private_t *ugeth = (uec_private_t *) dev->priv;
134 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
138 #if defined(CONFIG_BITBANGMII)
141 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
142 if (strncmp(dev->name, bitbang_phy_port[i],
143 sizeof(dev->name)) == 0) {
144 (void)bb_miiphy_write(NULL, mii_id, regnum, value);
148 #endif /* CONFIG_BITBANGMII */
150 ug_regs = ugeth->uec_mii_regs;
152 /* Stop the MII management read cycle */
153 out_be32 (&ug_regs->miimcom, 0);
154 /* Setting up the MII Mangement Address Register */
155 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
156 out_be32 (&ug_regs->miimadd, tmp_reg);
158 /* Setting up the MII Mangement Control Register with the value */
159 out_be32 (&ug_regs->miimcon, (u32) value);
162 /* Wait till MII management write is complete */
163 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
166 /* Reads from register regnum in the PHY for device dev, */
167 /* returning the value. Clears miimcom first. All PHY */
168 /* configuration has to be done through the TSEC1 MIIM regs */
169 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
171 uec_private_t *ugeth = (uec_private_t *) dev->priv;
173 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
178 #if defined(CONFIG_BITBANGMII)
181 for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
182 if (strncmp(dev->name, bitbang_phy_port[i],
183 sizeof(dev->name)) == 0) {
184 (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
188 #endif /* CONFIG_BITBANGMII */
190 ug_regs = ugeth->uec_mii_regs;
192 /* Setting up the MII Mangement Address Register */
193 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
194 out_be32 (&ug_regs->miimadd, tmp_reg);
196 /* clear MII management command cycle */
197 out_be32 (&ug_regs->miimcom, 0);
200 /* Perform an MII management read cycle */
201 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
203 /* Wait till MII management write is complete */
204 while ((in_be32 (&ug_regs->miimind)) &
205 (MIIMIND_NOT_VALID | MIIMIND_BUSY));
207 /* Read MII management status */
208 value = (u16) in_be32 (&ug_regs->miimstat);
211 ("read wrong value : mii_id %d,mii_reg %d, base %08x",
212 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
217 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
219 if (mii_info->phyinfo->ack_interrupt)
220 mii_info->phyinfo->ack_interrupt (mii_info);
223 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
226 mii_info->interrupts = interrupts;
227 if (mii_info->phyinfo->config_intr)
228 mii_info->phyinfo->config_intr (mii_info);
231 /* Writes MII_ADVERTISE with the appropriate values, after
232 * sanitizing advertise to make sure only supported features
235 static void config_genmii_advert (struct uec_mii_info *mii_info)
240 /* Only allow advertising what this PHY supports */
241 mii_info->advertising &= mii_info->phyinfo->features;
242 advertise = mii_info->advertising;
244 /* Setup standard advertisement */
245 adv = phy_read (mii_info, PHY_ANAR);
246 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
247 if (advertise & ADVERTISED_10baseT_Half)
248 adv |= ADVERTISE_10HALF;
249 if (advertise & ADVERTISED_10baseT_Full)
250 adv |= ADVERTISE_10FULL;
251 if (advertise & ADVERTISED_100baseT_Half)
252 adv |= ADVERTISE_100HALF;
253 if (advertise & ADVERTISED_100baseT_Full)
254 adv |= ADVERTISE_100FULL;
255 phy_write (mii_info, PHY_ANAR, adv);
258 static void genmii_setup_forced (struct uec_mii_info *mii_info)
261 u32 features = mii_info->phyinfo->features;
263 ctrl = phy_read (mii_info, PHY_BMCR);
265 ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
266 PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
267 ctrl |= PHY_BMCR_RESET;
269 switch (mii_info->speed) {
271 if (features & (SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full)) {
273 ctrl |= PHY_BMCR_1000_MBPS;
276 mii_info->speed = SPEED_100;
278 if (features & (SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full)) {
280 ctrl |= PHY_BMCR_100_MBPS;
283 mii_info->speed = SPEED_10;
285 if (features & (SUPPORTED_10baseT_Half
286 | SUPPORTED_10baseT_Full))
288 default: /* Unsupported speed! */
289 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
293 phy_write (mii_info, PHY_BMCR, ctrl);
296 /* Enable and Restart Autonegotiation */
297 static void genmii_restart_aneg (struct uec_mii_info *mii_info)
301 ctl = phy_read (mii_info, PHY_BMCR);
302 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
303 phy_write (mii_info, PHY_BMCR, ctl);
306 static int gbit_config_aneg (struct uec_mii_info *mii_info)
311 if (mii_info->autoneg) {
312 /* Configure the ADVERTISE register */
313 config_genmii_advert (mii_info);
314 advertise = mii_info->advertising;
316 adv = phy_read (mii_info, MII_1000BASETCONTROL);
317 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
318 MII_1000BASETCONTROL_HALFDUPLEXCAP);
319 if (advertise & SUPPORTED_1000baseT_Half)
320 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
321 if (advertise & SUPPORTED_1000baseT_Full)
322 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
323 phy_write (mii_info, MII_1000BASETCONTROL, adv);
325 /* Start/Restart aneg */
326 genmii_restart_aneg (mii_info);
328 genmii_setup_forced (mii_info);
333 static int marvell_config_aneg (struct uec_mii_info *mii_info)
335 /* The Marvell PHY has an errata which requires
336 * that certain registers get written in order
337 * to restart autonegotiation */
338 phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
340 phy_write (mii_info, 0x1d, 0x1f);
341 phy_write (mii_info, 0x1e, 0x200c);
342 phy_write (mii_info, 0x1d, 0x5);
343 phy_write (mii_info, 0x1e, 0);
344 phy_write (mii_info, 0x1e, 0x100);
346 gbit_config_aneg (mii_info);
351 static int genmii_config_aneg (struct uec_mii_info *mii_info)
353 if (mii_info->autoneg) {
354 /* Speed up the common case, if link is already up, speed and
355 duplex match, skip auto neg as it already matches */
356 if (!genmii_read_status(mii_info) && mii_info->link)
357 if (mii_info->duplex == DUPLEX_FULL &&
358 mii_info->speed == SPEED_100)
359 if (mii_info->advertising &
360 ADVERTISED_100baseT_Full)
363 config_genmii_advert (mii_info);
364 genmii_restart_aneg (mii_info);
366 genmii_setup_forced (mii_info);
371 static int genmii_update_link (struct uec_mii_info *mii_info)
375 /* Status is read once to clear old link state */
376 phy_read (mii_info, PHY_BMSR);
379 * Wait if the link is up, and autonegotiation is in progress
380 * (ie - we're capable and it's not done)
382 status = phy_read(mii_info, PHY_BMSR);
383 if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
384 && !(status & PHY_BMSR_AUTN_COMP)) {
387 while (!(status & PHY_BMSR_AUTN_COMP)) {
391 if (i > UGETH_AN_TIMEOUT) {
397 udelay(1000); /* 1 ms */
398 status = phy_read(mii_info, PHY_BMSR);
402 if (status & PHY_BMSR_LS)
411 static int genmii_read_status (struct uec_mii_info *mii_info)
416 /* Update the link, but return if there
418 err = genmii_update_link (mii_info);
422 if (mii_info->autoneg) {
423 status = phy_read(mii_info, MII_1000BASETSTATUS);
425 if (status & (LPA_1000FULL | LPA_1000HALF)) {
426 mii_info->speed = SPEED_1000;
427 if (status & LPA_1000FULL)
428 mii_info->duplex = DUPLEX_FULL;
430 mii_info->duplex = DUPLEX_HALF;
432 status = phy_read(mii_info, PHY_ANLPAR);
434 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
435 mii_info->duplex = DUPLEX_FULL;
437 mii_info->duplex = DUPLEX_HALF;
438 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
439 mii_info->speed = SPEED_100;
441 mii_info->speed = SPEED_10;
445 /* On non-aneg, we assume what we put in BMCR is the speed,
446 * though magic-aneg shouldn't prevent this case from occurring
452 static int bcm_init(struct uec_mii_info *mii_info)
454 struct eth_device *edev = mii_info->dev;
455 uec_private_t *uec = edev->priv;
457 gbit_config_aneg(mii_info);
459 if ((uec->uec_info->enet_interface_type == RGMII_RXID) &&
460 (uec->uec_info->speed == 1000)) {
464 /* Wait for aneg to complete. */
466 val = phy_read(mii_info, PHY_BMSR);
467 while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
469 /* Set RDX clk delay. */
470 phy_write(mii_info, 0x18, 0x7 | (7 << 12));
472 val = phy_read(mii_info, 0x18);
473 /* Set RDX-RXC skew. */
475 val |= (7 | (7 << 12));
476 /* Write bits 14:0. */
478 phy_write(mii_info, 0x18, val);
484 static int marvell_init(struct uec_mii_info *mii_info)
486 struct eth_device *edev = mii_info->dev;
487 uec_private_t *uec = edev->priv;
488 enum enet_interface_type iface = uec->uec_info->enet_interface_type;
489 int speed = uec->uec_info->speed;
491 if ((speed == 1000) &&
492 (iface == RGMII_ID ||
493 iface == RGMII_RXID ||
494 iface == RGMII_TXID)) {
497 temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
498 if (iface == RGMII_ID) {
499 temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
500 } else if (iface == RGMII_RXID) {
501 temp &= ~MII_M1111_TX_DELAY;
502 temp |= MII_M1111_RX_DELAY;
503 } else if (iface == RGMII_TXID) {
504 temp &= ~MII_M1111_RX_DELAY;
505 temp |= MII_M1111_TX_DELAY;
507 phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
509 temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
510 temp &= ~MII_M1111_HWCFG_MODE_MASK;
511 temp |= MII_M1111_HWCFG_MODE_RGMII;
512 phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
514 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
520 static int marvell_read_status (struct uec_mii_info *mii_info)
525 /* Update the link, but return if there
527 err = genmii_update_link (mii_info);
531 /* If the link is up, read the speed and duplex */
532 /* If we aren't autonegotiating, assume speeds
534 if (mii_info->autoneg && mii_info->link) {
537 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
539 /* Get the duplexity */
540 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
541 mii_info->duplex = DUPLEX_FULL;
543 mii_info->duplex = DUPLEX_HALF;
546 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
548 case MII_M1011_PHY_SPEC_STATUS_1000:
549 mii_info->speed = SPEED_1000;
551 case MII_M1011_PHY_SPEC_STATUS_100:
552 mii_info->speed = SPEED_100;
555 mii_info->speed = SPEED_10;
564 static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
566 /* Clear the interrupts by reading the reg */
567 phy_read (mii_info, MII_M1011_IEVENT);
572 static int marvell_config_intr (struct uec_mii_info *mii_info)
574 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
575 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
577 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
582 static int dm9161_init (struct uec_mii_info *mii_info)
585 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
587 /* PHY and MAC connect */
588 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
591 phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
593 config_genmii_advert (mii_info);
594 /* Start/restart aneg */
595 genmii_config_aneg (mii_info);
600 static int dm9161_config_aneg (struct uec_mii_info *mii_info)
605 static int dm9161_read_status (struct uec_mii_info *mii_info)
610 /* Update the link, but return if there was an error */
611 err = genmii_update_link (mii_info);
614 /* If the link is up, read the speed and duplex
615 If we aren't autonegotiating assume speeds are as set */
616 if (mii_info->autoneg && mii_info->link) {
617 status = phy_read (mii_info, MII_DM9161_SCSR);
618 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
619 mii_info->speed = SPEED_100;
621 mii_info->speed = SPEED_10;
623 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
624 mii_info->duplex = DUPLEX_FULL;
626 mii_info->duplex = DUPLEX_HALF;
632 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
634 /* Clear the interrupt by reading the reg */
635 phy_read (mii_info, MII_DM9161_INTR);
640 static int dm9161_config_intr (struct uec_mii_info *mii_info)
642 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
643 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
645 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
650 static void dm9161_close (struct uec_mii_info *mii_info)
654 static int fixed_phy_aneg (struct uec_mii_info *mii_info)
656 mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
660 static int fixed_phy_read_status (struct uec_mii_info *mii_info)
664 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
665 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
666 strlen(mii_info->dev->name)) == 0) {
667 mii_info->speed = fixed_phy_port[i].speed;
668 mii_info->duplex = fixed_phy_port[i].duplex;
669 mii_info->link = 1; /* Link is always UP */
677 static int smsc_config_aneg (struct uec_mii_info *mii_info)
682 static int smsc_read_status (struct uec_mii_info *mii_info)
687 /* Update the link, but return if there
689 err = genmii_update_link (mii_info);
693 /* If the link is up, read the speed and duplex */
694 /* If we aren't autonegotiating, assume speeds
696 if (mii_info->autoneg && mii_info->link) {
699 status = phy_read (mii_info, 0x1f);
700 val = (status & 0x1c) >> 2;
704 mii_info->duplex = DUPLEX_HALF;
705 mii_info->speed = SPEED_10;
708 mii_info->duplex = DUPLEX_FULL;
709 mii_info->speed = SPEED_10;
712 mii_info->duplex = DUPLEX_HALF;
713 mii_info->speed = SPEED_100;
716 mii_info->duplex = DUPLEX_FULL;
717 mii_info->speed = SPEED_100;
726 static struct phy_info phy_info_dm9161 = {
727 .phy_id = 0x0181b880,
728 .phy_id_mask = 0x0ffffff0,
729 .name = "Davicom DM9161E",
731 .config_aneg = dm9161_config_aneg,
732 .read_status = dm9161_read_status,
733 .close = dm9161_close,
736 static struct phy_info phy_info_dm9161a = {
737 .phy_id = 0x0181b8a0,
738 .phy_id_mask = 0x0ffffff0,
739 .name = "Davicom DM9161A",
740 .features = MII_BASIC_FEATURES,
742 .config_aneg = dm9161_config_aneg,
743 .read_status = dm9161_read_status,
744 .ack_interrupt = dm9161_ack_interrupt,
745 .config_intr = dm9161_config_intr,
746 .close = dm9161_close,
749 static struct phy_info phy_info_marvell = {
750 .phy_id = 0x01410c00,
751 .phy_id_mask = 0xffffff00,
752 .name = "Marvell 88E11x1",
753 .features = MII_GBIT_FEATURES,
754 .init = &marvell_init,
755 .config_aneg = &marvell_config_aneg,
756 .read_status = &marvell_read_status,
757 .ack_interrupt = &marvell_ack_interrupt,
758 .config_intr = &marvell_config_intr,
761 static struct phy_info phy_info_bcm5481 = {
762 .phy_id = 0x0143bca0,
763 .phy_id_mask = 0xffffff0,
764 .name = "Broadcom 5481",
765 .features = MII_GBIT_FEATURES,
766 .read_status = genmii_read_status,
770 static struct phy_info phy_info_fixedphy = {
771 .phy_id = CONFIG_FIXED_PHY,
772 .phy_id_mask = CONFIG_FIXED_PHY,
774 .config_aneg = fixed_phy_aneg,
775 .read_status = fixed_phy_read_status,
778 static struct phy_info phy_info_smsclan8700 = {
779 .phy_id = 0x0007c0c0,
780 .phy_id_mask = 0xfffffff0,
781 .name = "SMSC LAN8700",
782 .features = MII_BASIC_FEATURES,
783 .config_aneg = smsc_config_aneg,
784 .read_status = smsc_read_status,
787 static struct phy_info phy_info_genmii = {
788 .phy_id = 0x00000000,
789 .phy_id_mask = 0x00000000,
790 .name = "Generic MII",
791 .features = MII_BASIC_FEATURES,
792 .config_aneg = genmii_config_aneg,
793 .read_status = genmii_read_status,
796 static struct phy_info *phy_info[] = {
801 &phy_info_smsclan8700,
807 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
809 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
812 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
814 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
817 /* Use the PHY ID registers to determine what type of PHY is attached
818 * to device dev. return a struct phy_info structure describing that PHY
820 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
825 struct phy_info *theInfo = NULL;
827 /* Grab the bits from PHYIR1, and put them in the upper half */
828 phy_reg = phy_read (mii_info, PHY_PHYIDR1);
829 phy_ID = (phy_reg & 0xffff) << 16;
831 /* Grab the bits from PHYIR2, and put them in the lower half */
832 phy_reg = phy_read (mii_info, PHY_PHYIDR2);
833 phy_ID |= (phy_reg & 0xffff);
835 /* loop through all the known PHY types, and find one that */
836 /* matches the ID we read from the PHY. */
837 for (i = 0; phy_info[i]; i++)
838 if (phy_info[i]->phy_id ==
839 (phy_ID & phy_info[i]->phy_id_mask)) {
840 theInfo = phy_info[i];
844 /* This shouldn't happen, as we have generic PHY support */
845 if (theInfo == NULL) {
846 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
849 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
855 void marvell_phy_interface_mode (struct eth_device *dev,
856 enet_interface_type_e type,
860 uec_private_t *uec = (uec_private_t *) dev->priv;
861 struct uec_mii_info *mii_info;
864 if (!uec->mii_info) {
865 printf ("%s: the PHY not initialized\n", __FUNCTION__);
868 mii_info = uec->mii_info;
872 phy_write (mii_info, 0x00, 0x9140);
873 phy_write (mii_info, 0x1d, 0x001f);
874 phy_write (mii_info, 0x1e, 0x200c);
875 phy_write (mii_info, 0x1d, 0x0005);
876 phy_write (mii_info, 0x1e, 0x0000);
877 phy_write (mii_info, 0x1e, 0x0100);
878 phy_write (mii_info, 0x09, 0x0e00);
879 phy_write (mii_info, 0x04, 0x01e1);
880 phy_write (mii_info, 0x00, 0x9140);
881 phy_write (mii_info, 0x00, 0x1000);
883 phy_write (mii_info, 0x00, 0x2900);
884 phy_write (mii_info, 0x14, 0x0cd2);
885 phy_write (mii_info, 0x00, 0xa100);
886 phy_write (mii_info, 0x09, 0x0000);
887 phy_write (mii_info, 0x1b, 0x800b);
888 phy_write (mii_info, 0x04, 0x05e1);
889 phy_write (mii_info, 0x00, 0xa100);
890 phy_write (mii_info, 0x00, 0x2100);
892 } else if (speed == 10) {
893 phy_write (mii_info, 0x14, 0x8e40);
894 phy_write (mii_info, 0x1b, 0x800b);
895 phy_write (mii_info, 0x14, 0x0c82);
896 phy_write (mii_info, 0x00, 0x8100);
901 /* handle 88e1111 rev.B2 erratum 5.6 */
902 if (mii_info->autoneg) {
903 status = phy_read (mii_info, PHY_BMCR);
904 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
906 /* now the B2 will correctly report autoneg completion status */
909 void change_phy_interface_mode (struct eth_device *dev,
910 enet_interface_type_e type, int speed)
912 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
913 marvell_phy_interface_mode (dev, type, speed);